|
EDA365欢迎您!
您需要 登录 才可以下载或查看,没有帐号?注册
x
我在做数模混合仿真的时候,在config中调用模拟电路和数字模块的symble,但是在进行display partition>all active时,系统报错:
1 L4 \+ ]! r E; }\o *SYSERR: Unable to hdbBind for inst I15 in cell Module tiadc, lib design, view schematic, configViewString spectre spice verilog verilogams behavioral functional schematic veriloga vhdl vhdlams hdl system verilogNetlist cmos.sch cmos_sch ahdl.
6 ~9 }2 H% ]: V# y$ m0 m2 p6 Y, E! E: w\o *USRERR: Selected context view string 'spectre spice verilog verilogams behavioral functional schematic veriloga vhdl vhdlams hdl system verilogNetlist cmos.sch cmos_sch ahdl'& k* t0 @. F7 V, b; F: S
\o offers no suitable view for inst I15 referencing placed master design.add_and_mult.symbol
. c8 S% {: M* {0 \, L2 r2 _+ `\o in cell Module tiadc, lib design, view schematic, configViewString spectre spice verilog verilogams behavioral functional schematic veriloga vhdl vhdlams hdl system verilogNetlist cmos.sch cmos_sch ahdl.. V! d( s! g; Y& {. z) `/ b% W5 q/ b; G
\o Please check HDB configuration or library setup.
; W2 c3 [) O7 Q0 j3 O# B0 v# ?* F* a\o *USRERR: Selected context view string 'functional'" W: P5 a8 E3 z) E( b V" u
\o offers no suitable view for inst I14 referencing placed master design.average.symbol1 U" d$ `; n% x' T' N. t- m$ p( B4 r
\o in cell Module tiadc, lib design, view schematic, configViewString spectre spice verilog verilogams behavioral functional schematic veriloga vhdl vhdlams hdl system verilogNetlist cmos.sch cmos_sch ahdl.
/ u8 K/ J0 p( Z3 A$ }5 g2 I\o Please check HDB configuration or library setup.
# q( x# h1 k: S! \* Q2 |\o *USRERR: Selected context view string 'functional'
$ o9 o0 _* O$ q" l\o offers no suitable view for inst I12 referencing placed master design.unit2.symbol
/ l( p, e5 ~9 w6 a4 ^( Q% b" r\o in cell Module tiadc, lib design, view schematic, configViewString spectre spice verilog verilogams behavioral functional schematic veriloga vhdl vhdlams hdl system verilogNetlist cmos.sch cmos_sch ahdl.
6 E2 e; V3 ?& N! |' t8 ]( ?\o Please check HDB configuration or library setup.
5 C' Q! H$ y! d; w\o *USRERR: Selected context view string 'functional'
; E+ s& p# ^! q& g1 T# N\o offers no suitable view for inst I11 referencing placed master design.unit1.symbol6 v+ B1 p( j. K, N
\o in cell Module tiadc, lib design, view schematic, configViewString spectre spice verilog verilogams behavioral functional schematic veriloga vhdl vhdlams hdl system verilogNetlist cmos.sch cmos_sch ahdl.3 f: l- o6 s2 L7 H& _0 a9 X$ Q
\o Please check HDB configuration or library setup.
% g7 G4 X9 _- f2 z( l. O! r% q& Q\o *USRERR: Selected context view string 'functional'4 i9 z7 k* K6 F8 T' [
\o offers no suitable view for inst I4 referencing placed master design.encode.symbol9 @9 [- N5 |6 @' ?
\o in cell Module tiadc, lib design, view schematic, configViewString spectre spice verilog verilogams behavioral functional schematic veriloga vhdl vhdlams hdl system verilogNetlist cmos.sch cmos_sch ahdl.
5 k! C ^ `+ ~( W! L p\o Please check HDB configuration or library setup., c) T0 _# h" V
\o *USRERR: Selected context view string 'functional'
& k0 W# |- o* T% s" }+ K0 o* B. I\o offers no suitable view for inst I2 referencing placed master design.encode.symbol, i& Q8 }: { \/ {2 b
\o in cell Module tiadc, lib design, view schematic, configViewString spectre spice verilog verilogams behavioral functional schematic veriloga vhdl vhdlams hdl system verilogNetlist cmos.sch cmos_sch ahdl.
- {6 \! N0 v. `: g( Z# { e\o Please check HDB configuration or library setup.
; f( ?: S! Q" n8 B5 {3 m5 ]\e *Error* Failed to partition the design.; y+ H' x T6 p& M8 h. M+ |
\e ( [7 F& j6 e8 p
\e *Error* mspDisplayPartition: Failed to create network. v- ~7 a, \. I" b% v" ]4 z
* B- F4 \1 ~3 S/ Q+ H0 F' c这是什么问题啊?求大神帮忙解决一下,鄙人不甚感激!!!( _ a1 j4 I; t/ M' v5 r
|
|