标题: 关于在capture cis 生成网表后导入PADS LAYOUT 的报错。请不吝赐教。 [打印本页] 作者: wanghf 时间: 2008-9-2 10:28 标题: 关于在capture cis 生成网表后导入PADS LAYOUT 的报错。请不吝赐教。 我在生成网表后，导入pads layout， 结果报告如下错误：) Z% l2 J2 K- R2 l$ n2 i
Can't find part Type item < XTAL_HC49SMT >% r4 T3 _% {9 `, o5 b
Y1 XTAL_HC49SMT1 ^0 I5 |# c4 z2 O/ T6 ?
Can't find part Type item < XTAL_HC49SMT >& Q+ S4 q8 L, B, d) h
Y2 XTAL_HC49SMT 2 ]+ ~! ?. A2 O; WCan't find part Type item < XTAL_HC49SMT > & k' V9 f, R9 ~0 i3 C, FY3 XTAL_HC49SMT ! c# {& L, ?1 m; V; _7 e' C*Part name not found U13 / ^3 B$ Q3 w7 m, rU13.1 R9.1 C45.2 R13.2 R14.1 5 c5 }% Q( N8 P, H*Bad *CONNECTION* ascii data format, nets must contain more than one pin. Signal N1356420 1 t5 i* I ?' I( o2 c*Bad *CONNECTION* ascii data format, nets must contain more than one pin. Signal XT2_PHY 0 u7 ?. N$ U$ M! V0 D*Bad *CONNECTION* ascii data format, nets must contain more than one pin. Signal USB_D+24 Y6 @2 ]# A# V2 o6 r
*Part name not found Y1* a$ C( v# m/ p
Y1.2 U6.1 C28.1 J3.1 J4.1 J5.1 1 I+ W, {' E2 b* I" _7 F* M*Bad *CONNECTION* ascii data format, nets must contain more than one pin. Signal OSC1- i8 }# B* H; m' G+ d/ D
*Bad *CONNECTION* ascii data format, nets must contain more than one pin. Signal CRS_PHY" v6 {* M! `' Q- x; Z5 c- e
*Part name not found Y2) v" y/ Q, }% ]4 E& Q4 L1 N
U5.34 Y2.2 C41.2" C A8 Q- l: K4 p& p2 H
*Bad *CONNECTION* ascii data format, nets must contain more than one pin. Signal RTCK1( U1 Z& t3 Q7 E$ Z. [9 I! \. o7 N
*Bad *CONNECTION* ascii data format, nets must contain more than one pin. Signal VDD_PHY ! Y; w F& U- ?. y* c*Bad *CONNECTION* ascii data format, nets must contain more than one pin. Signal TXD1_PHY E( A9 P- m8 f. \*Bad *CONNECTION* ascii data format, nets must contain more than one pin. Signal USB_OTG_ID! n6 V0 z+ W% M
除了上述报错元件不能导入，可以导入其它元件。我的部分PCB封装在自己建的pads库里，还用了些常用的自带库。请问# K M4 M7 ]) ~! x. h. \
这些错是什么原因造成的？我看了一天了也没头绪。 G6 Z; A- L$ j5 Y `多谢各位看完。 0 G: V: b b5 t `6 p8 S我会把整个设计放在附件里。- {( O" u5 `; f" L, z7 A. F/ r
再谢。
我已经把封装改好了。