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本帖最后由 lvsy 于 2014-4-16 10:05 编辑
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可以！对于Altera的FPGA，JTAG接口不是VCCIO供电的，它有专用的电源VCCPD，VCCPD的电压不能小于VCCIO。7 h6 x# M% P% H1 M$ ^3 n
0 K0 k6 r: F! J! I; X$ T如果是xilinx的FPGA，7系列也是可以的。设置CFGBVS管脚，接GND。
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# y. S& Y$ X( I$ z8 FThe 7 series devices support configuration interfaces with 3.3V, 2.5V, 1.8V, or 1.5V I/O. The
# J% v% {/ W5 c y6 A) O( Tconfiguration interfaces include the JTAG pins in bank 0, the dedicated configuration pins
/ Q+ W9 r4 B; K qin bank 0, and the pins related to specific configuration modes in bank 14 and bank 15. To
( W5 M, d6 R6 Q3 C$ E6 l" \support the appropriate configuration interface voltage on bank 0, bank 14, and bank 15,% W G, x6 `1 c% e1 C, B
the following is required:
! ]1 W5 p7 w' w' V( W1 _• The configuration banks voltage select pin (CFGBVS) must be set to a High (VCCO_0), s5 g* H H" e# `, ]1 a
or Low (GND) in order to set the configuration and JTAG I/O in banks 0, 14, and 155 s. _6 f. O+ a/ R
for 3.3V/2.5V or 1.8V/1.5 operation, respectively. When CFGBVS is set to Low for7 a7 V8 e& ~$ }9 q G
1.8V/1.5V I/O operation, the VCCO_0 supply and I/O signals to bank 0 must be 1.8V ~ r9 Y6 E; R! ]4 N- J
(or lower) to avoid device damage. If CFGBVS is Low, then any I/O pins used for
% H# A: |% _3 L+ q+ nconfiguration in banks 14 and 15 must also be powered and operated at 1.8V or 1.5V.
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发表于 2014-4-15 18:32
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