|
|
EDA365欢迎您！
您需要 登录 才可以下载或查看，没有帐号？注册
x
本帖最后由 dsws 于 2014-4-28 12:56 编辑 9 @4 a d) S2 @: q; l+ x" ?
6 x0 L# l' K# r0 k) a. u/ N& _
链接: http://pan.baidu.com/s/1dD9XLPB 密码: ujuq0 z/ f& P" W* I/ x6 T: A4 H1 B
2 H7 [, J2 |0 r, |. O3 x) a
0 ], Y" I$ G$ A" V2 b* v
DATE: 04-25-2014 HOTFIX VERSION: 027
y- o7 p& |% F. `+ ]$ R2 `2 e===================================================================================================================================: L( G0 f& {2 [! j- d* w8 F5 b, K
CCRID PRODUCT PRODUCTLEVEL2 TITLE% u' ^6 X1 Q9 J5 D& ?/ j% A* ?6 _4 H
===================================================================================================================================2 w1 Q% p% n! k, z
308701 CONSTRAINT_MGR OTHER Needs to delete user defined schedule in CM
" Y& L% J8 s; F& `5 @481674 ALLEGRO_EDITOR PADS_IN No board file saved from PADS_in, m1 `3 {& v6 Y- O& n* X1 K$ y
982929 ALLEGRO_EDITOR EDIT_ETCH can't route on NC pin and other that are not pin.. o- l- _1 b6 P7 u+ S* S3 [
1012783 FSP OTHER Need Undo Command in FSP) p$ \& \; O( u: i0 K0 b( c
1017381 ALLEGRO_EDITOR DRC_CONSTR Need Dynamic Phase to be able to measure back to the Drive Pins.) Z p9 q, h( t: C: _" J
1072673 PCB_LIBRARIAN GRAPHICAL_EDITOR Copy paste goes offgrid if mouse is moved
0 M: }% A- |% Y1 f* c1073231 CONCEPT_HDL CORE Copy-paste of signal names goes off-grid in Windows mode.
+ A' E- N6 y# x$ x% P1105371 CONCEPT_HDL INTERFACE_DESIGN Strange behavior when shorting two Net groups
- u% v0 B/ i5 O1 W1116498 CIS LINK_DATABASE_PA link database with modified part results in Capture crash; h( u5 v! b+ ^5 W `& W
1118632 ALLEGRO_EDITOR GRAPHICS Text display refresh issue while in Edit > text command
2 T5 O5 \9 L$ ^' U6 K% d+ c& k$ U1155821 SIG_INTEGRITY LIBRARY Xnet are not recalculated correctly when model is changed on the Series switch part defined as discrete with Espice mode
' L0 L. F- r$ V1 l. c* C. ~% I/ V1157372 ALLEGRO_EDITOR DRC_CONSTR Dynamic phase for Diff Pairs not reporting back to Driver pin if pin escapes present
; e2 p! e% r$ `2 i7 l1 l: X1171951 ALLEGRO_EDITOR CREATE_SYM Jumper has a limited of count when it add to list.
! F/ n( ^ I# D2 ?1180871 CAPTURE LIBRARY_EDITOR Copied parts don't retain pin name and pin number settings V# C# i# O! N5 V
1185575 SIP_LAYOUT DIE_STACK_EDITOR Updating symbols causes the graphics for the Assy layer to change from Bottom to Top.- Q$ ?1 s5 U q3 H- Q) c% o. N
1185772 PCB_LIBRARIAN CORE VALID_PACK_TYPE warning when cell was opened in PDV) ]2 {8 Z7 ^3 B8 L% z
1192377 CAPTURE SCHEMATIC_EDITOR Pin name/number position is incorrect on schematic if it is changed for a rotated part.! e) j3 k$ k, W/ H$ l3 h5 {
1202654 ALLEGRO_EDITOR GRAPHICS Zoom using mouse wheel shall maintain the center co-ordinates5 Q S% ? |8 C3 y+ ~
1208031 ALLEGRO_EDITOR INTERACTIV Snap to Pin for via during Copy command do not snap to connect point everytime, p6 m+ y1 h$ H- n w
1208478 PSPICE PROBE Attached project gives overflow error with marching ON.
4 m2 ?' ]5 W2 C9 x1210015 CONCEPT_HDL CORE The value of $PN should be not turned on spin or rotate symbol
' P$ s% R, l0 T* K1210425 CONCEPT_HDL CORE When moving a circuit tool reports that connectivity has changed
. H p5 j; y% D7 S. j1 \1215858 ALLEGRO_EDITOR SHAPE Force update does not void cline with the shape
* L0 y2 s4 K& m1215906 ALLEGRO_EDITOR SHAPE Dynamic shape fill smooth failed when copying to other layers; J7 q1 Y% V2 L+ u2 h
1216358 CONCEPT_HDL CORE Can we improve our export BOM function to check if user did export physical function before exporting BOM? f/ @' C! a2 W7 v& j. |7 ~5 I# }
1217364 CONCEPT_HDL OTHER Netlist reports fail because error: GScald failed.: M4 p# A) A! s0 {8 s7 K* V
1217529 CONCEPT_HDL CORE ADW checks do not catch single quotes in PTF values4 M+ b& o7 W$ `% M
1217556 F2B PACKAGERXL signal name change not sent to Allegro after packaging4 R7 x$ M, e% c( D
1219283 ALLEGRO_EDITOR DRC_CONSTR Show constraint is inconsistent when displaying region information8 ~, [4 T: [1 M" [& K/ m: n0 O
1220078 F2B PACKAGERXL Export Physical crashes when ALL the part pins are added* w, v' ]* s, t' y, @( l: n
1220393 CONSTRAINT_MGR CONCEPT_HDL HDL import physical from board file will annotate CM data back to HDL which includes cross-section thickness.
8 w: s+ W% z' L& M1 p6 d1220540 ALLEGRO_EDITOR GRAPHICS Need an option to see the pads inside the internal plane shapes
- z7 m# s$ P3 I1220936 CONCEPT_HDL CORE About crash by vpadd/vpdelete command on Linux
! o9 T+ |% v! Y3 {$ a- }: {1221059 ALLEGRO_EDITOR DRC_CONSTR Get a "Shape to Thru Via Spacing" DRC error only the first time when the shape is manually voided.
* z f. ?2 |1 ?- E% E1221182 ADW TDA Team Design with SAMBA: k2 }( P4 I Y" F$ t1 }! L
1222442 CONSTRAINT_MGR UI_FORMS Duplicate pin pairs appear in DiffPair: y( {, r/ N7 r% A
1223175 CONCEPT_HDL CONSTRAINT_MGR Schematic crashes when opened
* L# E# D* |3 j T1223533 ALLEGRO_EDITOR GRAPHICS Why the through pins for STEP models are shown at an offset when viewed in 3D inside Package Symbol?& t1 w; b) V& _7 y
1223680 CONSTRAINT_MGR ECS_APPLY Improve ECSet mapping by allowing user to address ambiguity of Parts
4 z i4 @" F$ d* Z* h8 ~1224156 SIG_INTEGRITY SIGWAVE Exporting spreadsheet with filter Subitems in SigWave exports all waveforms
, q% M, `' e" ]( _1224417 ALLEGRO_EDITOR PLOTTING Hidden font pattern is not showing correct in 16.5 version also 16.6 version.
; {. V" O% |3 \" ~- i& H2 u0 Y1224704 F2B DESIGNVARI There is no lock for the variant.dat file - multiple users can open the editor7 Q" |. A5 S, \: J8 Q. K8 r( k
1224968 ALLEGRO_EDITOR INTERACTIV Delete >(RMB click) Cut> Snap Pick to>off grid loction does not work for lines., Q( a w3 `1 R4 i* U' @
1224982 CONCEPT_HDL PDF commandline publishpdf does not work when there are spaces in the path
2 J: b7 M+ m! ?1225114 CAPTURE GENERAL H-pins added after netgroup pin get color as of netgroup pin* d2 w$ r2 o, z8 x3 g; c' h/ h
1225494 CAPTURE DRC Different DRC results for Entire design and selection" y* a6 A8 O. y( e G6 d! Q; ]' z
1226153 ALLEGRO_EDITOR INTERFACES Export STEP should include PART_NUMBER property0 f' r5 T K( a' i
1226235 ALLEGRO_EDITOR EDIT_ETCH Enhancement to include Pin_delay of descrete forming Xnet
% O2 d+ g3 N7 y% v, p1226372 CAPTURE GENERATE_PART ENH: Functionality to add pin spacing in New Part From Spreadsheet3 d( N* C* f; ^8 W" ]* j9 F% \
1226477 CONCEPT_HDL CORE DE HDL縮 `Allowed Global Shorts? function is inconvenient for Global Signal
) Y; v3 ?& v6 K |0 f+ d1226813 SIP_LAYOUT LEFDEF_IF ERROR SPMHLD-120 when importing a DEF file. Request to increase the number of characters/line in a .cml file9 _$ W. w1 d1 c* L ~
1227453 ALLEGRO_EDITOR SHAPE Addition of Fillet generate Pin to Shape Spacing DRC errors and DBDOCTOR errors ^0 d h) t' T* G" a, Y! e
1227461 ALLEGRO_EDITOR SHAPE Sliding a cline for certain net changes the thermal relief connects for pins connected to another net from 4 to 5,6,7,8
' u5 w* Z2 ]8 o1227469 CIS DBC_CFG_WIZARD Oracle Views not visible on Step2 of CIS Configuration
# I* c) B" N( x1227780 CAPTURE ANNOTATE Inconsistent behaviour when annotating heterogeneous part
" _" A. L ?$ h' C3 u4 M1227831 CONCEPT_HDL CORE Pin text and H-block name in upper case1 T3 p' f+ c: M8 J8 Z8 Y
1227954 CONCEPT_HDL OTHER supress check for global signals when wires are unconnected to pins
7 O7 U' V/ u8 r& O- t1228190 ALLEGRO_EDITOR OTHER Unable to close the 'usage' window during license selection# A+ f; F0 A$ w7 H5 A9 ] D
1228899 CONSTRAINT_MGR INTERACTIV Export/Import constraints in "overwrite" mode from same design shows different results when imported second time.) b$ M2 a1 ?5 }' E! v
1228934 ALLEGRO_EDITOR EDIT_ETCH The "View Active Layer" option like the Board Station should be provided for dynamic layer visibility.
7 H6 z9 l( u9 z3 z& b1229316 ALLEGRO_EDITOR EDIT_ETCH When routing with Hug only enabled we were able to route through other routes(sometimes Hug).6 G6 @- p5 s6 m$ W2 p: z2 L
1229545 CONSTRAINT_MGR OTHER Allegro indicate bundle scheduled nets in CM* S( W# V! j1 v( L4 J2 w+ Y1 t
1230056 ALLEGRO_EDITOR GRAPHICS Bug: 3D View of Mechanical Symbol with the drill hole defined) u: C& S9 o! V% G
1230432 CONCEPT_HDL CORE No Description information in BOM
! d/ Y! f+ G S% s- H- V" z5 [9 S1231148 F2B DESIGNVARI The variant.dat file is not updated with library PTF changes
. e% G" P+ h) |9 w) j1231625 F2B DESIGNSYNC VDD at command line needs to support sch2sch and test variable to write out report files
: _; l1 b L/ I0 c1 Z( Z% t1231697 CONCEPT_HDL CORE If any locked files exist force a pop-up dialog restricting certain commands
- n1 B- A T$ M1231767 CONCEPT_HDL OTHER Unable to find under the search options single bit vector nets
" N y2 b2 b# D- p1231961 ALLEGRO_EDITOR SHAPE Shapes not updating to smooth unless we use force update and as a result false DRC's appear in board./ A9 p: b! k- G$ }
1232100 CONCEPT_HDL SKILL Unable to execute the SKILL commands in viewer mode
0 W6 r* q v- W# U* f1232336 CONSTRAINT_MGR CONCEPT_HDL cmFeedback takes 5hrs to complete during Import Physical/ H3 F0 r: Q+ u# E" i. y
1232710 F2B DESIGNVARI Dehdl crash while moving component in variant viewer mode
4 K& H' ~& q1 s1233894 F2B PACKAGERXL The page data is missing in the pst* and PCB files+ j2 s( \' E7 d" ~! P0 L/ p
1235785 CONCEPT_HDL CREFER cref_from_list custom text is not subsitituted in complex hierarchy
+ u. W; f, B( H$ D' z# R2 [1235928 CAPTURE SCHEMATIC_EDITOR OleObject modifications not saved: J$ g8 Q" j! S) R& q" ^3 X
1236065 CAPTURE PART_EDITOR Mirrored part after being edited get pin name locations incorrect
4 \8 e. x7 {5 H; y1236071 ALLEGRO_EDITOR SHAPE Airgap for Octagonal Pads ignores DRC Value when Thermal set
! b N& F# z5 c& B7 ?1236072 CONCEPT_HDL CORE Page 122 cannot be saved as logical page 119 has different page mapping in connectivity data and schematic
' u. c* `6 f# O7 d1236161 CONCEPT_HDL CORE Import Design shows the current project pages
+ q9 |; `& P( s% a R+ @5 w1236432 ALLEGRO_EDITOR PADS_IN pads_in doesnot translate via and shape in some instances.
% B3 u. O+ m) J' V. J( C1236557 CONCEPT_HDL PDF Running Publish PDF on command line in linux doesn't output progress until completion8 O8 x$ p7 e8 N& z; j
1236589 CONCEPT_HDL PDF Enhancement license failure error should appear in pdfpuplisher log file8 r& h6 ]- d) s# m2 `( o
1236644 ALLEGRO_EDITOR EDIT_ETCH create fanout deletes shape" K8 v b$ F2 Y$ k
1236689 ALLEGRO_EDITOR GRAPHICS Graphics displays extraneous lines when panning or zooming' F% ^" g, m) F1 ?2 x
1236781 F2B PACKAGERXL Export Physical produces empty files
$ A9 B8 y, k x' e1237331 PSPICE ENVIRONMENT pspice.exe <cir file name> - hangs when run
0 l; J, U/ s2 f% g! o* W1237400 CIS EXPLORER Capture hangs on 2 consecutive runs of `refresh symbol from lib? command
1 _( f Z( j' K0 o4 D1237437 CONCEPT_HDL CONSTRAINT_MGR CM Crash when saving after restore from definition( e+ k6 W9 z) ?
1237862 CONSTRAINT_MGR OTHER A way to remove the RAVEL markers from the Constraint Manager. n! z) ]6 G& M( u
1238852 CAPTURE GENERAL signal list not updated for buses
: u+ g1 K9 A: D2 N7 i. M9 z2 z1238856 FSP DE-HDL_SCHEMATIC FSP schematic generation crashes
5 g1 t. }* |3 `5 f) R3 M% [1239079 ALLEGRO_EDITOR INTERACTIV The 16.6 Padstack > Replace function leaves old padstack.4 a. N( [- o1 X9 T4 G& J1 m# k8 }1 J
1239706 CONSTRAINT_MGR ANALYSIS The reflection result on a differential signal in the CM when Measurement location is DIE6 ]2 v( x. l6 L
1239763 PSPICE PROBE Cannot modify text label if right y axis is active
0 }. x) l& ^1 f2 j& S1 X, K1240276 ALLEGRO_EDITOR GRAPHICS Printing to PDF from SigXp is giving unreadable images
& q% k( t; P' y% r; l3 ] w1240356 CAPTURE IMPORT/EXPORT Can縯 import SDT schematic to Capture.
: t- S( C. `/ `* ~1240502 F2B PACKAGERXL Corrupt cfg_package does not stop PackagerXL from completing
+ |3 x0 ~) \9 n3 v9 U+ u1240607 ALLEGRO_EDITOR OTHER Footprint of screw hole got shift in DXF file, }, V: x; |2 N( [6 _
1240670 ALLEGRO_EDITOR PLACEMENT Select multiple parts and Rotate makes them immovable, a* _$ x P% i" w [* A7 n2 C, e
1240773 CAPTURE DRC DRC check reports error for duplicate NetGroup Reference in complex hierarchy* I3 }, Z; \3 k( \& }) S- O& j, F
1240845 SIG_EXPLORER EXTRACTTOP Narrowband via models for Mirrored BB Vias not extracted in in the interconn.iml and this gives bad ringing in waveforms" O. q1 v+ c/ ~+ a; p/ q' \; J
1241634 ALLEGRO_EDITOR OTHER Netshort for pad-pad connect not working+ P3 R3 o4 m$ W5 ^/ [ ^* b
1241776 CONCEPT_HDL CORE In hierarchal design not all pages are getting printed.% I9 w8 j1 F$ a2 j+ R2 ?
1241788 CONSTRAINT_MGR CONCEPT_HDL Issues with changing focus in Constraint manager using keys on keyboard
, [. c# _& ^. ~6 N! i1242683 ALLEGRO_EDITOR INTERACTIV Color View Save replaces file without warning
# p" ^4 u* A2 ^! }2 s5 D$ Y- ~1242818 ALLEGRO_EDITOR PLACEMENT Placement edit mirror option places component on wrong side0 p* Y* _" n5 d* o9 U
1242847 ALLEGRO_EDITOR GRAPHICS Need an option to suppress Via Holes in 3D Viewer
7 j: Z5 [! y/ b9 V- c8 V/ J( n1242923 ADW COMPONENT_BROWSE UCB reports Missing From DB only after selecting the Row in the search results2 r$ V; P1 {5 U1 K* Y( `( i2 k
1243609 CONCEPT_HDL CORE autoprop for occurrence properties
2 {7 c$ U( k! K1243682 F2B DESIGNVARI after undocking variant icon cannot be redocked back to GUI& I3 O v m: [( i
1243686 ALLEGRO_EDITOR GRAPHICS Invoking Edit->Text, the infinite cursor disappears until edit mode is changed.
4 o1 q3 y* N) U+ R4 L* E1243715 CAPTURE PART_EDITOR Pin name positioning get changed after rotating or mirroring
- c+ |" f! c1 S( T" H7 e1244945 CONCEPT_HDL PDF PDF Publisher does not include image when file is not located in the root folder: N D1 i k6 `' y8 J B% x1 r
1245568 CONCEPT_HDL CORE Dual unselect needed for wires attached to other net/source and property is not deselected when component is
% a- {. T& z( ]& O1245819 F2B PACKAGERXL wrong injected properties information passed during packaging of the design
. W4 w" z& F- R5 E2 p/ q1245916 SCM CONCEPT_IMPORT Where does the folder location reside for DEHDL imported blocks?
% H; @; k+ {* s4 ^/ _1246347 CONSTRAINT_MGR CONCEPT_HDL DEHDL crash if environment variable path has trailing backslash character
1 O! F1 q+ A6 ]6 ~; X1246896 ALLEGRO_EDITOR DFA DFA_UPDATE on Linux reports err message if the path has Upper case characters
/ S- z* C. H/ M; x& e' k1247019 SIP_LAYOUT DIE_STACK_EDITOR SiP Layout - refresh/update symbols is mirroring the assembly drawing data on DIE that is placed ChipDown2 l! H) q5 S9 R' i# L, n+ ?
1247037 CAPTURE LIBRARY_EDITOR Copy & Paste of library parts resets pin name and number2 M \2 Z% @1 k/ W4 l1 E
1247089 CONCEPT_HDL CORE Group Align or Distribute > Left/Center/Right crashes DEHDL
. `1 P1 m' ?! Z! G# @1247163 CONCEPT_HDL PDF Physical Net Names in PDF not maintained' `$ y: [* G8 p, ^2 p# B% }
1247462 CONCEPT_HDL CORE Text issue while moving with bounding box
( B- ^1 e3 o0 V" h6 s5 e1247464 ALLEGRO_EDITOR UI_FORMS When using the define B/B via UI the end layer dropdown arrow is partially covered# y' Y. `. k9 s, K L
1249063 CONCEPT_HDL CONSTRAINT_MGR CM and SigXP doesn縯 respect PACK_IGNORE at components
8 F3 F4 y8 b6 @1250270 CONCEPT_HDL CORE Part Manager Update places wrong parts, J0 d' O6 ~2 c/ M# s. x
1251206 ALLEGRO_EDITOR ARTWORK Aperture command cannot create appropriate aperture automatically from design.
$ u8 P4 t1 v) [/ _1251356 ALLEGRO_EDITOR INTERFACES Some STEP models are missing in 3D view of footprint, although all components have STEP model mapped in footprint; F, s5 p/ }" C
1251845 ALLEGRO_EDITOR EXTRACT Crosshatch arcs do not extract correctly( t- ]/ Z* i# w) r# Z
1252143 APD OTHER When using the beta "shape to cline" command the tool is removing the shape instead of converting it.) V7 q$ O& H9 F, b" f
1252737 SIP_LAYOUT OTHER SiP Layout - Option to create shapes from Pins for WLP wafer level packaging technologies
; |5 a# }" G( Y6 ?/ d% z3 D1253424 SCM SCHGEN Export Schematics Crashes System Architect) e E' o% o, m9 q
1253508 ALLEGRO_EDITOR INTERFACES Bug - Export IPC2581 exports Crosshatch shapes as filled
$ D; W/ X3 u" a9 S2 p/ ]' Q1253554 SIP_LAYOUT OTHER SiP Layout - Add Netlist Spreadsheet export to SiP layout to help with connectivity auditing1 w$ d% ]3 P1 v* |
1254578 SPIF OTHER Specctra crash with Error -1073741819 for Auto router
; U2 A5 Q* y& G& I; z. H3 H1254637 ALLEGRO_EDITOR DRC_TIMING_CHK adding nets to a net group causes constraint assignment error
' I4 A+ K! r! g8 [( U Q6 A) _; u1254676 GRE IFP_INTERACTIVE Rake Lines disappear when Auto-Interactive Breakout is enabled.+ ^; N2 z4 o2 x
1255067 SIG_INTEGRITY REPORTS Allegro hangs on Net Parasitc Report generation' a' j4 ~7 A& O7 M" s2 R
1255267 ALLEGRO_EDITOR SKILL axlDBGetPropDictEntry does not return a list of all objects, h9 Q3 h' _0 l2 k
1255383 SIP_LAYOUT IC_IO_EDITING cant move bumps or driver in app mode( V7 _' h8 @ g/ ]9 \! ?# }% q7 l
1255703 ALLEGRO_EDITOR SKILL axlCNSSetPhysical and axlCNSGetPhysical return nil if a constraint set name is provided
% V7 V; T- Q# \0 v5 C1255759 ALLEGRO_EDITOR INTERFACES Change the silkscreen OUTLINE from layerFunction DOCUMENT to layerFunction BOARD_OUTLINE
+ f. m+ o- ?* [9 j& u1256457 CONCEPT_HDL CONSTRAINT_MGR Extracting a XNet from CM crashes the tool8 ^( B! h% m' _
1256597 GRE CORE Allegro GRE crashes while running Plan Spatial, on a particular design3 k5 M' i$ t, Z) t" _
1256650 ASI_PI GUI PFE - Cannot generate model file error when using company decap library
1 y$ J' {9 I" E$ g+ S# j1256837 SIP_LAYOUT DIE_EDITOR Open and close of die editor takes too long
/ f, H( P1 G0 U. [1257732 CONSTRAINT_MGR OTHER Bug - Export Analysis Results in CM makes Allegro crash
: e' y% Q9 c' i. B1257755 ALLEGRO_EDITOR OTHER Editing time in Display > Status seems to be logging wrong time
% R8 B7 p7 X/ u+ M7 d1258029 APD WIREBOND The bondwire lost after import the wire information
1 Y$ O0 [, E' F7 } r$ s# u5 P! M1258979 APD NC NC Drill: There is difference of number of drills.
1 D# m! s& d; |/ \) w1259484 SIP_LAYOUT OTHER SiP - calc min airgap calculate minimum airgap beta feature improvement
! k% U5 A# J2 Z* ^0 p4 W* |4 W9 P1259677 CONCEPT_HDL CORE hier_write -forcereset cause component prop change.9 s% I2 J; B( r4 W# ]5 p! e
1259913 ALLEGRO_EDITOR UI_FORMS Unable to save setting of "use secondary step models in 3D viewer") a: T$ \) }( Z. d+ ]5 _+ U) E
1261758 ALLEGRO_EDITOR EDIT_ETCH Auto Interactive Delay tune (AiDT) is deleting clines
q: O8 J: r' d5 w( H; e1262543 ALLEGRO_EDITOR MANUFACT merge shape results in moved void5 r D: d( _, s! C: w1 {
1264767 ALLEGRO_EDITOR DRC_TIMING_CHK XNET is choosing to resolve to a different name from 16.5 to 16.6 and is causing constraint loss; I) C% R3 G: L5 ~2 v- @$ E
/ f" D8 N3 R* f
|
|
/1 
发表于 2014-4-26 15:14
QQ好友和群
QQ空间
腾讯微博
腾讯朋友
微信
收藏
支持！
反对！
楼主
