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http://dl.vmall.com/c0fu1auqa8( f4 m+ {5 U0 Y- H G
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DATE: 02-14-2014 HOTFIX VERSION: 023: B1 z5 x$ r- J' m! _2 x6 L
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9 k, a- e$ A' z- z+ }! {+ ~+ t2 [CCRID PRODUCT PRODUCTLEVEL2 TITLE( A1 X5 C# Y" v
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0 u; t' J/ s" F3 Q# ]' C1 O1120183 F2B DESIGNVARI Variant Editor Filter returns incorrect results.
7 F8 E1 p* y3 o7 S1202715 SPIF OTHER Objects loose module group attribute after Specctra
; ]4 i: H5 }5 @! h W: @, q1203443 ADW LRM LRM takes a long time to launch for the first time
' T$ \8 J/ t! U5 k1207204 CONCEPT_HDL CORE schematic tool crashed during save all$ ]) s8 U: ?9 E2 C( P" t) P9 s
1222101 CONCEPT_HDL CORE Pins are shorted on a block by the Block's title delimiter
' C* a; V7 v5 f6 }+ F1223709 FSP FPGA_SUPPORT Need FSP model of Altera 5AGZME3E3H29C4 FPGA
( F3 k" S4 h% v% N a! g1224025 ALLEGRO_EDITOR INTERFACES The 3D viewer when working on a brd file shows package placed on BOTTOM side of my board while it is present on TOP side( h# T0 O5 R6 G# T* u- A+ X8 ?
1225591 F2B PACKAGERXL Aliased net signals starting with equals sign are not resolved correctly in cmgr+ F# r( U+ z1 J( h8 m1 q
1226480 ALLEGRO_EDITOR EDIT_ETCH Routing time is took to double increase when using the Add Connect because DRC is Allowed. H0 s3 o6 O2 {, h# y
1229234 FLOWS PROJMGR Can't open the part table file from Project Setup
0 n, B/ X% i) j5 D7 A2 X i1229555 ALLEGRO_EDITOR ARTWORK IPC-2581 not recognizing pin offsets correctly.# s: c: s# {& c# I% l! n/ F! Z6 _
1229610 FSP FPGA_SUPPORT New FPGA device request - Altera Cyclone V ST: 5CSTFD6D5F31I7
8 R* J Y9 `2 J+ h9 `! F; [7 }1229664 ALLEGRO_EDITOR SHAPE Shape not voiding different net pins causing shorts with no DRC's$ U$ l: i# f D8 E" \; B
1232601 ALLEGRO_EDITOR MANUFACT Cannot add test point to via on trace.7 a, e* L+ ^! k% x2 p z
1232772 ALLEGRO_EDITOR DATABASE When applying a place replicate module Allegro crashes0 T* ]: X6 x8 j6 w3 P, {
1233216 SIP_LAYOUT DIE_ABSTRACT_IF Allow more than 2 decimal places for the shrink facor in the add codesign form3 k2 A \# X/ L
1233690 PDN_ANALYSIS PCB_STATICIRDROP PDN IRDrop: Mesh mode in Report is incorrect.5 S3 j# y8 g7 w( ^6 O
1233977 ALLEGRO_EDITOR INTERFACES single shape copied and rotated fails to create when importing IDX, Q V, W G% q) J
1234357 SIP_LAYOUT SCHEMATIC_FTB DSMAIN-335: Dia file(s) error has occurred.' F- D# ^7 W0 o: p
1234450 ALLEGRO_EDITOR INTERFACES clines, pads, etch shapes to be at the same level with the board when viewed in STEP viewer.& u2 q" h$ A t' E! | c$ E
1235587 PSPICE MODELEDITOR PSpice Model Import Wizard does not display symbol graphics for DE-HDL Symbol
9 J$ M5 v4 S% b! j* ]9 n: I1236571 ALLEGRO_EDITOR GRAPHICS Allegro display lock up and panning issues2 z2 i1 _+ q- m& {7 v
1237415 ALLEGRO_EDITOR INTERFACES Multidrill pad is exported with single Drill in the STEP File) ?7 H* h. \5 t" z
1237807 ALLEGRO_EDITOR SCHEM_FTB The line feed code of netview.dat |
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发表于 2014-2-18 16:44
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