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DATE: 02-07-2014 HOTFIX VERSION: 022
# N4 A" T3 u0 p! T* u===================================================================================================================================8 M; L9 v& ~; m4 R$ J# }7 ^( k
CCRID PRODUCT PRODUCTLEVEL2 TITLE
7 w& E& _! A: T) _" U# G, b/ n! `===================================================================================================================================
3 Q& p) `" B K. g192358 ALLEGRO_EDITOR PADS_IN Pad_in does not translate some copper shapes' z; H9 J+ f0 a& _
222141 ALLEGRO_EDITOR PADS_IN PADS_IN: Extra shapes are created whenimporting PADS design: p) O, d4 f% H9 j; z$ S
274314 ALLEGRO_EDITOR PADS_IN PAD_in boundary defined for flooded area be translated DYN9 |3 ?2 G6 ]/ W
413919 ALLEGRO_EDITOR PADS_IN pads_in cannot import width of refdes.
K$ F2 W. m2 V) y/ p609053 ALLEGRO_EDITOR PADS_IN "Mils to oversize" of "pads in" did not workcorrectly for MM data.( b0 y! n" Y) u
666214 CONCEPT_HDL OTHER Option to increase Line thicknessin publishpdf utility
. k; s8 q, }+ P) L% f738482 ALLEGRO_EDITOR GRAPHICS Export image creates black image with Nvidia GeForce 8400M GS Graphicscard+ G! T3 b8 ^( ]. Y- T3 U
982950 CONCEPT_HDL OTHER change the mouse button for thestroke to have same function with in pcb editor1 f8 Q! e1 y8 k! ^8 Z5 n
1020886 SIP_LAYOUT LEFDEF_IF a quicker way to promote die pins (byimporting macro_pin list)
& G4 M& W5 L; x m" t3 x6 e5 u" t1032678 CIS VIEW_DATABASE_PA View Database Partgives incorrect result in complex design with variants.+ s$ ^: N' g8 F* G5 h
1033864 ALLEGRO_EDITOR PADS_IN pads_in doesnot translates teardropspresent in design. ?3 F+ r& V/ p, i
1054862 CONCEPT_HDL OTHER Option to increase Linethickness in publishpdf utility# X4 j }; ]$ w5 x$ @. O
1055252 FSP PROCESS Add a synthesis option to target agroup to contiguous or consecutive banks. }7 O4 ?2 x$ A
1100772 CONSTRAINT_MGR OTHER In Constraint Manager > DRC >Spacing the Show Element DRC totals are wrong.
- m0 Y% H* t6 U) S& r7 X, o/ s R1135020 CIS DESIGN_VARIANT Variant list is showing wrong results forhierarchical designs" i( t3 i" s" M# e
1138951 SIP_LAYOUT DIE_ABSTRACT_IF Fix die abstract r/w to properly supportpinnumbers on ports
8 R8 [7 q; {- e# Z9 a. H$ k1140042 CONSTRAINT_MGR OTHER Diff_Pair lengths and analysis arelost after closing and opening Constraint Manager.6 T$ N+ }5 N [. q
1143662 ALLEGRO_EDITOR INTERACTIV Enhancement Request for RMB - Snap Pickto options increased to include Pin edge
$ y* ~' X3 f, Z1147961 PSPICE SIMULATOR Simulation produces no output data
; V' ~5 w4 Y) N# H* ?6 L; J1 H' V1150874 ALLEGRO_EDITOR PADS_IN Dimensions in PADS are not translatedcorrectly during pads_in translation
+ }1 R5 I5 f3 V8 Y3 ~6 a0 X1154184 CONSTRAINT_MGR CONCEPT_HDL Difference in the way topology isextracted in 16.3 versus 16.6" a; j& P& W* ~ h" z
1154770 CAPTURE PROPERTY_EDITOR Variant Name property doesn't show value inVariant View mode
$ {( [$ L( U8 x1158350 CONCEPT_HDL CORE Need a warning Message whileimporting a 16.3 sub-design in a 16.6 Design9 c( ?3 Q5 K# I9 a* h0 Z3 @. `# _
1162347 ALLEGRO_EDITOR EDIT_ETCH Enh- Allow new option in Move commandsuch that it allows stretching etch using only 45/90 degree segments directly% G& p/ j- M6 b. z, s( a
1165553 ALLEGRO_EDITOR INTERACTIV Subclass list invoked from the statuswindow does not represent correct colors.
' v* A) Y$ O" A2 D* M1168079 FSP MODEL_EDITOR Clicking OK or Save As in rules editorallows user to overwrite the master with no warning
4 h# P7 F% w$ w. M1172043 SCM OTHER : in pin name causes SCM to crash2 [( `/ H$ H$ Y9 ^* I
1172207 CAPTURE STABILITY Capture crash while adding new partfrom Spreadsheet6 s1 U* {8 m+ j% N- _% ]" }
1172743 ADW TDA Allowed character set for thecheck-in comments is too limited' T) n5 m* D/ a, w4 {4 h
1174099 SIP_LAYOUT WIREBOND Option to reconnect wire based on 縫in name� in the Wire Bond Replace! p8 B9 v+ Q5 T0 A2 j7 z" D) S
1177672 APD IMPORT_DATA Netlist-in wizard didn縯 provide detail information about whatcolumns have been ignored by import process
. D/ t- J# t- G9 w, D1177714 CONCEPT_HDL RF_LAYOUT_DRIVEN RF component's LOCATIONproperty can not be set to invisible
! W2 g* ^, w; y4 V7 p1177820 CONSTRAINT_MGR INTERACTIV Done the Allegro command when attemptingto launch CM$ V& R0 G! c9 P9 J
1178586 ALLEGRO_EDITOR EDIT_SHAPE Number of digits displayed after thedecimal point of Shape Creation function does not match the Accuracy of BRD, p6 b$ F% G: S% h' O+ c1 [
1179688 PSPICE STABILITY pspice crash for particular HOMEvariable vlaue9 a( y# B* W. [* P2 E
1179827 SIP_LAYOUT OTHER SiP Layout - Spreadsheet to Symbolexport - enable field to add Keywords for data fields to excell cells
4 ] p7 {9 ~6 j: y' F, A# Y1179879 SIP_LAYOUT STREAM_IF Data file corrupt when exporting Streamdata from SiP database.4 `5 u7 J/ Z6 v2 T8 U0 `
1180164 F2B BOM BOM csv data format converts toexcel formats
0 |& [; q! d0 F1 w4 p1180477 ALLEGRO_EDITOR INTERFACES IPC-356 output is listing a duplicatelocation in the comment section
4 v& }& v; g4 s( n1180932 SIP_LAYOUT OTHER SiP Layout - Symbol to Spreadsheetadd option for writing to existing spreadsheet* \7 v/ F( b. q& U9 n% a
1181377 ALLEGRO_EDITOR INTERACTIV Pick Releative does not work correctlywith RMB-Move Vertex
# c4 V, Z K p9 Z$ t8 f6 A1181516 ALLEGRO_EDITOR DRC_CONSTR Getting a "Thru Pin to RouteKeepout Spacing" when there should not be one.4 I5 _# U" X# q! v+ a* U
1181739 GRE CORE Running Plan > Spatial crashesGRE, {- {: y4 y$ F2 o9 I5 ]: o7 m
1181935 ALLEGRO_EDITOR DATABASE Enh. Property that allows internal C-CDRC errors& U c, M8 f2 [3 G6 i
1182185 SIP_LAYOUT OTHER SiP Layout - Import symbolspreadsheet - suppress Family for the font in the XML spreadsheet
7 T5 P1 i' [) Y5 e0 t9 t' n1182566 SIP_LAYOUT OTHER SiP Layout - Spreadsheet to symbol- Enhance ability of spreadsheet exchange to allow for a portion of a full pinmap
3 h0 N0 h% l" O1182599 CONSTRAINT_MGR DATABASE CM Prop Delay Actuals do not updateafter Z Axis option is turned ON or OFF and Analyze is run.
+ V! @6 i4 `# U. F; X \( z. D; l1182892 CAPTURE SCHEMATIC_EDITOR Pspice marker rotationbefore placement" K) Z" @6 Z$ s: J( ]) b8 R+ G
1183682 ALLEGRO_EDITOR DRC_CONSTR Implement Nodrc_Sym_Pin_Soldermask &Nodrc_Sym_Pin_Pastemask to symbol level' Q( N; [- `7 \. A+ S, ~, _5 @
1185445 SIP_LAYOUT DIE_ABSTRACT_IF Die abstract export needs to be able toselect xda file type when browsing
) x4 R& u) s8 z+ d6 w) ^# u1185932 ALLEGRO_EDITOR SHAPE Soldermask in solder mask void DRC6 z0 J7 n) W( v$ `
1185946 CONCEPT_HDL CORE Ericsson perfomance testing report5 sept 2013
; h, k2 s. W: N1187213 FLOWS PROJMGR Unable to lock the directive:backannotate_forward8 a Z) v9 y- N
1187444 ALLEGRO_EDITOR DRC_CONSTR With this design Database check promptserror "SPMHGE-47: Error in call to batch DRC"
# j$ }" l* H! e0 \1187597 ALLEGRO_EDITOR DRC_CONSTR No Package to Package Spacing DRC error,when symbol overlap sideways at 45 degree.5 A4 @( @3 R3 e9 t6 G, H+ z# ]
1187723 FSP PROCESS Synthesis can fail depending on componentplacement
8 M5 T% x- e4 ?* _2 i7 F1188164 SIP_LAYOUT OTHER SiP Layout - Spreadsheet interfacesImport Export and Add Component - include Keyword for NET_GROUP
7 |/ A& y3 [$ L7 E# T/ X6 v& i1188245 CONCEPT_HDL CORE INFO(SPCOCN-2055): You cannot runthe CHANGE command in a read only schematic
) P- Q) b; g& X1 R+ `+ E* Z5 p1190927 CONCEPT_HDL CORE Check sheet does not reportshorted signal/power nets if power symbol is connected to a pin
4 w* z- V0 \# {; @1191497 ALLEGRO_EDITOR INTERACTIV ENH: Adding names to the text blockparameters numbers
$ A N$ M9 z6 O1192005 SIP_LAYOUT IMPORT_DATA Import SPD2 is missing 1 smart metalshape from file
7 ]6 d: l n3 B7 C, d- h1192204 ALLEGRO_EDITOR EXTRACT Need ability to extract vias that arelabeled as microvia
% j1 M7 F6 j0 x* R- k t1193063 ALLEGRO_EDITOR MANUFACT TestPrep log displays "Pin is notaccessible from bottom". The component is through hole.# Z" b+ ^. c% _% R
1193418 ALLEGRO_EDITOR GRAPHICS 3D Viewer can`t export image in both SPB166S015 and SPB165S0477 F1 p; H, x4 S: i$ u
1194305 SIP_LAYOUT EXPORT_DATA export package overlay creates file withno package info
" [% m& f" `1 u; |4 A: b" e1194418 APD IMPORT_DATA issue when doFile->import->netlist-in wizard) R% x; l; }! p( z# |# A
1195279 F2B PACKAGERXL Ptf files are not being read whenpackaging with Cache
4 J( r2 f, r1 [7 _0 o \ q) D1195374 ALLEGRO_EDITOR INTERACTIV Modules are not showing up in Tools >Module reports
( `! A6 W, O+ p3 b( S1196603 SIP_LAYOUT EXPORT_DATA Change form for "Write PackageOverlay..." to better support longer lists of routing layers
& P* ?5 L, h8 T6 h1197302 CONSTRAINT_MGR UI_FORMS Inconsistancy in selection of objectfor Spacing Constraint Worksheet
+ P4 n4 B0 M- W& `6 ?% s1197399 CAPTURE OTHER Draw toolbar disappears when usingPrint Preview8 ?) _ h+ b8 J$ s( m
1197543 ADW TDA TDO does not correctly showdeleted pages
# p' j! f! n& j; l* r1198033 CONCEPT_HDL CORE Signals do not get highlightedwhen Show Physical Net Name is option enabled; G( t' ?0 e7 r3 z. r6 F1 D
1198468 ALLEGRO_EDITOR GRAPHICS 3D_step model does not show thecorrect view in 3D_Viewer when symbols have multiple place_bounds.
# `" _' V q, R5 l: ^1198617 CIS GEN_BOM Mech parts are showing with Partreference in CIS BOM
: M, L1 O/ z! j$ K3 {5 `1199764 ALLEGRO_EDITOR SHAPE Allegro crashes when trying todelete small island on POWER layer.
. v0 l, Y6 P5 S; f+ j1200232 ALLEGRO_EDITOR INTERACTIV Moving all items including board outlinewhich is made of lines does not move the board outline in General Edit Mode.6 W2 b" y6 D* S
1200748 ALLEGRO_EDITOR INTERACTIV Additional pin edge vertex object tosnap pick q1 C, G2 n; L ?. I) {
1201056 ALLEGRO_EDITOR DATABASE Unsupported functionality strip designcreates a .SAV file
$ i- j" ]: E: C8 V) f0 o1201638 CIS PART_MANAGER Part retains previous linking inside thesubgroup
: v& A$ Q6 X o- ]3 O1201834 ALLEGRO_EDITOR PLOTTING Bug: Import Logo command changesresulting imported object
, w9 S5 f [0 {. \/ m6 c1202406 SIP_LAYOUT OTHER enable the dynamic display of componentpin names for co-design dies in Sip Layout
2 ]' ]* M* V m1202431 CONCEPT_HDL PDF The publishpdf -variant optionshould have a "no graphics" option# G+ W I$ [* v$ O
1202717 ALLEGRO_EDITOR DATABASE About Warning(SPMHA1-108):Illegal linesegment ... end points.+ D$ W% X, Q4 x- k! b! h
1203459 CONSTRAINT_MGR INTERACTIV Object Report has no mechanism to outputinformation for a specific design.
1 c. k( n7 j0 |" N1204544 F2B DESIGNVARI Variant Editor does not warn on save ifno write permissions are on the file
+ T# A9 L8 V. d! E6 C* f7 p1205500 FSP CONSTRAINTS MAPP FSP FPGA port mapping VHDLsyntax. z- O) c5 ~4 _; k) u5 @
1205952 ALLEGRO_EDITOR GRAPHICS Step Model for Mechanical Part isvisible in 3D viewer only when Etch Top Subclass is enabled; o8 Z0 r+ G: N% v
1206103 SIP_LAYOUT IC_IO_EDITING add port name property to pins, and addSkill access I/O driver cell data
3 P. G7 M0 l8 M* y" A5 ]/ l: B1206546 CAPTURE ANNOTATE User assigned refdes are resettingwhen 緼nnotation type� is set to 縇eft-Right� or 縏op-Bottom�9 `, {. _+ s K" y* j- g
1206561 ALLEGRO_EDITOR GRAPHICS Not all mechanical symbols made with Stepfiles are displayed in the 3D View
9 W! H& n' E" S3 M C! i; ^% @1207125 SIG_INTEGRITY ASSIGN_TOPOLOGY ECSet mapping wrong for 2 bit in a 4bit bus' }7 C6 t/ g6 g: ?
1207386 CAPTURE GENERATE_PART Altera pin file not generating the partproperly1 n. K& t$ E/ S' g/ A
1207629 CAPTURE TCL_INTERFACE Bug: GetMACAddresses tcl command notworking0 E3 K+ {4 K* W+ H3 I9 r8 s4 B. Z8 `
1207994 CAPTURE TCL_INTERFACE TCL pdf export in 16.6 fills DOT type pinswith black color
) ^' `" m( b* q1208017 F2B DESIGNVARI sch name is not same when updatingSchematic View while backannotating Variant
5 u2 S% L) E6 B/ R3 T7 z3 f1209363 ALLEGRO_EDITOR INTERFACES When placing pins using the polarcommand the tool returns 4500.00 for 45 degrees.
! o( h4 j' j x" T6 j Q1209769 CONCEPT_HDL CORE Top DCF gate information missing
4 z1 B' s0 Y7 z$ T# ~& i5 _ n+ H1210194 CONCEPT_HDL CONSTRAINT_MGR HDL crashes with Edit Via List dialog box$ ~0 \; h8 y( _) u" g: ]3 t
1210442 CONCEPT_HDL INFRA Save design givesERROR(SPCOCN-1995): Non synchronized constraint property found in schematicpage* p$ ~& N1 d9 Q1 C7 W4 Q9 ?/ _
1210685 ASI_PI GUI User can't edit padstack inPowerDC-lite
" d; n# [2 ?+ c" E' s1210744 SIG_INTEGRITY SIGWAVE SigWave: FFT Mode Display unit seemsnot to be correct+ g- g) [. }+ R2 h
1210829 CAPTURE NETLIST_VERILOG Shorted port is missing from verilog file3 v% B7 f4 y& A0 e
1210850 CONCEPT_HDL CORE DE-HDL backannotation crashingafter instantiating specific cell from Ericsson BPc Library
- L8 n) Z# B- y- t0 Z1211620 ADW COMPONENT_BROWSE Component BrowserPerformance
) v0 f# _% q* h: X$ ]9 t8 K$ J& S8 E1212102 ALLEGRO_EDITOR INTERACTIV Shape edit boundary adds arc mirrored tothe highlighted preview.
( N2 H$ {# l) b6 x1213294 CONCEPT_HDL SECTION DE-HDL windows mode multiple section fails tosection first contactor pin from column of individual pins
8 E( Q" l. K$ J: d# ^6 F1213402 APD DATABASE The old "ix 0 0" fix is now causing the features to lose netsentirely.+ ^3 I- A/ m5 u& `, m5 T
1213694 ALLEGRO_EDITOR PARTITION Via connected to Dummy Net pin in Partitiongets connected to shape on the board after importing partition- D) `# }6 u- w3 D4 |
1214247 CONSTRAINT_MGR UI_FORMS Selecting the "All" folderin Spacing Constraints in CM does not automatically select the first column forediting
; q/ d' @( b! K; C1 D8 T1214320 SIG_INTEGRITY SIGNOISE signoise command with -L and -k option
$ N" n0 S' L P' V1214433 CONCEPT_HDL CORE Genview does not update sym_1 withports added to the schematic
, U& n+ C: R9 x. m2 d; J8 U; D1214909 ALLEGRO_EDITOR NC NC Drill Legend show extra rowsfor drills
5 v6 X' _2 a6 @1214916 SIP_LAYOUT OTHER package design integrity check forvia-pin alignment with fix enabled hangs
+ ?+ g6 X( R1 g, _: d2 q; n1215954 SIG_INTEGRITY SIMULATION Cycle.msm does not exist error whensimulating extracted net" g2 B" z2 _4 F5 L+ J" o% @' ]
1216328 CAPTURE STABILITY Capture crash
: y. Y+ k0 v' g1216993 ALLEGRO_EDITOR DRC_TIMING_CHK Allegro crash on SPB16.50.049
9 k8 F c1 e2 S- `( O1217450 F2B BOM ERROR 233: Output file path doesnot exist" \9 }& O4 u9 d* H, I0 v
1217612 ALLEGRO_EDITOR INTERACTIV Replace padstack will not replacepadstacks that have multiple alphabetic characters in the pin name - AB21-AB37 F* T4 B+ S. p5 H$ M+ p
1217823 ALLEGRO_EDITOR INTERACTIV Compose shape fails with SPMHIS-4731 r( O: _( P2 N2 ]
1217887 ALLEGRO_EDITOR INTERFACES An undo option to be made available inthe STEP Package Mapping window
2 R* f! `9 v: w# e& E1218665 ALLEGRO_EDITOR INTERFACES In step viewer, the bottom side partsare placed above the pcb board surface" j# q3 V" B) G2 t1 c: M2 @3 _
1219053 PSPICE PROBE PSpice crash with the attachedDesign
% b1 {6 N, c; O" B5 V' a1219067 ALLEGRO_EDITOR EDIT_ETCH dynamic fillets behavior is unstable4 d) L3 B# x$ \) {6 o' i& u5 ]
1219095 ALLEGRO_EDITOR MANUFACT Design Cross section chart is taperedfor two layer board
: G& u E' o: X1 q1219126 ALLEGRO_EDITOR SKILL Skill issue with axlRefreshSymbol()
$ h, f- H% Q8 x1 W1 L1220701 ALLEGRO_EDITOR INTERACTIV View > Windows > Worldview(showhide view command) fails with command not found
6 S! h# {# o& W, r! _1221057 ALLEGRO_EDITOR REPORTS Units in Cross section report forspacing is not synced with the design
- h- x6 @9 O" A) ?* w4 U# W/ u1221139 ALLEGRO_EDITOR EDIT_ETCH Delay tune is not tuning differentialpair
" d! d2 p) m' ~8 C1221157 SIP_LAYOUT IMPORT_DATA import spd2/na2 file is not importingdata correctly into sip7 x9 \$ f9 ?9 ?' x" D
1221163 SIG_INTEGRITY GEOMETRY_EXTRACT Simulation aborts withsevere convergence issue when coupled vias is enabled.
0 j0 N, F( S. _# G1 P1221416 ALLEGRO_EDITOR DATABASE strip design for function type
! l0 P) o5 s9 i \; D1221931 ALLEGRO_EDITOR DATABASE Fatal software error when embeddingcomponent
% S8 f3 Z5 E$ ^1 o+ r1222105 CONCEPT_HDL CORE Moving Pins around the edge of aBlock causes the text of the pin to change its text size.
3 n2 n7 Q( c8 n8 i# X( b; B( L1222124 APD DATABASE Same Net DRC's exhibiting inconsistentbehavior.( ^3 D6 w6 b: [
1222272 SIG_EXPLORER EXTRACTTOP Cannot extract net or open SigXplorerafter selecting a netgroup
% \- j8 H$ _0 V! N* m& M6 V6 \( H1222329 ALLEGRO_EDITOR SHAPE STEP-Model Symbol which has place bound bottom is on Top
7 o, |1 R$ J: t4 Q a& o. m1223183 SIP_LAYOUT BGA_GENERATOR Getting an incorrect error message whenusing the BGA generator with a long BGA name.+ W7 \% o2 d2 Q, m. C
1223662 ALLEGRO_EDITOR REFRESH Allegro crashes when trying torefresh symbol
$ P. o/ o1 S3 V# q$ U& u1 B" Q1223932 CONCEPT_HDL CORE DEHDL block desend does not find1st page if its not page1
/ V1 K4 w' L+ P! y$ L; }$ @1 G1223940 CONSTRAINT_MGR UI_FORMS Unable to change CLOCK name inSetup/Hold Worksheet under Timing in CM.6 b: H7 p1 s% ^: Z! p
1224127 SIG_INTEGRITY IRDROP Is the old static IRDrop in 16.6officially supported?
. O; q' V$ q+ r: l1225492 PCB_LIBRARIAN CORE PDV expand vector pins resizessymbol outline to maximum height again: y: E+ d# i; I) K
1225546 CONSTRAINT_MGR ECS_APPLY nets where the referenced ECS mapscorrectly in constraints manager for front end but not in back end' `+ v/ G( |. r. E9 `
1226405 ALLEGRO_EDITOR INTERFACES File > Export > IDF ask for filterconfig file eventhough it is created in same session and stored in parent folder2 J9 {- A! v7 b- C+ R
1226448 PDN_ANALYSIS PCB_STATICIRDROP License failure about PDNAnalysis with XL and GXL* s: L2 N+ I$ U$ ^, W- j
1228721 SIP_LAYOUT OTHER File Export Netlist Spreadsheetenhance sort to be a natural method per Jedec according to customer |
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发表于 2014-2-10 15:09
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