|
|
EDA365欢迎您！
您需要 登录 才可以下载或查看，没有帐号？注册
x
http://pan.baidu.com/share/link?shareid=437717&uk=3826038294% g2 N5 \! l% B7 N+ s+ p8 u
. h0 [, V3 @' P/ x V8 }{:soso_e102:}
% u6 I1 b* @2 J4 {* ]5 I9 w! p& J" b$ V9 |* F, O9 ?+ p, v
DATE: 05-24-2013 HOTFIX VERSION: 010
% ]! W- ^* w- `8 j===================================================================================================================================. S) C9 O4 ~/ i$ ?) u" f. U, Y
CCRID PRODUCT PRODUCTLEVEL2 TITLE
1 L: b! u+ p! f- @3 }+ h. s===================================================================================================================================
* ~! n0 S+ l" L- a2 H1084716 ALLEGRO_EDITOR OTHER Getting an MPS error when updating CM from SigXplorer
+ R2 Y8 r7 f9 \1111430 FSP CAPTURE_SCHEMATI Auto-resize the schematic sheet so that hierarchical block fits within border
$ Z' x& A* w$ T- Q5 P" ^! A1119007 CONCEPT_HDL CORE PDF Publish of schematic creates extremely large PDF files# H7 p" Y: c& x' y! u+ @
1121020 FSP MODEL_EDITOR Cut-Paste from Excel causes empty cell in Rule Editor" V$ _- ]) ~6 }/ G; F" V6 Y
1124610 PSPICE SIMULATOR Attached design gives "INTERNAL ERROR -- Overflow" in SPB116.6' a6 }* Y2 `9 \& c7 r" [# i/ w
1125330 FSP CAPTURE_SCHEMATI FSP generates OrCAD schematics with components (Resistors) outside page border) u; g! Y) ?+ h. Q+ h! N* Y
1131775 ADW LRM LRM error with local libs & TDA6 n! Y) S4 c' ~, q9 p+ n0 n3 A. S
1131868 CONCEPT_HDL CONSTRAINT_MGR Many net-class constraints "fell off" the design after uprev and Import Design of GEP4' G0 L) R O x$ R
1132080 ALLEGRO_EDITOR PLOTTING Size of the logo changes after File > Import > Logo
+ \1 E" `7 K. E* C# x# X1134956 SPECCTRA HIGHSPEED Route Automatic fails with error when Impedance rules are turned ON in Allegro CM.
: }2 l' H; ?2 M2 w- D' E0 V1135548 SIP_LAYOUT SHAPE This design shows two areas with shape shorting errors that should not occur
' d8 N9 H) J" N) V! \1 r# q1138312 ALLEGRO_EDITOR MANUFACT NCROUTE is not generated for filled rectangle slot ?
8 J% `1 T* Q& N3 ~3 f9 E1139433 ALLEGRO_EDITOR GRAPHICS embedded netnames not displayed or getting very small upon panning after exiting 3D Viewer.# t0 i" U" Q% U n, t* b" p
1139509 CONCEPT_HDL CORE The LRM update changes npn device to resistor
' [& m0 _( ~- D- d1140752 ALLEGRO_EDITOR PLACEMENT Moving a place replicate module crashes allegro, Y& G/ p O& X& G( V8 [. H+ w4 m
1141314 SIP_LAYOUT SYMB_EDIT_APPMOD Design will lock up after changing the border using Edit Boundary in Symbol edior mode. |% }# V* q- R9 S: _% b2 d
1141751 ALLEGRO_EDITOR INTERFACES Allegro Crashes with Export IPC2581.& v0 i; i9 ~ s8 G, a% X* B+ p
1142478 CONSTRAINT_MGR INTERFACE_MAPPER adding constraint to netgroup causes CM & PCB SI to crash
8 w! a7 |( u( ], B% d1142884 ALLEGRO_EDITOR OTHER Boolean type user defined property doesn't export to the PDF
9 Y1 ]3 V' v+ s9 M1143199 SIP_LAYOUT DIE_EDITOR Enable bump remastering
/ z% G- U9 b- c* _" [! N8 S1143654 SIP_LAYOUT DIE_EDITOR Add X&Y offset when adding or moving a pin in die editor
2 n3 Y% k7 @: U$ H A, { |
评分
-
查看全部评分
|
/1 
发表于 2013-5-25 09:24
QQ好友和群
QQ空间
腾讯微博
腾讯朋友
微信
收藏
支持！
反对！
