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代码
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相关对象
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说明' o- c, k7 C0 [& ]" z) m6 L* G; K; I
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单一字符代码9 w6 p0 j, B* `; W- A
2 M* o* f7 L9 O' m
P& s$ u$ s7 o5 h. ^7 ]$ {L
K g S" ^9 \- f5 _( X6 ^/ j; { K$ x6 O$ S
Line
+ W* [: g! M+ ]+ ^ 走线2 U5 W0 X- X6 D: N$ L2 A& I
7 ^, q& L+ L q9 U! H$ @3 y. _
4 A* m0 U+ W: M, w( `P% @. a/ I; j3 ~
6 |" g0 q' D- Z; d Pin8 E6 P4 N% G. E- B3 t0 |
元件脚
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6 j9 }# z* J8 F' R7 gV
. I, Z- s2 B8 d% `- s- Y/ r* {, E1 J1 o( ?
Via
7 X" k9 k: Q9 x 贯穿孔
& M" P4 z* u" Z1 S) |/ ~
4 b: }& y* A# a$ e# |) ?- B
" }( R* Q2 d( H* _K
& g& p7 C7 V2 T1 I0 j: `: n S
' O u$ G! h8 A Keep in/out
; p% C# ^( }) W9 R 允许区域/禁止区域
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" @# [6 _; b" {3 n' m- @1 UC
9 W5 n- [$ L; v! v$ p! K! j: F* l" D b( X; e
Component
8 a3 j, G7 O6 y" e 元件层级4 e1 G$ _; k7 ^9 Y/ T
. t: A7 ^+ L/ e/ k
) w6 }% i: w; t5 ~" xE& N2 b1 A% R# `# k4 [8 g, x
4 }3 C: w) v/ s$ m1 ?8 L Electrical Constraint # n# d% h; {4 `+ C s: b
电气约束
3 l3 m8 r! }7 x1 ~, S x, B1 q
( k, \& D2 {" V: P$ }/ o ; \9 p4 c, V u% `0 l7 K
J$ J' K! }' X# s7 Y$ j
! h& ?# f+ `$ q1 o$ Y5 \ T-Junction
, z3 d1 N$ x. [ 呈现T形的走线* r( `2 H4 W. S. I* ]- }$ _, f: H
5 _ u# v% a/ s( _) `. m% F ' J& l, k4 H, A( s$ h
I b! p6 m) v, K" t
+ f1 m" ?5 \3 R Island Form- \8 O- i5 \* u# p: q1 T/ r' a
被Pin或Via围成的负片孤铜
/ O5 g8 s* Z! t2 ^: m* k0 Y {; y* ^& T2 Y
R( _% E8 Z; D0 M1 L! n$ S6 f# Q! t, o% [
L5 i5 B% Z$ k+ Y5 `4 Z
$ j9 `: k) x+ n f8 I
: U5 v( A9 P! n
! L. _" [- a- X错误代码前置码说明- K C. t2 y' n0 q' s% Y+ d5 V
3 ?1 ~: N- @ o& R
* P6 ]! x# m3 U& }& [% _- G
6 B) a1 Z9 x* X/ F2 k # i2 c: ] C5 B2 i9 a
W/ e0 U8 z5 V) b9 l7 N
% o" n+ N/ g \/ R# b! p$ B
Wire ! i) E3 Q7 A' k/ V H' y& I
与走线相关的错误- a0 o% U3 Y3 g# W7 T8 A
0 V- D6 p, O; P! _
5 d, K; b4 g, FD
+ m8 N: k: D0 ^; s( n! \- V% u2 i9 G9 j' b5 c7 \
Design
+ W( ?& l9 A2 f( t4 U3 R5 h 与整个电路板相关的错误( m6 `2 i% H: t5 N
m9 ]$ C, z. k" v' L ' y! U9 C! I! B S
M# m: i: n/ i: t' b2 V5 S# ]; `. g+ w
3 _% w& t& L* Q0 G4 Q Soldemask, Q' U' n7 f. t( M# ~2 Q
与防焊层相关的错误; T4 k0 c9 i! z$ m
9 m* f7 u' D9 O, F0 Y4 ^
$ X1 E2 Z) B* y; H7 b8 E x9 M4 S, p0 ]/ Q7 K" a
. t$ O2 o* R! C8 J- o D
$ o o6 \4 c2 \& `( g 3 U/ D# o6 ?, k( n8 N0 k+ J- v
1 u$ _" H' Z) F ?
错误代码后置码说明
$ @5 P$ |# ?/ f1 ~+ S3 b
* {' u. E* H3 c2 j
# L2 z7 n/ i& g& A4 \) _2 J0 G9 a2 o % }) D8 V5 B- n0 }8 ]9 q. a
4 m9 A1 u1 T" M
S! c* c8 }6 b7 H/ W* _; @5 `0 x: p
; M# V- d0 T" F: V Shape/Stub5 O8 V' ~- u, ~4 v
与走线层的Shape或分支相关的错误
* c! m1 p1 s$ x( [) `. |5 T- O# [
- |# q% U6 X6 D/ {& K3 {# y1 [ : l: q) d( W N3 U
N
q0 ^" t8 `* A1 g. V* i1 v) ^1 D2 C- \ X8 p$ `" ^3 S
Not8 Y; `+ g- P. o: l, n2 a. j1 B
Allowed
6 \0 H' V% G/ T, | g3 X8 ]+ u$ j 与不允许的设置相关的错误
6 G; s( W2 V. t" x0 z5 k7 Z# c8 b- Z) T5 P: I" |
' O( { @& `9 ?
W' O# O4 g* A- d5 H: N
2 z7 A. P- E5 ~ |# J. E. W+ P
Width1 _/ H/ [8 Y! i& j/ |
与宽度相关的错误- \- t' q: d0 w/ { [4 j. [
: |* V" f. u* @
; }1 `0 @9 `. r+ m4 a; T
+ [4 a, t: S6 M- O3 ~1 K
) M7 G- x, B) R; a6 x
, K% H4 G( Z5 H- y/ Q! E+ a7 ?
$ ?- e6 E- i5 A' v: r: d) Q - `- \! i8 Z1 i$ O7 ?2 v1 g3 u
双字符错误代码9 u, ^& b: N) k
; L A- J! }/ E0 |% a3 d m ; @( r3 F) `- P) q% }8 \5 U2 j
1 _# t: G1 e, z
7 \9 p1 \7 \# a6 BBB
) ?+ o8 d8 X+ G7 v& N
# L0 o7 v4 K" C2 p8 \: ^ Bondpad to Bondpad
2 `; w" N: D9 b% S6 Q Bondpad之间的错误6 |+ x* l$ k, w; B
! t1 f0 v5 U8 ]$ o i% }) j9 @
* G; ?. y7 z3 QBL, h. W0 R0 g! Z( j) S
& {9 R5 a% y8 b, ?& k8 {' ]9 l( j
Bondpad to Line
1 P; Y& n4 r- X% h0 K: [) f Bondpad与Line之间的错误8 e2 r1 i- |7 W3 m1 ]* Q
, z9 S7 @6 H7 b* ?- _
6 F4 |" [ o0 w$ W$ N" q" GBS1 m& H y# c0 m# {, g8 `( g
5 V0 e h2 g0 { g2 _) Z Bondpad to Shape " ]% T$ ?+ x9 P3 @" m J m- c x
Bondpad与Shape 之间的错误- A; \8 G$ `$ {/ B/ m% U
* k% _' }+ L) x H5 {
5 V5 ^. p; F& _3 |CC
! f/ F% Q" o1 t q$ \& K5 z: t/ r5 i3 a' L) l8 I
Package to Package! w! P9 }2 ?+ ~; @0 H. d
Package之间的 Spacing 错误# T8 \& l# Q/ I8 p% |
! b& S) K4 T, B% [' N& L! [0 k
3 u: b2 J2 _1 j8 c {( [) Q9 WSymbol Soldermask to Symbol
" n) f/ {6 z3 R) M8 {0 R Soldermask零件防焊层之间的Spacing 错误
\% t, @2 V: [& H/ J8 {- n( ^, L3 S
& e: C7 X! H: k 7 u, @% ?$ j# ]' B5 m& s" N) ^( t7 u
DF
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Differential Pair Length Tolerance
) l2 {6 \6 G+ w3 a: q* l, B, { 差分对走线的长度误差过长7 Q' w, ^$ u# I7 g1 U
& _ b+ G4 K, m# l
2 Y+ u+ {5 q* d! q8 h* z+ YDifferential Pair Primary Max Separation4 @3 e5 @1 S1 k9 J
差分对走线的主要距离太大% t! m V. V% ~5 y5 }* F5 E
$ G3 P6 _/ m1 S& m
- H3 \& G" @" n# Z( ]2 h5 S
Differential Pair Secondary Max Separation
9 ^ S1 S8 ]- O1 p2 B 差分对走线的次要距离太大, u6 T( |5 O! l. [1 O6 N
) |( \2 J V3 t5 Q- T. F+ t: }
; z% a' A T0 L$ I% I% c
Differential Pair Secondary Max Length
( W+ f! B F. Y& o% n/ I9 x! l! | 差分对走线的次要距离长度过长 A9 K$ D9 g: F& v
) H$ F. I! R ^1 v, O0 x 0 I9 x1 ]5 N8 t6 u H
DI8 j$ s7 g* P" s0 c% k0 b6 d) H
& n7 p& w$ O; [5 X1 @ Design Constraint Negative Plane Island; r @9 U5 d5 i: q( t
1 V8 m/ W1 O3 T( i
负片孤铜的错误
0 s# B, K" I( n! x
5 U: S9 f9 l" ~% |
9 ?) [; s) D: WED
. V3 J$ N/ \% q; u2 g
2 t# H' @9 ~6 ] c P, e6 C, m Propagation-Delay
0 q! J) }" j2 ]$ v 走线的长度错误 W K; w( k+ u* T" i3 ^/ o
4 l" f& k* W' Y' y. w# b
) b5 ?$ }3 a# R; v1 n1 k0 M! w- oRelative-Propagation-Delay
7 z" l3 @) Z* l$ _9 A 走线的等长错误
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: s E" F8 N9 O9 ^
EL
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Max Exposed Length
9 x* l/ J# w7 D( \ 走线在外层（TOP&BOTTOM）的长度过长3 ?: U, J1 J# S
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5 B2 H$ A; m. I# M8 f7 d/ bEP
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Max Net Parallelism Length-Distance Pair
" D9 n6 K# B1 R5 M 已超过Net之间的平行长度# B! U" J/ M4 b
7 f- |+ B0 [# f! P7 e
6 j( G2 f z6 }ES
& a! s5 o0 n7 A0 o/ ^, ~! `* a" O- ?" {2 T
Max Stub Length7 T( C. K0 n/ v" |0 C0 W* \
走线的分支过长! J* ]8 ]. M% ]& l4 Z
+ k: w2 Y1 v/ c, B+ Y$ v: r
4 Q) Y* {1 o u* T1 O1 Y- X/ IET! @; @/ M4 \ h7 ~' u* v2 p
. r1 D; J% a: ]& N3 W Electrical Topology
* K/ j' s w9 e, j; l6 @5 j6 b 走线连接方式的错误
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0 ]: Q c2 m6 J V& }+ S
EV0 ]( V+ R9 v/ i& D; i$ y9 F
, X* ^, Z! l5 ^6 f Max Via Count3 q/ {( ~9 h1 W& J
已超过走线使用的VIA的最大数目& U( n3 q8 Q9 a5 i2 {1 H2 ]' K
4 S# O0 g' K! ^+ x5 j ) |5 b6 u" G6 l$ o! h! Y
EX
7 b8 f5 _ U# d6 n9 }9 d0 b4 l2 L% p i6 i2 d# e+ d, T! d' I
Max Crosstalk
- E, R( H! E- V$ \. s9 `7 {; U 已超过Crosstalk值
: d/ d" ?* y) j" X L
8 ^ H3 X" u* Y% e: l T
! M7 l( p _1 `% ^0 {Max Peak Crosstalk3 c* C# Q; P, g% |% x, M3 |
已超过Peak Crosstalk值5 `9 c1 o4 y& I) t( O
w( {0 p# m/ V: h$ ~ 4 l$ O% o2 E% W! q
HH% k0 z5 \9 A7 N. X, Q9 B
* T# l) ^, q8 \0 i! S: x Hold to Hold Spacing
8 ]: N: N4 [5 }; Z I0 K3 H/ @ 钻孔之间的距离太近
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4 f' _/ h7 [' x) H
HW
' J9 d' p$ Q3 o$ r* b, \) c& ^8 ^8 r! X. ^0 o8 n
Diagonal Wire to Hold Spacing
; r& U2 B$ i @ U& K g# Q 斜线与钻孔之间的距离太近
+ C7 J& X+ k9 B4 y" n8 z
$ m( W' V# Q. i
" W* Z0 }- C. D% A9 y8 F0 a& C: g" sHold to Orthogonal Wire Spacing 8 X. b/ f* \2 N( D& |
钻孔与垂直/水平线之间的距离太近
% \: K+ J0 }+ y3 D" J, b# ]' U: @2 M; F$ k0 J8 `
2 ` ~" p( U5 `1 P& W0 Z
IM- c4 x0 v! e3 P; J" d
; m$ C/ G0 O% r1 A) k" e0 W
Impedance Constraint
! F7 n* v8 t1 z4 Y 走线的阻抗值错误
/ U# {( ~; ]5 d4 A# a8 n
6 H! y% k( e, J6 ? ]$ r* j 2 w! t6 j/ C; E- ]
JN
6 Z- }% ]- e; r2 `; D# F+ X9 |" _' ?
T Junction Not Allowed
3 G* W7 P2 [. b& g( L# r 走线呈T形的错误) Q1 q+ M, j6 y9 r6 L$ o7 j
: b2 S# d8 H" | @% [' T
! i( \! \& j. q3 ^4 y/ cKB8 _4 h4 u# v- U, T; L
$ d2 U b- {) p5 f4 F
Route Keepin 3 L8 ?0 v( |1 z8 L5 W
to Bondpad
, g2 B4 Z* \8 Y: v- o Bondpad在Keepin之外
0 } e* S8 d! n
1 R* u! p7 q6 t' Y+ d- K* G
# F' }# H. ^" M; ]+ v6 K5 Z0 D6 o6 eRoute keepout
% V3 v1 o, a3 ~" v5 v3 m: P4 Eto Bondpad
% O* a* w* A9 q2 W* _; \" b6 ^ Bondpad在keepout之内; R i- N4 M3 T* }
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- V, K* N1 s6 D+ K4 R3 \8 C" H
Via Keepout0 N' R% b; W% `7 [/ u' q6 r
to" h; v8 [' x/ x3 j! I% q
Bondpad/ l( _ H. C% `, l$ k6 l1 p( u
Bondpad在Via Keepout之内
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; t; ^6 v- _% H
KC/ ]* z! l8 a* W6 }
; Z9 o7 A0 ^. h1 O& p. k Package to Place Keepin Spacing + h7 u0 C9 }( j
元件在Place Keepin之外
2 Z, x% U- s: Q- m7 y* v$ A# L u1 i/ b8 P8 g$ R/ h
7 Z+ _# j/ w; j: |Package to Place Keepout Spacing# ^0 O# X$ E2 N8 @' x7 J/ G
元件在Place Keepout之内+ [1 r: T/ r8 @5 a+ Y' G9 m+ z2 S; l
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KL
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Line to Route Keepin Spacing
+ |, ?# e1 t6 k w" e O ], O* ? 走线在Route Keepin之外
& @1 z/ F, u; ]8 b! d% W( t
2 Y& X1 Q' c+ { `# M, u! b& q+ N& c
Line to Route Keepout Spacing2 X9 D, r0 K6 T$ {
走线在Route Keepout之内
9 H3 c2 T0 `2 X8 i: s) f2 f- X! I; B3 S
. ]! M9 L+ R2 EKS6 y _1 @+ }) Y/ s% {& e8 Y
6 }" g$ n$ ~+ K' h' O Shape to Route Keepin Spacing' @& }! B' p6 m. x2 K
Shape在Route Keepin之外
1 |- F% c& P# X% a5 S V: M) X0 m# Y2 D+ k6 u
7 u+ B4 Y5 F# n" ~- nShape to Route Keepout Spacing9 e2 y9 J. ^( V; R' f3 P
Shape在Route Keepout之内
" m5 H3 V7 n' l. C8 M! K! e4 G x& u1 X" E7 r; s, w9 n
) Y; k' Y8 X A* K4 K. A
KV/ @; v$ l) d: `0 p @1 P# C
: _( V) V& }! v# X5 v) y; @1 s9 Q BBVia to Route Keepin Spacing! \$ y* t: V( o3 U, c+ j4 i- {
BBVia在Route Keepin之外
% a1 [% M2 d2 _$ P' t/ E+ t# V0 l# @" c `* _4 `( Q" B( f9 b9 x
1 F3 f$ v* ?1 |, e" {BBVia to Route Keepout Spacing, h( N; c5 s1 ~+ W
BBVia在Route Keepout之内
2 j" Z/ q% O. o; j2 |( A1 w7 M# f0 n. |5 a8 J- e
! g0 V* K- a; `7 I1 I, ?* eBBVia to Via Keepout Spacing
! ~1 m6 D1 \1 K. [0 Z BBVia在Via Keepout之内
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. T5 C( u% D0 F& X) {" V# `
Test Via to Route Keepin Spacing
. N4 R3 [7 |. X" q( @ Test Via在Route Keepin之外: P" e2 T* Q6 ]& C0 p" M7 g# y
: o+ Y1 C3 b( d ) a/ O B" f6 O
Test Via to Route Keepout Spacing
" d" k2 b2 A7 ^: x3 u4 B6 c4 G z Test Via在Route Keepout之内
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. o( `1 y; V/ B4 ^. n3 A
6 `6 _, I( B! Y t/ i* h @$ ETest Via to Via Keepout Spacing: k' Y( T! L6 X! O# C
Test Via在Via Keepout之内7 j2 J7 X1 f, B
6 W' e4 j9 J d# c/ o, b. X; v! K9 A9 x 9 ?8 h. p. p$ ?2 |# ^ p
Through Via to Route Keepin Spacing0 r. c7 x. m! W5 \2 F" d
Through Via在Route Keepin之外
( U6 d1 V9 d0 A$ g Q* d/ ^/ o+ R7 R, l0 }. y# L
9 [* a! b, z$ Z) o6 u3 H, j: |
Through Via to Route Keepout Spacing
3 P% z$ p0 a) W6 x$ Z3 S Through Via在Route Keepout之内3 ~! u- u. i. i' i& b4 h. T
5 E9 F8 Z2 e0 x& q) A/ v6 Z# Y
1 F8 {: S: v. J
Through Via to Via Keepout Spacing
6 E! p$ W3 z7 L. q Through Via在Via Keepout之内: H6 R7 `6 m! B; o
9 F4 v) P' l+ X L
! v* Q4 u" Y3 w0 Q4 qLB
/ |4 C5 u# T# @9 R8 A& E+ E8 U2 l) f7 Q; q5 Z- O! g7 W
Min Self Crossing Loopback Length$ \( ]1 H! u( l; `5 R" x {
无# m) W* R: P9 ^; w7 u0 g
" C/ O/ x: e( P 0 z5 O. [* p* {0 A1 R
LL
4 d% }9 R+ d/ X6 k: ]+ K; r5 k' d/ s& T3 L3 {# Q' f" H1 ^
Line to Line Spacing
) X! c% o- ^6 \5 f- |6 J. F 走线之间太近
( K. a7 ?) Y+ u9 ?8 w4 H6 M0 D2 }9 r( H" [
( n- p/ ^! \* ?; P7 K/ B( e! g1 q: MLS6 q- n: J" F/ p- E* ?4 I2 T
" L1 V. y7 Q4 u% g A Line to Shape Spacing' f0 f" m. l" z
走线与Shape 太近 9 C9 e8 T8 [- f4 B& `" f
3 w/ m! @# @# @/ z. O4 e: Z - d+ O' q' O! [9 i7 F0 X
LW6 Q# N2 h7 Z$ l" |
8 R" C1 T0 @& T: N Min Line Width
% U* Z9 D i2 h 走线的宽度太细
o( y, J5 c! F0 b9 T( M- v# ]
0 d" n8 S# y! Q7 U8 P 7 E- ?/ P0 k' v) y: a4 K( z+ b
Min Neck Width
1 d+ m; Y6 h* I& o! T 走线变细的宽度太细
9 _- n% m4 h( P( Z( o4 v/ p) c
+ ^' ~: i: u1 X% c( u
) r2 R1 i0 _& J1 L, }: LMA% S& m( D2 L; E4 `: ^7 D) L+ `3 A
& |- a% R8 E5 @1 N# s0 W3 n
( j' ~! ]7 A7 {; t. f1 e% CSoldermask Alignment Error Pad* F# q0 k8 C) }' ^; |& i
Soldermask Tolerance太小3 U, S; g% `& L, I0 s
" {% m, \4 |9 M* k$ C- ?5 _2 [8 G : L, a" {- W' L. B! X* S* M2 z
MC$ y, n/ _ i! l* h5 t6 Z0 D p
3 E" m7 J6 A2 w/ ?" W( U Pin/Via Soldermask to Symbol Soldermask
0 c6 ?4 }. J* L; N$ g6 [6 n Pad与Symbol Soldermask之间的错误9 _' N3 U: l* @, C t3 c: s
' n g# G! R& n& K3 _* x4 K
9 ^% e0 h( G+ s0 O* G% ]
MM
' C3 e3 A$ \1 f, u2 m0 `& I6 [- m3 Z3 N; r, X' B9 ?! D
Pin/Via Soldermask to Pin/Via Soldermask
. G5 W" a8 i& m6 o; \ Pad 5 t# R, m. K5 E" f
Soldermask之间的错误
& N1 S& V+ q; M/ U" j \8 b0 J+ W3 h- J9 J! G
6 D1 Y/ |- i: g. ~/ TPB, w# Y {( t7 |( M" C2 a! v
1 k/ W5 F2 G" c2 E/ M5 i
Pin to Bondpad
% [2 R- n5 t: i, T* Z, E Pin与Bondpad之间的错误8 {- t$ L9 Q8 b7 |% I0 y
6 e' Y) H: B2 W1 x
8 f/ z" k) Z: G9 l: q5 ~ _PL
- p1 B ~$ ^3 b1 j |7 ~5 H( S0 I4 q3 k) y; @4 q" m+ L
Line to SMD Pin Spacing # }2 e$ U1 U: c1 V+ a2 O
走线与SMD元件脚太近5 |5 s7 D, m; r2 h
& [4 G$ T3 k+ L+ y* `; q
, `3 e' R4 a# s4 ]! Y
Line to Test Pin Spacing* A% P8 P; x: k5 W: @* T
走线与Test元件脚太近
( v. P; U' h. C2 ]6 W
2 f! `4 x0 B* Z
4 j+ t8 J4 _1 o% g+ oLine to Through Pin Spacing2 Y2 K; b+ U$ _* m0 w# i. e, Y1 ?
走线与Through元件脚太近
: d5 F! D8 c8 W( i0 g
) l6 S* o9 D7 X7 h, ~ ' N% ?7 f; U/ N
PP3 b1 [9 |2 r( j4 k$ `1 t& j
5 [# S9 t4 c; G. I$ F# o5 T- i8 N SMD Pin to SMD Pin Spacing
; g$ P, U4 c7 O0 Q9 E SMD元件脚与SMD元件脚太近0 B1 | v* a$ S2 Y4 y0 p
. p8 @; |2 s3 i' J6 l& r Q
8 Y/ j- u: |) `2 Q; R
SMD Pin to Test Pin Spacing
2 ^. s6 D9 \! |; T7 g SMD元件脚与Test元件脚太近9 f0 F2 x% n% L% ?0 `- ]- j
9 w4 J; a. z. J6 c! ?* i% l
4 T# b( t& b' c4 Z, xTest Pin to Test Pin Spacing8 [3 @( X. V) [, s& @; s5 `- o
Test元件脚与Test元件脚太近" h& T# ]9 k, x# U& n: Y
( `4 @# k6 q7 W, ]( s5 R
# K4 ^: e' I4 h; r4 zTest Pin to Through Pin Spacing
2 H& w3 B' ~6 s. Y: u Test元件脚与Through元件脚太近
, Z6 Z% d5 R9 J, j/ i% J5 J
* o0 @8 l2 p* ?$ H& k 4 C* j: l8 I/ `* d
Through Pin to SMD Pin Spacing
; W6 J) v1 V' l6 b3 g! x Through元件脚与SMD元件脚太近
+ ]9 @5 V, E; W3 R/ Q9 q8 ^
, ~( v4 \0 ~5 K2 W" \6 S0 F
6 u% r h' o) `: h2 S3 O6 LThrough Pin to Through Pin Spacing% \. w/ p" _6 T6 c) r2 I
Through元件脚与Through元件脚太近( b* {5 @( r# {5 }- z$ C) ]; R
* K; |( Y1 z. s$ B# W
/ z, U8 b) _' fPS
( q* k0 ?8 ]: v6 Q4 m
) Z5 F: {2 `9 J, a/ ?" {: E3 `' } Shape to SMD Pin Spacing, m$ [; @3 ~+ S: r; q" H. x/ N
Shape与SMD元件脚太近; X3 q; v8 s' p _
# ?) _( P ~' j& V
: ]; e* @% t1 S4 ]5 w( IShape to Test Pin Spacing& g( w- P6 Z% J' [ P! W) P
Shape与Test元件脚太近+ c3 V9 t: Q3 M1 Z) ?7 ^
" L% c; u* b' I3 J : D3 @$ C5 a$ q1 Z! O; g
Through Pin to Shape Spacing) G+ i' W3 c7 X: g' }( ?
Through元件脚与Shape太近
( H2 n& j' Y* g- D
7 b9 C; h+ k5 |0 l% p$ A% v) ~ / m" x, n9 \+ Z* u( E
PV6 T: Q6 ?0 M) N* x9 ]
# [& n2 q+ L# B BBVia to SMD Pin Spacing
. i2 y3 h8 Y0 B0 {! r, s6 h BBVia与SMD元件脚太近0 k7 j; P( e* C" g- k0 ^
3 s3 |( n* Y4 k+ S7 e5 ] y 7 C- C/ C( u# w% r& u
BBVia to Test Pin Spacing: W U1 D4 @3 d+ K- I) y- s; H* Q/ v* T* M! p
BBVia与Test元件脚太近
+ v) L; s0 |( I
- C& m/ T9 q; _9 B8 R2 ?+ q& N Z! w) i) k+ ~( D6 y5 _5 H" X! f. i
BBVia to Through Pin Spacing
' g) S4 h) c* p5 Z. g7 |8 T- I BBVia 与Through元件脚太近
2 V* d7 }2 j1 j1 e% b) @" J% B5 p2 S4 M
4 g' z$ o3 Z+ I3 a( m3 eSMD Pin to Test Via Spacing& b* ^3 \" _9 h5 C+ f j" _8 K' w
SMD Pin与Test Via太近
/ j5 V6 M6 T7 |! b) \! F2 Q# ?4 N- e
0 W! W% c; f! R J
SMD Pin to Through Via Spacing
! w5 [3 g; v; L) q5 V, k- k Q" H$ n( w3 v SMD Pin与Through Via太近; U0 j4 U1 u* [/ I! }: ~0 B
2 Q7 M- z* Y+ k/ K3 A1 _
6 A. F; Q) ?* @, g4 rTest Pin to Test Via Spacing
5 i3 a4 `0 k0 @8 `+ l Test Pin与Test Via太近/ L, [1 Y9 S0 y! L& w# e- R
% q E* W; j# m, T$ H, q$ B; F ; _4 T9 t, X* E" s
Test Pin to Through Via Spacing
& w: d3 t) o. w& E8 ~* X Test Pin与Through Via太近& p0 j( n8 M: V% t( S. v
. K2 S" }+ L2 K
* N2 q; y. O, P- j# ^3 P! L
Test Via to Through Pin Spacing
9 Y; c+ l: x7 f) r2 y) f7 q Test Via与Through Pin太近
8 m$ W5 a7 U9 d/ O8 L, F5 F, p% U( j. w: T+ t' z: T% W
& T9 F1 {: v; r* ]% Q: A
Through Pin to Through Via Spacing" e/ `4 M. n. Q8 f2 P
Through Pin与Through Via太近/ [% m8 ?: t" M: a! M+ _) L
5 k; \; G T4 `4 l
9 m% }) t4 q% C. q: F3 P' q
RC
3 W! W* j Y( V! Z8 A
/ I( ]) i5 W7 g7 G$ j Package to Hard Room& s5 V8 ?6 `- O0 g3 M- n0 \* r
元件在其他的Room之内7 p! H. b0 r! W) }
, p% R7 t+ A ]; o
6 `/ W9 E6 U3 \5 A6 K! lRE' k3 O1 X0 `! G& a- r4 V
3 F% Q6 X) K& h5 \$ J$ ~4 [ Min Length Route End Segment at 135Degree
/ q* ?* y9 N5 V( P- ~8 f6 T9 ^+ ^+ N 无
+ s1 Y3 n1 T( ~9 `% o1 R
$ R' Q, T& L6 ? 7 @ K2 ]4 V$ h
Min Length Route End Segment at 45/90Degree" p# h% ~3 z% `" r, e
无. q* _; E7 q: {3 S
/ {5 e$ |% o7 y* |8 D# P1 k. n
3 G1 G) o7 d1 O6 L) |) \. o
! ]( A6 J" l8 @ A7 _3 @2 O6 g% }SB / a( a) k, C$ M3 i: Q4 {) N2 S
8 U, ^$ q: h, d8 Q! _3 Y 135Degree Turn to Adjacent Crossing Distance6 |$ m; v3 |9 U, M3 _" f- F+ G
无
# I- z' K2 [# J
0 w! N1 `' J# C" O, v
- a2 e, e/ n6 \. ^; ]90Degree Turn to Adjacent Crossing Distance
1 e2 \/ [3 C- H# K 无$ O+ S5 P! K7 z
( d8 c- P" z+ t& _, y! A/ S
6 {& Q2 `5 J$ @3 c: S8 q2 }SL
2 T6 |+ A& A0 h5 ~7 i; u$ Y r* J
G q2 q* _5 L1 [! \' A+ }- M0 S Min Length Wire Segment* L. p6 U/ {+ [7 ?# z
无
& z3 z3 U5 t9 f- n( F9 h' @8 s, d
: b B, l" e/ H, K2 ?Min Length Single Segment Wire0 B. w/ d6 B; ^& D% @
无' N3 D" W" D7 ^' y+ q
( j" }0 J- h! m; i- d
$ ^) y6 `7 C# T- T; z; y3 ISN8 A ]& O# P/ ]- T) m
A. k( e; O" L3 N" \" Z: Q1 ^% j Allow on Etch Subclass* Q+ L. Q6 j) n I
允许在走线层上, O3 m$ Y+ G. n( d* n
. H1 Z$ G9 c% w" o
SO
2 D& f/ c8 d! e/ R# E; t8 O
- k1 F5 K) y5 P: z8 R) s+ R Segment Orientaion
) M7 Y/ T2 y" X' O/ f 无
3 A* g4 _1 v3 l; Z. R7 }3 c: x$ o# I
# `, F3 s) F0 G- E" X
BB9 \2 _ u" G: i
/ E' o& ]8 Z* h Bondpad to Bondpad8 f# { b7 m I i2 h7 e
Bondpad之间的错误+ e$ @, V3 X! D* M6 a
1 o0 _- U6 m( o+ M6 X1 g 2 t$ _# s& n- t5 |9 J/ }! E7 d) e
SS8 [) A1 }5 y2 E7 Q/ c; ^
& ~* X& ~2 w& }/ j" R8 [- K Shape to Shape
+ p+ ~: \6 q) H P+ N4 b$ L' q Shape之间的错误
/ s. d: O) N+ c8 t1 U1 X( V/ J: I0 A: y7 J' J; q5 D7 B z+ |! t
6 ]9 F2 _5 K5 C
TA ) j& x5 y$ A5 }) x/ l, k8 ^5 R
$ b8 `* M0 O, _0 r7 `
Max Turn Angle + [% A6 ^' W+ k0 s z) m" ?
无
; J" {. q! i, G4 l9 l' n7 y& G, ~2 O, y
, m, @. h0 z" z; S- g
VB* I( I8 P4 J5 c5 e1 l1 y9 e0 Z- |
, q0 y$ O( s+ f* M7 I Via to Bondpad
" N0 f9 ]. S% h; P; Q0 R Via 与Bondpad之间的错误
: c4 T$ v1 m6 |) d& a- p- N m# c/ x1 g# W+ K' s, }
6 S0 i) _8 ]& y8 m8 |( Y; aVG* H% K- Q: w ]' q5 a) y0 ^9 E: _ S0 s
! W) ^" B9 ]% K/ M* l2 E
Max BB Via Stagger Distance
- a7 z( k! v1 t8 ]6 A 同一段线的BB Via之间的距离太长
% [1 l" p9 F' ~1 Y( E; z" e
. l6 J& x6 m) k" u
7 x/ f; [0 m' L3 k+ }Min BB Via Gap
4 h" \3 Q8 L( x BB Via之间太近1 `1 |7 N" P' y7 ?
, z( }' j u1 }6 A% ]1 S6 _
3 u1 H5 f5 x1 KMin BB Via Stagger Distance
' J, k( i, [; ?) ^) h! @ 同一段线的BB Via之间的距离太近9 \4 \& t- U+ P3 @0 o/ F
5 {! w C' n4 W' q
9 @& M# G" E8 h$ ~/ j/ BPad/Pad Direct Connect3 s1 @) W0 ]% z9 S
Pad 在另一个Pad 之上
( y6 \: [5 R- d& z; f* Q$ _2 h( L/ b. z+ i' K# i* r+ `0 C
* _+ A( @7 F7 N4 \7 B
VL) G. |9 c9 b4 U; N8 d) u
+ d, v( A4 F% j* L6 A b% [: V2 | BB Via to Line Spacing6 d# V W0 }% k- ]! D: R
BB Via与走线太近8 u) O% }) d2 D- I$ d% H
+ F# t2 D' |2 b B. E) e : V- \2 W: H8 x" W9 Z
Line to Through Via Spacing
; }$ A# i) g2 ~& I) } 走线与Through Via太近
9 o* v% W, l8 x8 E, u3 ]1 v& }+ @9 j2 J4 B2 A
0 s) S: m- s* D8 s6 _
Line to Test Via Spacing
5 s2 B6 N! F H- T1 K 走线与Test Via太近
% U1 {3 `+ ~) b- y8 Y5 O8 T. e% u3 Q. S
. d$ H6 J- S% i K4 F1 m1 J, ]! ~VS0 W: j T7 M# ?( D5 {0 ]
0 n% ?$ e9 V( `
BB Via to Shape Spacing
/ P! C6 z; ?/ v BB Via与Shape太近
7 A3 _ M N9 W* \' z5 m
$ h; d3 ~1 P# S3 [
: t; R5 m( D0 j/ S8 [/ AShape to Test Via Spacing
3 p+ s0 s7 |& U Shape 与Test Via太近) l, Q! \. v* X7 D; p, Q
( z& s$ d4 H1 R2 O s/ H5 |
, |- n2 i# u5 f3 A, V q, W, ~Shape to Through Via Spacing
# \! `' m b3 p2 v3 ~+ h. K Shape与Through Via太近
- Z/ D9 I, m3 [9 U7 D1 X8 n; d, h1 L; W! J+ m2 O
6 B$ T7 I0 o& `VV4 S* X0 Q9 P" }6 v( r
6 T+ y* I: B u* ?% T BB Via to BB Via
5 X6 X3 ^4 n8 A# f- BSpacing* v1 n8 g+ |- r% ^$ M- z$ V
BB Via之间太近
9 w. O- t: f6 ]7 I5 v) a% ^; a2 Q5 U( d& I" E7 ^ e! F* ?
1 H" I2 l' b5 N) K) k- g& \6 iBB Via to Test Via Spacing
: i2 Z1 v4 n/ l8 y2 @+ d9 A BB Via与Test Via太近6 M1 z) X5 |1 V. U- t: `
* o6 v, @+ S0 o# X
+ \5 e1 m$ o* @; g7 R2 jBB Via to Through Via Spacing
% |8 M# V$ d! W3 R) d3 I BB Via与Through Via太近
4 x/ w8 a, k. _- a5 v2 {9 O
4 z: U* i: U; C6 S/ W8 j
3 i4 T& l: k) \# XTest Via to Test Via Spacing% W1 H& g: `* R) W3 T
Test Via之间太近
8 {8 S" T& G* w8 E" q6 W- h; X: r1 T! O1 I1 d! O
6 i- z+ e) l. J/ F5 HTest Via to Through Via Spacing
; W0 d9 H, p0 k, \' j/ N Test Via与Through Via太近 C" j; ?- `* E' w+ q
9 e/ y( [ G$ e- e6 c7 ^9 N$ q- s
. r# y. D- g# d8 G& o0 AThrough Via to Through Via Spacing
/ X) u5 f4 |0 s2 z2 H6 K* ?: l Through Via之间太近
: @4 X( k0 v4 b- x# ]9 w" j% x* I* ?0 o$ g8 N- u4 y
) ]9 H1 |; U9 b# e8 c* dWA
& v. e/ f5 j. |) c# n. j% U4 [; n# j0 }( o& u7 J
Min Bonding Wire Length
$ N! D/ ], u8 \! H* i Bonding Wire 长度太短
) w# ^: u' B- c' M- |2 L
# E' c2 f2 s, d P
7 l* m+ V, J5 ^WE3 V4 p- \4 L* W- i2 {' r/ v
* W& R/ J' p: @8 k
Min End Segment Length
% q) J/ G `; _9 } 无
4 i3 }1 R6 ]; }1 A' D- ]1 q8 o8 b0 l
( O# }- c, X0 ]) a+ XMin Length Wire End Segment at 135Degree
5 [- X! f) A, F I 无+ e: F+ n Z" R+ x
F7 O. I% Z/ [, y/ m p # q. c5 f- O1 |$ ^
Min Length Wire End Segment at 45/90Degree. L9 N3 M6 h1 Y
无! q K# C p. H5 J/ A0 t# Q3 G
: N- m5 C+ C* w3 Z8 Z/ W$ J8 f% |9 A / J8 U e. ?* J; p8 a5 N! \& a1 q
WI8 l' X1 [ ?0 |: D
: R8 Q' \$ l# S P" @6 b
Max Bonding Wire Length* J0 n2 z# T( Q( A2 f
Bonding Wire 长度太长
- ^9 i s/ Z f" X% l3 U" l
1 N' B6 P$ K. b# | 5 v2 O& q3 k* ?9 Z
WW
9 K( E1 I1 N# u1 G2 a7 j- W
/ B$ O; X" s6 A: q5 T Diagonal Wire to Diagonal Wire Spacing $ L% V4 z& |6 D1 z$ U
斜线之间太近2 n" p/ w2 J6 D
b2 A+ {1 d* q7 @& Y 8 m6 Q3 N- g5 c1 |
Diagonal Wire to Orthogonal Wire Spacing
; g# ^+ s. Z" D2 T0 l! A 斜线与垂直/水平线之间的距离太近
4 Q0 `, _. E: @
; N) P+ M/ M! u/ D3 K7 A2 } 9 q. q, a' u0 n8 B
Orthogonal Wire to Orthogonal Wire Spacing
- v7 H( v! U' W. A4 C 垂直/水平线之间的距离太近5 }# t( w& v) ?! v( A2 Y2 U9 D
8 q9 V, F( A M9 @0 x
* ^; K! h( k, P' D% y, c( i2 ?
WX
, K7 \/ S) A2 W" U# P8 M5 x4 d0 [ F6 i8 L7 }4 y6 J
Max Number of Crossing3 @3 y; w2 W0 i) V% q" r& ?
无8 C% z# p8 \0 V* P
, a E+ v i7 j) o5 G
, y0 u1 Y6 x. Q1 ?' Y
Min Distance between Crossing
. N; E. u; g" | 无
& ?7 f5 i" V! Q, \5 o+ D& v) N5 j2 t6 [5 s; s
+ Y7 c3 K% S2 q3 q% m% SXB; ^2 R) f5 O* f$ |. H
8 ^. _8 A& |# L$ @; L0 x 135 Degree Turn to Adjacent Crossing Distance
* W1 _% b5 _$ O! u) r 无% D( T" x/ w- w% k( | Z( r
( [ o$ r3 j5 C c+ w: g + f: ~. t2 i" X: P$ j5 n1 p% w
90 Degree Turn to Adjacent Crossing Distance7 Y, @) |1 f3 v
无$ {( I. p9 t9 k! \) [" [. v
# t9 P) m3 J) d8 C) @, @
( H6 ?- P7 T5 \+ h. _' N: c8 gXD, I2 c/ E. w/ F$ v6 ?" @. c
( [2 A# @8 ^5 G4 f6 y- Z
Externally Determined Violation
' w% @: z( B l+ s 无' D, T7 o/ B8 M6 N7 B' v
/ t$ S* b# [6 e0 ~ ) |& K. m; Z8 O0 p F
XS
& b. {) u1 y" y) A0 S4 N
+ `+ C( v1 n8 P1 v! e Crossing to Adjacent Segment Distances
( D1 U" X6 T8 @( t 无 |
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发表于 2010-4-23 01:18
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