PCB 导入网表出错，但是又不知道是什么错误...

xiaoyunvsmm · 发表于 2012-12-14 07:38

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错误信息显示如下。。。求大神帮我解释一下。。万分感谢~~

(---------------------------------------------------------------------)3 v4 o* D) |# X" o% G, q4 D% d
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( Netrev Allegro Import Logic )
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( Drawing : SDX_Allegro.brd )5 ?; T! H7 i, {3 b1 b* M+ w
( Software Version : 16.3p004 )% o% @7 O4 z) y) B
( Date/Time : Fri Dec 14 07:39:06 2012 )
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(---------------------------------------------------------------------), Z9 s5 X- A( H' q
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------ Directives ------
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RIPUP_ETCH FALSE;: n7 V! J p$ M
RIPUP_SYMBOLS ALWAYS;
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Missing symbol has error FALSE;- d2 Q( h1 W N% u6 B5 h6 K, Q
SCHEMATIC_DIRECTORY 'D:/SPB_Data/SDX_ALLEGRO/SDX_ALLEGRO';
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BOARD_DIRECTORY '';0 a% z( @# q5 {7 W/ s3 f$ T7 u
OLD_BOARD_NAME 'D:/SPB_Data/SDX_ALLEGRO/SDX_ALLEGRO/SDX_Allegro.brd';
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NEW_BOARD_NAME 'D:/SPB_Data/SDX_ALLEGRO/SDX_ALLEGRO/SDX_Allegro.brd'; R2 D, p% t/ M* U
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CmdLine: netrev -$ -i D:/SPB_Data/SDX_ALLEGRO/SDX_ALLEGRO -y 1 D:/SPB_Data/SDX_ALLEGRO/SDX_ALLEGRO/#Taaaaaa05284.tmp
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------ Preparing to read pst files ------
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#1 ERROR(24) File not found% R! N( j+ a+ T H. R) |: p, i$ `
Packager files not found' l3 A% @! [/ F
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#2 ERROR(102) Run stopped because errors were detected
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netrev run on Dec 14 7:39:06 2012
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COMPILE 'logic'
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CHECK_PIN_NAMES OFF
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CROSS_REFERENCE OFF0 j$ T1 t8 X9 J5 B0 X
FEEDBACK OFF
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INCREMENTAL OFF
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INTERFACE_TYPE PHYSICAL* D- x' y- V3 Q: j% Q$ f
MAX_ERRORS 500
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MERGE_MINIMUM 5
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NET_NAME_CHARS '#%&()*+-./:=>?@[]^_`|'; w6 X% i3 L' o& v) X: v% Z
NET_NAME_LENGTH 244 o- X) d0 M+ B/ H$ f
OVERSIGHTS ON! L. Q3 ]2 W) H! w
REPLACE_CHECK OFF% u. ~ y9 G$ \. W; e' z/ Z
SINGLE_NODE_NETS ON! b( x" Y. O r8 n3 i& ?
SPLIT_MINIMUM 0% ~& V0 o% j" a* w% m/ ]! {4 b
SUPPRESS 205 G* f+ r/ q" L* u
WARNINGS ON n, @) E- F+ L& p" L4 _9 |
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2 errors detected
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No oversight detected- G7 X7 L& |/ _; i+ I9 ~( n/ b7 V* a
No warning detected
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cpu time 0:00:46- ?* j2 _6 y5 \5 o. R9 B, g$ L
elapsed time 0:00:00