错误如下5 l6 f, {, a9 s) }
ERRORack:679 - Unable to obey design constraints (LOC=CLB_R38C1.S0) which. W; q7 i9 D3 a& n. v
require the combination of the following symbols into a single SLICE2 [" w( |+ [) {% F z0 @4 } l" T0 l
component:) k+ m) x* g. ^& b& a( y, _2 K8 n% \
FLOP symbol "Chain[37].uChain/Node[0].uNode0/uFdce" (Output Signal =3 d$ r% b9 q( M3 h
Chain[37].uChain/wOutA0<0>) : _" ?% p6 ~! m FLOP symbol "Chain[37].uChain/Node[0].uNode1/uFdce" (Output Signal =3 y# u: I, I" k% j
Chain[37].uChain/wOutA1<0>) $ v0 e9 X" R0 |# L+ k( R1 G The set/reset signal Reset_IBUF_1 of register' @* i* {& W4 m( g% M
Chain[37].uChain/Node[0].uNode1/uFdce doesn't match the existing usage of the5 w7 @, V% d; ?# X; r4 w) D
SR MUX. The signal Reset_IBUF_2 already uses SR. Please correct the design ! r% w6 P; f& u constraints accordingly.. l( i0 i7 g" a$ Z2 y4 j$ ~; z
请大侠帮忙
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发表于 2012-6-8 17:35
ack:679 - Unable to obey design constraints (LOC=CLB_R38C1.S0) which. W; q7 i9 D3 a& n. v
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