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本帖最后由 hzqydq 于 2013-4-9 15:11 编辑 / S, L) P8 O9 n
% ~5 J- }5 w$ K: z1 @' THotfix_SPB16.50.041_wint_1of1.exe0 ]6 Q0 S! }+ {- J ]+ M* a
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下载地址
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" y/ ^4 g8 n K7 _7 ahttp://dl.vmall.com/c0kgf7xkaj8 c6 e0 J5 y% F. g9 b$ k& y
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. F U# Y. o, L2 ^: P" N* NHotfix中只需要安装最新的版本即可。7 z1 W3 A# _2 k; t; l/ y9 |
DATE: 04-4-2013 HOTFIX VERSION: 0417 j$ S7 ^8 V' T- H4 n9 U
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4 S' f5 N! \9 ]6 a; k3 SCCRID PRODUCT PRODUCTLEVEL2 TITLE5 r: B- {: ^4 D
===================================================================================================================================
+ ~- e3 x6 p2 }" e+ y( \1 m: C835944 ALLEGRO_EDITOR OTHER Customer want to change for Jumper symbol by other Alt symbol.
6 ^, K+ x3 }& g3 \988019 ALLEGRO_EDITOR PLACEMENT Allegro hangs when doing place replicate create
; N8 y/ z1 }5 a; t. Q; Z1065641 PCB_LIBRARIAN CORE PDV symbol editor is crashing when deleting a group using delete or CTRL+X8 J5 z* q& @; [, ?/ t D/ M2 G+ q2 l
1073152 CONCEPT_HDL OTHER Printing Published PDF schematic has missing lines
' J9 m+ A+ l5 L3 M9 r1082587 FSP FPGA_SUPPORT Support of Xilinx's Zync device4 n/ ]* M3 ?; ?0 o$ ^* w
1100945 SCM SCHGEN SCM generated DE-HDL has $PN placement issue
# S& [1 p/ g. }( Z9 T0 z1107172 CONCEPT_HDL OTHER Project Manager Packager does not report errors on missing symbol/ S0 O$ J* }2 W5 X$ O0 y
1107397 SIP_LAYOUT PLACEMENT Place Manual-H rotates die) a* Q$ W0 y( V( [# v
1108603 PCB_LIBRARIAN VERIFICATION PDV Tools Verification > View Verification (CheckPlus) leaves <project>.cpm_tmp.cpm! r! ?8 y c2 l0 B3 I
1109466 ALLEGRO_EDITOR ARTWORK Artwork create some strange gerber lines for fillet.; V$ t3 |2 |1 @8 W. @! f# A
1109926 CONCEPT_HDL CORE viewing a design disables console window
( s) O% @3 @6 R1110077 ALLEGRO_EDITOR DRC_CONSTR Duplicate Drill Hole DRC's are not shown for Pins overlapped in same symbol unless "Min metal to metal" DRC is turned ON: H9 _9 E) `, K% _- \) t& i
1110264 RF_PCB FE_IFF_IMPORT IFF Import in DEHDL has component offset& n% y4 }5 e4 X7 O& G
1112295 APD DXF_IF Padstacks offset Y cannot be caught by DXF.6 u- A6 Y: X; Y4 x4 ^
1112395 CONCEPT_HDL CORE BASE\G for global signal is not obeyed after upreving the design to 1650.4 X& ^+ p [+ P, u& R
1112774 GRE CORE Allegro GRE not able to commit plan after topological plan- k3 {4 Q* y+ F: h$ ?/ y, \
1113317 CONCEPT_HDL SKILL skill code to traverse design not working properly& | y( q- l$ |: u X+ {: X: p
1114630 CONCEPT_HDL ARCHIVER Archcore fails because the project directory on Linux has a space in the name
6 J d* F6 z* d$ H1114689 CONCEPT_HDL CORE Unknown project directive : text_editor- M0 D" `0 k4 u7 v4 w8 q+ `
1114928 F2B PACKAGERXL error (SPCODD - 5) while Export Physical even after change pin from A<0> to A$ K# x) {: _ H- p" b
1115625 ALLEGRO_EDITOR SKILL Design extents corrupted when axlTrigger is used.9 h5 d7 l. W( K
1115708 ALLEGRO_EDITOR INTERFACES Export DXF is outputting corrupt data on one layer. |
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发表于 2013-4-9 15:08
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