* r& D, V& v5 D" F! F" `8 KDATE: 12-12-2014 HOTFIX VERSION: 040===================================================================================================================================CCRID PRODUCT PRODUCTLEVEL2 TITLE===================================================================================================================================577694 ALLEGRO_EDITOR OTHER Need to retain padstack edits during "Refresh Symbols"1105280 FSP MODEL_EDITOR Negative Voltage leads to 'Internal error. Invalid voltage value -12 specified for pin'1198148 FSP OTHER In the Symbol Setup form instances instantiated multiple times must be customized individually1200015 CONCEPT_HDL CORE module_order.dat is generated for sym_n view automatically1275209 PSPICE NETLISTER PSpice is not considering 3K9 as 3.9K if inside a condition in PSpice template1297335 SPECCTRA FANOUT Wrong fanout created in PCB Editor on using the Route Automatic option.1316637 CONCEPT_HDL PDF PublishPDF does not set arc lines to the defined line width setting1320581 ALLEGRO_EDITOR OTHER Dangling line listed in Dangling Line report but no line exists.1326104 CONCEPT_HDL CORE Pin dots, pin text do not stay on grid in symbol editor on moving/copying.1329848 CONSTRAINT_MGR CONCEPT_HDL Export Excel from DE-HDL CM displays 'Server busy' message.1330044 CONSTRAINT_MGR OTHER Need command line equivalent of cmDiffUtility to save reports as HTML1330122 SIP_LAYOUT PLACEMENT When placing IC type symbols in SiP they are being placed as Wire Bond instead of Flip Chip.1330930 CONCEPT_HDL CORE Hyperlink in attributes window not working.1336086 SIP_LAYOUT MANUFACTURING If a design has bondfingers at a certain angle/position the tool does not create a soldermask opening1338610 MODEL_INTEGRIT TRANSLATION IBIS to DML failed with incorrect error message.1338925 ALLEGRO_EDITOR MANUFACT Need a 16.5 route file option in SPB 16.6.1339672 CONCEPT_HDL CORE Editing a symbol in PDV results in error (SPCOCN-1731)1339987 ALLEGRO_EDITOR SKILL axlFormCreate embeddedForm is not working as expected1339989 PCB_LIBRARIAN LIBUTIL Con2con exits if Global section of PTF file has NC_PINS1340342 F2B DESIGNVARI DE-HDL crashes when trying to use Variant commands1340360 ALLEGRO_EDITOR EDIT_ETCH On running the AiDT command, if Total Etch Length is defined directly on an XNet, PCB Editor crashes.1340854 CONSTRAINT_MGR CONCEPT_HDL Component properties are lost during backannotation1341096 SIP_LAYOUT ASSY_RULE_CHECK ADRC rule 'Wire to Pad Optical Short' gives wrong results1341330 ALLEGRO_EDITOR DRC_CONSTR Spacing rules not followed if bond_pad is set to bond_finger1342705 ALLEGRO_EDITOR INTERFACES IDX incremental bend areas need delete processed first before adds1342910 FSP SETTINGS Unable to remove "Don't Use Banks" setting.1343076 SIG_INTEGRITY OTHER 'OrCAD PCB Professional' tier should not allow Differential Pair extraction1343239 PCB_LIBRARIAN VERIFICATION Con2con reporting errors against the wrong primitive1343257 SCM SETUP In SCM, unable to add termination to design.1343403 CONCEPT_HDL CORE Return code in Search_History prevents DE-HDL launch.1343749 CONCEPT_HDL CORE Global Navigate does not always respond1343870 ALLEGRO_EDITOR DATABASE Import Logic changes VIA net names to GND1343949 FSP IMPORT_ALLEGRO Import Instances from PCB Editor does not import FPGA model1344265 CONCEPT_HDL CORE DE-HDL crashes on viewing page search1344413 SIP_LAYOUT DIE_GENERATOR When composing a die From Geometry the die pads are shifting.1344745 ALLEGRO_EDITOR EXTRACT Need information about the changes in the format of the report generated using axlExtractToFile()1346277 SIP_LAYOUT DIE_ABSTRACT_IF Shape cannot be read when sip_symed_codesign is set.1346318 CONSTRAINT_MGR OTHER cmDiffUtility shows "unrelease_unrelease.." message and stops1346621 ASI_PI GUI Sigrity tools shown in PI Base Analyze menu regardless of option selected1347103 ALLEGRO_EDITOR INTERFACES Step mapping - 3D view for mechanical symbol % `! j+ G/ E6 v1 p. d
/1 
发表于 2014-12-13 15:14
QQ好友和群
QQ空间
腾讯微博
腾讯朋友
微信
收藏
支持！
反对！