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本帖最后由 Csec 于 2014-4-28 11:04 编辑
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1 v1 S1 h# k4 Lhttp://sw.cadence.com/P/download ... e4d05&file=.exe- w/ c/ ^- l+ n# K% A1 Y9 @' n- \
更新百度网盘下载链接！# B- b3 p2 L# w- K
http://pan.baidu.com/s/1mgwSsPy' l( w; e+ p' Z) N. c) e
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DATE: 04-25-2014 HOTFIX VERSION: 027% k! X) U+ e+ C( @% l4 }
===================================================================================================================================4 y7 Y0 u2 ?% ]5 c
CCRID PRODUCT PRODUCTLEVEL2 TITLE
' i. @+ F2 h& K===================================================================================================================================. X9 S* |/ ?5 v) I0 T3 r! R
308701 CONSTRAINT_MGR OTHER Needs to delete user defined schedule in CM: q% C+ e, j7 a
481674 ALLEGRO_EDITOR PADS_IN No board file saved from PADS_in1 A' F4 P3 E+ g* T4 o; e4 l Z0 z
982929 ALLEGRO_EDITOR EDIT_ETCH can't route on NC pin and other that are not pin.6 ~& c' G; |4 V
1012783 FSP OTHER Need Undo Command in FSP
( \& I, {& h* w- h; B, @1017381 ALLEGRO_EDITOR DRC_CONSTR Need Dynamic Phase to be able to measure back to the Drive Pins.# e" B2 {/ M. y
1072673 PCB_LIBRARIAN GRAPHICAL_EDITOR Copy paste goes offgrid if mouse is moved" X- L4 O: q7 i3 X! z
1073231 CONCEPT_HDL CORE Copy-paste of signal names goes off-grid in Windows mode.
* {; O- B$ g9 |* H8 |1105371 CONCEPT_HDL INTERFACE_DESIGN Strange behavior when shorting two Net groups: t8 T" t% g! W$ t
1116498 CIS LINK_DATABASE_PA link database with modified part results in Capture crash+ W0 A/ T% p( V# a
1118632 ALLEGRO_EDITOR GRAPHICS Text display refresh issue while in Edit > text command' a* o! W1 j4 i( ~+ ?
1155821 SIG_INTEGRITY LIBRARY Xnet are not recalculated correctly when model is changed on the Series switch part defined as discrete with Espice mode
) q( g( N' ~5 { ^+ u% A! S1157372 ALLEGRO_EDITOR DRC_CONSTR Dynamic phase for Diff Pairs not reporting back to Driver pin if pin escapes present
) ^8 g! t- Y/ G( T9 l, t1171951 ALLEGRO_EDITOR CREATE_SYM Jumper has a limited of count when it add to list.
% D; r0 o7 k N/ G: b6 I# }$ N1180871 CAPTURE LIBRARY_EDITOR Copied parts don't retain pin name and pin number settings1 }+ D, w$ t0 S7 y% H& k4 ^
1185575 SIP_LAYOUT DIE_STACK_EDITOR Updating symbols causes the graphics for the Assy layer to change from Bottom to Top.
% b" L* x* b Y% y5 {7 {' d1185772 PCB_LIBRARIAN CORE VALID_PACK_TYPE warning when cell was opened in PDV
) h& _9 M; a2 t! j1192377 CAPTURE SCHEMATIC_EDITOR Pin name/number position is incorrect on schematic if it is changed for a rotated part.: J- c9 L3 `$ ]) Q% O
1202654 ALLEGRO_EDITOR GRAPHICS Zoom using mouse wheel shall maintain the center co-ordinates
- [ w: u2 Q1 n9 r1208031 ALLEGRO_EDITOR INTERACTIV Snap to Pin for via during Copy command do not snap to connect point everytime: k! s$ {* g }4 h3 V% D
1208478 PSPICE PROBE Attached project gives overflow error with marching ON.0 U' x+ A% w2 f; @% ]0 t% G- ]- ~, D4 S
1210015 CONCEPT_HDL CORE The value of $PN should be not turned on spin or rotate symbol5 p9 ^, E8 T; l# a2 N
1210425 CONCEPT_HDL CORE When moving a circuit tool reports that connectivity has changed
$ w8 u6 P+ y* }) l9 }- H1215858 ALLEGRO_EDITOR SHAPE Force update does not void cline with the shape
. G+ a% r& g6 U) Z+ @2 a W9 N" X$ X1215906 ALLEGRO_EDITOR SHAPE Dynamic shape fill smooth failed when copying to other layers. b5 w0 L) ~+ ?; l7 r
1216358 CONCEPT_HDL CORE Can we improve our export BOM function to check if user did export physical function before exporting BOM?' s" r. b8 g" e- s: ^7 |
1217364 CONCEPT_HDL OTHER Netlist reports fail because error: GScald failed.
" n& T% k1 C7 |( b0 H* m1217529 CONCEPT_HDL CORE ADW checks do not catch single quotes in PTF values5 ?9 O' R* I+ i# g8 W
1217556 F2B PACKAGERXL signal name change not sent to Allegro after packaging
. Q" y( H5 X& ^# a# t1219283 ALLEGRO_EDITOR DRC_CONSTR Show constraint is inconsistent when displaying region information
# r# L2 i) v: F1 h) \1220078 F2B PACKAGERXL Export Physical crashes when ALL the part pins are added
" i$ l7 T) o& @! A% a1220393 CONSTRAINT_MGR CONCEPT_HDL HDL import physical from board file will annotate CM data back to HDL which includes cross-section thickness.
6 L+ J8 F2 z0 p. h1220540 ALLEGRO_EDITOR GRAPHICS Need an option to see the pads inside the internal plane shapes/ S m. p* E. X; @7 P. e& j+ l4 t
1220936 CONCEPT_HDL CORE About crash by vpadd/vpdelete command on Linux, I( O+ ?7 G8 L- Y$ A' Z7 N9 z5 D2 s
1221059 ALLEGRO_EDITOR DRC_CONSTR Get a "Shape to Thru Via Spacing" DRC error only the first time when the shape is manually voided.
$ _+ n) k: \- }8 C3 Z1221182 ADW TDA Team Design with SAMBA2 A$ E8 u3 m/ H2 l9 K j
1222442 CONSTRAINT_MGR UI_FORMS Duplicate pin pairs appear in DiffPair/ Y- O5 _, c' r. |
1223175 CONCEPT_HDL CONSTRAINT_MGR Schematic crashes when opened4 @% n( R2 Z/ m/ b4 R5 S
1223533 ALLEGRO_EDITOR GRAPHICS Why the through pins for STEP models are shown at an offset when viewed in 3D inside Package Symbol?
3 y- Z4 n1 P# s& ~) l3 F1223680 CONSTRAINT_MGR ECS_APPLY Improve ECSet mapping by allowing user to address ambiguity of Parts% `# p$ M7 R/ z- ~- g( d
1224156 SIG_INTEGRITY SIGWAVE Exporting spreadsheet with filter Subitems in SigWave exports all waveforms
+ E+ a( _! U9 I& C# r1224417 ALLEGRO_EDITOR PLOTTING Hidden font pattern is not showing correct in 16.5 version also 16.6 version.
% O& \* o2 ~6 e- y. d% o/ O% N5 j+ W1224704 F2B DESIGNVARI There is no lock for the variant.dat file - multiple users can open the editor: K. M' y7 m: |- ]) x# Y' [
1224968 ALLEGRO_EDITOR INTERACTIV Delete >(RMB click) Cut> Snap Pick to>off grid loction does not work for lines.2 a n5 A: v1 D- d# ?
1224982 CONCEPT_HDL PDF commandline publishpdf does not work when there are spaces in the path, i ? d7 ^! V
1225114 CAPTURE GENERAL H-pins added after netgroup pin get color as of netgroup pin- m; ]& s8 W; B
1225494 CAPTURE DRC Different DRC results for Entire design and selection, A" u$ d" g" b( p/ ]
1226153 ALLEGRO_EDITOR INTERFACES Export STEP should include PART_NUMBER property" h3 w; Q9 W: e. }& C8 e+ G/ H
1226235 ALLEGRO_EDITOR EDIT_ETCH Enhancement to include Pin_delay of descrete forming Xnet
, e$ h7 i2 O7 ]4 z' E* P1226372 CAPTURE GENERATE_PART ENH: Functionality to add pin spacing in New Part From Spreadsheet
4 @9 J @9 B% y1226477 CONCEPT_HDL CORE DE HDL縮 `Allowed Global Shorts? function is inconvenient for Global Signal
2 _) F# @2 Y& Y6 g1226813 SIP_LAYOUT LEFDEF_IF ERROR SPMHLD-120 when importing a DEF file. Request to increase the number of characters/line in a .cml file
3 u' R; k, E' y' f1227453 ALLEGRO_EDITOR SHAPE Addition of Fillet generate Pin to Shape Spacing DRC errors and DBDOCTOR errors
! r6 g$ X& k" ~" x" y+ e( d0 T1227461 ALLEGRO_EDITOR SHAPE Sliding a cline for certain net changes the thermal relief connects for pins connected to another net from 4 to 5,6,7,8" T; s- t j1 t9 B' ?
1227469 CIS DBC_CFG_WIZARD Oracle Views not visible on Step2 of CIS Configuration4 Z& }9 l8 s/ D( q# l
1227780 CAPTURE ANNOTATE Inconsistent behaviour when annotating heterogeneous part; c( Y5 q) j' e$ d
1227831 CONCEPT_HDL CORE Pin text and H-block name in upper case
3 t) l/ O4 C% E) F: a* M1227954 CONCEPT_HDL OTHER supress check for global signals when wires are unconnected to pins/ f. r4 ]7 ?7 k& D& i0 Q( O
1228190 ALLEGRO_EDITOR OTHER Unable to close the 'usage' window during license selection
* X0 C9 m" K+ Z2 h: M1228899 CONSTRAINT_MGR INTERACTIV Export/Import constraints in "overwrite" mode from same design shows different results when imported second time.1 N* c. H! l- I% T+ }# {0 y
1228934 ALLEGRO_EDITOR EDIT_ETCH The "View Active Layer" option like the Board Station should be provided for dynamic layer visibility.' @: T( P( z+ q% x r
1229316 ALLEGRO_EDITOR EDIT_ETCH When routing with Hug only enabled we were able to route through other routes(sometimes Hug).+ \' p( g2 b2 ^0 s9 T/ L
1229545 CONSTRAINT_MGR OTHER Allegro indicate bundle scheduled nets in CM$ i: J" f# ~& |1 U) x) q& a0 J
1230056 ALLEGRO_EDITOR GRAPHICS Bug: 3D View of Mechanical Symbol with the drill hole defined
+ y( O; S( f' q+ N. z0 m1230432 CONCEPT_HDL CORE No Description information in BOM+ ~0 t1 Z$ [. \+ j
1231148 F2B DESIGNVARI The variant.dat file is not updated with library PTF changes+ }2 p: ~) y0 T7 U- C( l
1231625 F2B DESIGNSYNC VDD at command line needs to support sch2sch and test variable to write out report files
$ ~0 h$ F' a/ o' d! K* e1231697 CONCEPT_HDL CORE If any locked files exist force a pop-up dialog restricting certain commands0 [. x8 }! T$ C
1231767 CONCEPT_HDL OTHER Unable to find under the search options single bit vector nets: Y3 i; \9 c- w5 ~8 ~! p
1231961 ALLEGRO_EDITOR SHAPE Shapes not updating to smooth unless we use force update and as a result false DRC's appear in board.! ?7 h8 |$ h7 K4 n
1232100 CONCEPT_HDL SKILL Unable to execute the SKILL commands in viewer mode1 y) E+ {1 I Y3 w& d9 F* P
1232336 CONSTRAINT_MGR CONCEPT_HDL cmFeedback takes 5hrs to complete during Import Physical
) B* t4 d3 V* G: N. N1 k: [1232710 F2B DESIGNVARI Dehdl crash while moving component in variant viewer mode
P, J1 p5 P R) t1233894 F2B PACKAGERXL The page data is missing in the pst* and PCB files* B% q' s/ V1 h* _6 e! q+ O5 z
1235785 CONCEPT_HDL CREFER cref_from_list custom text is not subsitituted in complex hierarchy- y1 F. S5 X `! E& W, M1 e/ G6 q
1235928 CAPTURE SCHEMATIC_EDITOR OleObject modifications not saved
) H* [% i% f/ @/ Z! N5 a1236065 CAPTURE PART_EDITOR Mirrored part after being edited get pin name locations incorrect6 z. [" ?* N5 o! p' C
1236071 ALLEGRO_EDITOR SHAPE Airgap for Octagonal Pads ignores DRC Value when Thermal set
L9 f' ?8 O: O A1236072 CONCEPT_HDL CORE Page 122 cannot be saved as logical page 119 has different page mapping in connectivity data and schematic
^- A0 ^% ?+ e5 N* D: P1236161 CONCEPT_HDL CORE Import Design shows the current project pages
) y0 w. e% L; {. R" ?1236432 ALLEGRO_EDITOR PADS_IN pads_in doesnot translate via and shape in some instances.2 C* Y1 c. `0 V9 m
1236557 CONCEPT_HDL PDF Running Publish PDF on command line in linux doesn't output progress until completion
+ F- @2 W: O/ T& [4 C1236589 CONCEPT_HDL PDF Enhancement license failure error should appear in pdfpuplisher log file2 V1 g/ h, B) U) V0 v6 m
1236644 ALLEGRO_EDITOR EDIT_ETCH create fanout deletes shape; E& W' i5 |( G& S0 @# |6 A
1236689 ALLEGRO_EDITOR GRAPHICS Graphics displays extraneous lines when panning or zooming# t& U1 T. S6 L: L) E6 B
1236781 F2B PACKAGERXL Export Physical produces empty files2 {7 c0 W" s& I" I; [
1237331 PSPICE ENVIRONMENT pspice.exe <cir file name> - hangs when run
, T+ O! X& `6 M5 `% m& X: h) E1237400 CIS EXPLORER Capture hangs on 2 consecutive runs of `refresh symbol from lib? command& G* Z2 h0 b' U! x6 Y- H
1237437 CONCEPT_HDL CONSTRAINT_MGR CM Crash when saving after restore from definition
( X, Q% p* C4 z) l1237862 CONSTRAINT_MGR OTHER A way to remove the RAVEL markers from the Constraint Manager.
/ @$ s: X/ ?3 x1238852 CAPTURE GENERAL signal list not updated for buses& C+ o" |) h* T$ v: t
1238856 FSP DE-HDL_SCHEMATIC FSP schematic generation crashes) s6 O6 w3 Q4 H* Y$ S3 D8 i$ {1 J
1239079 ALLEGRO_EDITOR INTERACTIV The 16.6 Padstack > Replace function leaves old padstack.. g. p" `) d1 @8 v& L3 W
1239706 CONSTRAINT_MGR ANALYSIS The reflection result on a differential signal in the CM when Measurement location is DIE
8 c1 P! z7 b; K# B1239763 PSPICE PROBE Cannot modify text label if right y axis is active# _$ P/ R1 P( N A
1240276 ALLEGRO_EDITOR GRAPHICS Printing to PDF from SigXp is giving unreadable images
5 D3 g5 e( \- u5 P1240356 CAPTURE IMPORT/EXPORT Can縯 import SDT schematic to Capture.
1 C' S) q1 l/ I1240502 F2B PACKAGERXL Corrupt cfg_package does not stop PackagerXL from completing
* v8 l* w4 u3 ^- [1240607 ALLEGRO_EDITOR OTHER Footprint of screw hole got shift in DXF file
7 u" V* u8 L2 j! y+ @1240670 ALLEGRO_EDITOR PLACEMENT Select multiple parts and Rotate makes them immovable
$ r' A% u1 g; f1240773 CAPTURE DRC DRC check reports error for duplicate NetGroup Reference in complex hierarchy/ Z! B; e/ V9 T) B
1240845 SIG_EXPLORER EXTRACTTOP Narrowband via models for Mirrored BB Vias not extracted in in the interconn.iml and this gives bad ringing in waveforms
0 R- }6 l! f Q9 F1241634 ALLEGRO_EDITOR OTHER Netshort for pad-pad connect not working& v' U' h# W- k& M5 I; y
1241776 CONCEPT_HDL CORE In hierarchal design not all pages are getting printed.
) n- \% h" ]* a# O/ S5 l# w( V; R1241788 CONSTRAINT_MGR CONCEPT_HDL Issues with changing focus in Constraint manager using keys on keyboard
. n6 I9 c3 l: s! L% B3 J" }! p2 \1242683 ALLEGRO_EDITOR INTERACTIV Color View Save replaces file without warning
( d }* g( w& z1 i* b. ]1242818 ALLEGRO_EDITOR PLACEMENT Placement edit mirror option places component on wrong side, a3 g- t, I9 B
1242847 ALLEGRO_EDITOR GRAPHICS Need an option to suppress Via Holes in 3D Viewer6 E0 w- I) a+ i, ^$ ?6 \+ q7 J: [
1242923 ADW COMPONENT_BROWSE UCB reports Missing From DB only after selecting the Row in the search results* D7 M5 q9 \" E) u5 e) o( W
1243609 CONCEPT_HDL CORE autoprop for occurrence properties" M$ G* g7 n0 b! G6 H# `, O% c
1243682 F2B DESIGNVARI after undocking variant icon cannot be redocked back to GUI
- P8 @3 l% o/ g- f4 M4 R1243686 ALLEGRO_EDITOR GRAPHICS Invoking Edit->Text, the infinite cursor disappears until edit mode is changed.. n' E! ?0 _2 V4 B9 {
1243715 CAPTURE PART_EDITOR Pin name positioning get changed after rotating or mirroring
' _8 b: ^3 c8 ^6 N1244945 CONCEPT_HDL PDF PDF Publisher does not include image when file is not located in the root folder4 _8 C' ~8 Y4 V+ S$ y8 z; R( V" ?
1245568 CONCEPT_HDL CORE Dual unselect needed for wires attached to other net/source and property is not deselected when component is
" ]1 q& h; M: A1 i9 d1245819 F2B PACKAGERXL wrong injected properties information passed during packaging of the design
, |# W# z2 ?8 @! |4 Z3 u: J1245916 SCM CONCEPT_IMPORT Where does the folder location reside for DEHDL imported blocks?: ^( O4 ~9 I2 Y5 j
1246347 CONSTRAINT_MGR CONCEPT_HDL DEHDL crash if environment variable path has trailing backslash character+ z7 M% J3 T+ ^/ N
1246896 ALLEGRO_EDITOR DFA DFA_UPDATE on Linux reports err message if the path has Upper case characters! P! {+ D) e" v/ l4 n! M
1247019 SIP_LAYOUT DIE_STACK_EDITOR SiP Layout - refresh/update symbols is mirroring the assembly drawing data on DIE that is placed ChipDown
$ r3 p9 D- }+ E- G+ `+ U1247037 CAPTURE LIBRARY_EDITOR Copy & Paste of library parts resets pin name and number6 _7 g1 k4 E( h6 q2 S* v# A
1247089 CONCEPT_HDL CORE Group Align or Distribute > Left/Center/Right crashes DEHDL
( g4 G$ @( ]1 C% S8 d3 [1247163 CONCEPT_HDL PDF Physical Net Names in PDF not maintained8 a7 B, c7 G* `5 \
1247462 CONCEPT_HDL CORE Text issue while moving with bounding box0 v& ~, L2 k% _0 V8 N+ V* Z- {
1247464 ALLEGRO_EDITOR UI_FORMS When using the define B/B via UI the end layer dropdown arrow is partially covered; K" R* h- ~# Z! E
1249063 CONCEPT_HDL CONSTRAINT_MGR CM and SigXP doesn縯 respect PACK_IGNORE at components2 ~: A$ S$ e8 i9 L- w. u7 e
1250270 CONCEPT_HDL CORE Part Manager Update places wrong parts4 A2 m6 N7 |7 N1 y6 f8 o' t
1251206 ALLEGRO_EDITOR ARTWORK Aperture command cannot create appropriate aperture automatically from design.
. ?! B, a: L& i, N/ }$ ?; a1251356 ALLEGRO_EDITOR INTERFACES Some STEP models are missing in 3D view of footprint, although all components have STEP model mapped in footprint
2 K* y( g6 I% L* G# g0 J1251845 ALLEGRO_EDITOR EXTRACT Crosshatch arcs do not extract correctly8 S) E; c: e# I6 m9 r# L, }
1252143 APD OTHER When using the beta "shape to cline" command the tool is removing the shape instead of converting it.+ u) c0 W2 A+ Y' N2 I
1252737 SIP_LAYOUT OTHER SiP Layout - Option to create shapes from Pins for WLP wafer level packaging technologies& g& F J$ z7 [
1253424 SCM SCHGEN Export Schematics Crashes System Architect
/ i4 _3 g/ Q1 B4 t7 m1253508 ALLEGRO_EDITOR INTERFACES Bug - Export IPC2581 exports Crosshatch shapes as filled' C; k# v# U# Y# P B
1253554 SIP_LAYOUT OTHER SiP Layout - Add Netlist Spreadsheet export to SiP layout to help with connectivity auditing4 M% k& N9 t# X- M4 H' Q, a
1254578 SPIF OTHER Specctra crash with Error -1073741819 for Auto router
: q. l" c# p' O2 W% }, o" b3 ?1254637 ALLEGRO_EDITOR DRC_TIMING_CHK adding nets to a net group causes constraint assignment error8 H# D* k& V9 o+ X( J
1254676 GRE IFP_INTERACTIVE Rake Lines disappear when Auto-Interactive Breakout is enabled.7 `% i1 W' }1 q6 l9 G7 i
1255067 SIG_INTEGRITY REPORTS Allegro hangs on Net Parasitc Report generation
' _1 X/ r C+ ?+ u0 I1255267 ALLEGRO_EDITOR SKILL axlDBGetPropDictEntry does not return a list of all objects4 d3 d5 ]4 }* l$ t7 L6 g
1255383 SIP_LAYOUT IC_IO_EDITING cant move bumps or driver in app mode1 }- [$ S) z. ~+ U" L5 K- m6 S
1255703 ALLEGRO_EDITOR SKILL axlCNSSetPhysical and axlCNSGetPhysical return nil if a constraint set name is provided
" E8 m' y& T2 t0 r1255759 ALLEGRO_EDITOR INTERFACES Change the silkscreen OUTLINE from layerFunction DOCUMENT to layerFunction BOARD_OUTLINE/ w5 u9 ~0 J* Z- {) U- T4 U
1256457 CONCEPT_HDL CONSTRAINT_MGR Extracting a XNet from CM crashes the tool e" s1 q9 u7 S9 t
1256597 GRE CORE Allegro GRE crashes while running Plan Spatial, on a particular design
& M4 {; Q% i2 u* G& G& { f+ N1256650 ASI_PI GUI PFE - Cannot generate model file error when using company decap library
. V6 `$ S h; c1 l3 V1256837 SIP_LAYOUT DIE_EDITOR Open and close of die editor takes too long
- z7 G1 T) c9 E' F0 ]1257732 CONSTRAINT_MGR OTHER Bug - Export Analysis Results in CM makes Allegro crash
- }! b5 D! C2 E t1257755 ALLEGRO_EDITOR OTHER Editing time in Display > Status seems to be logging wrong time# L# B% Y y$ u
1258029 APD WIREBOND The bondwire lost after import the wire information3 C! p) S: S! D& k3 h4 L3 `
1258979 APD NC NC Drill: There is difference of number of drills.$ T9 h0 b' _; _1 t! E
1259484 SIP_LAYOUT OTHER SiP - calc min airgap calculate minimum airgap beta feature improvement/ c: D9 e( `0 }# ?( H# B) [
1259677 CONCEPT_HDL CORE hier_write -forcereset cause component prop change.
' i7 a0 G' m/ W, f- z1259913 ALLEGRO_EDITOR UI_FORMS Unable to save setting of "use secondary step models in 3D viewer"0 f' q2 F" d" m" d$ i
1261758 ALLEGRO_EDITOR EDIT_ETCH Auto Interactive Delay tune (AiDT) is deleting clines+ Z- U1 ?) H. l% h) `
1262543 ALLEGRO_EDITOR MANUFACT merge shape results in moved void$ T; F( `" D: w6 C& Y7 M2 e) @
1264767 ALLEGRO_EDITOR DRC_TIMING_CHK XNET is choosing to resolve to a different name from 16.5 to 16.6 and is causing constraint loss
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发表于 2014-4-26 15:15
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发表于 2014-4-27 21:59
