|
|
EDA365欢迎您！
您需要 登录 才可以下载或查看，没有帐号？注册
x
本帖最后由 Csec 于 2014-4-28 11:04 编辑
6 a' X- z8 X. X
$ z7 {6 G) X/ x+ z9 D5 ^! \9 {http://sw.cadence.com/P/download ... e4d05&file=.exe8 G+ e8 W6 W# E U3 a: n
更新百度网盘下载链接！& E1 I+ Q9 L, O: }8 @( c
http://pan.baidu.com/s/1mgwSsPy
+ R! K# z( e7 O8 b" O% d3 x1 L
DATE: 04-25-2014 HOTFIX VERSION: 027
& f% A. U j- R) J8 q1 E+ m5 E/ X===================================================================================================================================
- L4 {2 X4 }" ~& k" k& |9 S+ ?CCRID PRODUCT PRODUCTLEVEL2 TITLE
( S6 D9 A: n% u=================================================================================================================================== B" I! q$ ]9 f7 @6 K4 v
308701 CONSTRAINT_MGR OTHER Needs to delete user defined schedule in CM
" a- `6 Q, N4 s$ S9 A8 {( I481674 ALLEGRO_EDITOR PADS_IN No board file saved from PADS_in
- ?# Y. F, M n. z; T982929 ALLEGRO_EDITOR EDIT_ETCH can't route on NC pin and other that are not pin.) O' R: d7 v; ~+ A8 k* x
1012783 FSP OTHER Need Undo Command in FSP5 ^; @6 a0 f/ M+ E- H; `8 _
1017381 ALLEGRO_EDITOR DRC_CONSTR Need Dynamic Phase to be able to measure back to the Drive Pins./ y! [% S/ l& \3 ?0 |
1072673 PCB_LIBRARIAN GRAPHICAL_EDITOR Copy paste goes offgrid if mouse is moved
" l+ d7 s) q6 m8 @1073231 CONCEPT_HDL CORE Copy-paste of signal names goes off-grid in Windows mode.
; h3 D+ E* {& h* T. T, `1105371 CONCEPT_HDL INTERFACE_DESIGN Strange behavior when shorting two Net groups
( n% O1 J$ u! }' B7 W7 I" U9 ]1116498 CIS LINK_DATABASE_PA link database with modified part results in Capture crash5 {2 O% I" U0 v
1118632 ALLEGRO_EDITOR GRAPHICS Text display refresh issue while in Edit > text command
" V3 \& P+ Y; i% }1155821 SIG_INTEGRITY LIBRARY Xnet are not recalculated correctly when model is changed on the Series switch part defined as discrete with Espice mode0 r- S R5 _( f0 S, }2 d, e4 Q
1157372 ALLEGRO_EDITOR DRC_CONSTR Dynamic phase for Diff Pairs not reporting back to Driver pin if pin escapes present
0 b- h) \$ s5 w9 w1171951 ALLEGRO_EDITOR CREATE_SYM Jumper has a limited of count when it add to list.
; R4 `7 I# O* Z7 _: t1180871 CAPTURE LIBRARY_EDITOR Copied parts don't retain pin name and pin number settings
- c2 K: z0 L' F( |1185575 SIP_LAYOUT DIE_STACK_EDITOR Updating symbols causes the graphics for the Assy layer to change from Bottom to Top.9 i* _- B8 e, `$ F
1185772 PCB_LIBRARIAN CORE VALID_PACK_TYPE warning when cell was opened in PDV
1 l8 O! M( t& X) S; k1192377 CAPTURE SCHEMATIC_EDITOR Pin name/number position is incorrect on schematic if it is changed for a rotated part.
1 g# o! M, n$ T1202654 ALLEGRO_EDITOR GRAPHICS Zoom using mouse wheel shall maintain the center co-ordinates
4 b1 b5 } ^0 ]: _6 X1208031 ALLEGRO_EDITOR INTERACTIV Snap to Pin for via during Copy command do not snap to connect point everytime
$ L2 e ^- k' B1 }- q2 Z- f. P5 r1208478 PSPICE PROBE Attached project gives overflow error with marching ON. u0 x9 G1 k5 p
1210015 CONCEPT_HDL CORE The value of $PN should be not turned on spin or rotate symbol
A4 ^* R l6 J1210425 CONCEPT_HDL CORE When moving a circuit tool reports that connectivity has changed
, ]; {0 a5 f+ \5 E# q1215858 ALLEGRO_EDITOR SHAPE Force update does not void cline with the shape8 W$ p$ R5 ?. ]0 g+ D! o
1215906 ALLEGRO_EDITOR SHAPE Dynamic shape fill smooth failed when copying to other layers
+ n+ S7 _+ h x7 O+ S# o% u0 \1216358 CONCEPT_HDL CORE Can we improve our export BOM function to check if user did export physical function before exporting BOM?
* Z7 _8 g4 ^! P4 H1217364 CONCEPT_HDL OTHER Netlist reports fail because error: GScald failed.+ |( d- e- k0 r, S6 V( [ J
1217529 CONCEPT_HDL CORE ADW checks do not catch single quotes in PTF values
; q. @0 j% ?% m1217556 F2B PACKAGERXL signal name change not sent to Allegro after packaging ~" `/ f( ]) a7 r2 B- }- D; `9 r
1219283 ALLEGRO_EDITOR DRC_CONSTR Show constraint is inconsistent when displaying region information
# x; L" [2 g( [" {( n* \3 R: E1220078 F2B PACKAGERXL Export Physical crashes when ALL the part pins are added
0 Z) K8 F( k9 _" ]1220393 CONSTRAINT_MGR CONCEPT_HDL HDL import physical from board file will annotate CM data back to HDL which includes cross-section thickness.' B6 f; ^) m7 E. X
1220540 ALLEGRO_EDITOR GRAPHICS Need an option to see the pads inside the internal plane shapes
- k* c' g/ A4 [" X0 e1220936 CONCEPT_HDL CORE About crash by vpadd/vpdelete command on Linux# T( u0 K$ o% _ P
1221059 ALLEGRO_EDITOR DRC_CONSTR Get a "Shape to Thru Via Spacing" DRC error only the first time when the shape is manually voided.4 {# k- ^ }9 h+ y
1221182 ADW TDA Team Design with SAMBA
& Y* A4 D7 S/ R2 N1222442 CONSTRAINT_MGR UI_FORMS Duplicate pin pairs appear in DiffPair0 G; {* _' b4 W7 G* y
1223175 CONCEPT_HDL CONSTRAINT_MGR Schematic crashes when opened
+ e# \; e; L, U [% }) b1223533 ALLEGRO_EDITOR GRAPHICS Why the through pins for STEP models are shown at an offset when viewed in 3D inside Package Symbol?: [7 L) h* }+ Y: y4 M
1223680 CONSTRAINT_MGR ECS_APPLY Improve ECSet mapping by allowing user to address ambiguity of Parts
# u8 P% X. R6 M1224156 SIG_INTEGRITY SIGWAVE Exporting spreadsheet with filter Subitems in SigWave exports all waveforms
# y" e4 S' V( c/ D5 v4 Z$ v* b; `1224417 ALLEGRO_EDITOR PLOTTING Hidden font pattern is not showing correct in 16.5 version also 16.6 version.
, [0 T; Z0 p3 F% v2 I1224704 F2B DESIGNVARI There is no lock for the variant.dat file - multiple users can open the editor
4 {" f# G6 Q) u" o! u1224968 ALLEGRO_EDITOR INTERACTIV Delete >(RMB click) Cut> Snap Pick to>off grid loction does not work for lines.2 U0 v3 u v! {
1224982 CONCEPT_HDL PDF commandline publishpdf does not work when there are spaces in the path2 p0 U3 y5 D7 ^3 N2 g! E( H* l% s
1225114 CAPTURE GENERAL H-pins added after netgroup pin get color as of netgroup pin
: a3 l' H, y/ L3 A6 J \* Z* k' ~1225494 CAPTURE DRC Different DRC results for Entire design and selection$ j- e, w9 V0 u
1226153 ALLEGRO_EDITOR INTERFACES Export STEP should include PART_NUMBER property
9 ^/ K ?* L; K9 ^1226235 ALLEGRO_EDITOR EDIT_ETCH Enhancement to include Pin_delay of descrete forming Xnet. _* Q% o- \0 U( }2 \3 D# g
1226372 CAPTURE GENERATE_PART ENH: Functionality to add pin spacing in New Part From Spreadsheet2 W( ~" O& l& t9 f, u, A& p7 f
1226477 CONCEPT_HDL CORE DE HDL縮 `Allowed Global Shorts? function is inconvenient for Global Signal8 ?+ I/ h ^! p6 l9 b' O* O( H
1226813 SIP_LAYOUT LEFDEF_IF ERROR SPMHLD-120 when importing a DEF file. Request to increase the number of characters/line in a .cml file
5 |' j% k! j; {8 F: U1227453 ALLEGRO_EDITOR SHAPE Addition of Fillet generate Pin to Shape Spacing DRC errors and DBDOCTOR errors
; Z. B1 _. I) k& i4 F0 r5 ^4 g1227461 ALLEGRO_EDITOR SHAPE Sliding a cline for certain net changes the thermal relief connects for pins connected to another net from 4 to 5,6,7,8, v$ J' h0 ~/ C& J! r' p
1227469 CIS DBC_CFG_WIZARD Oracle Views not visible on Step2 of CIS Configuration& c. ]* s5 k2 U4 H8 ]2 y- N, k* r
1227780 CAPTURE ANNOTATE Inconsistent behaviour when annotating heterogeneous part
6 I# f7 K& W. r( X1227831 CONCEPT_HDL CORE Pin text and H-block name in upper case
% H7 O- s. k+ J6 z% f" b( m1227954 CONCEPT_HDL OTHER supress check for global signals when wires are unconnected to pins% a5 H( }5 i$ `* F8 U, Q
1228190 ALLEGRO_EDITOR OTHER Unable to close the 'usage' window during license selection
7 N, N2 `' s) f) o) I( @+ k7 e1228899 CONSTRAINT_MGR INTERACTIV Export/Import constraints in "overwrite" mode from same design shows different results when imported second time.
3 p, u/ `( Z$ _" ]9 D1228934 ALLEGRO_EDITOR EDIT_ETCH The "View Active Layer" option like the Board Station should be provided for dynamic layer visibility.! p' }- M3 f. |3 q: S
1229316 ALLEGRO_EDITOR EDIT_ETCH When routing with Hug only enabled we were able to route through other routes(sometimes Hug).
8 Q7 Q$ ]9 }; w8 _& N4 o. _- ~1229545 CONSTRAINT_MGR OTHER Allegro indicate bundle scheduled nets in CM4 H! f+ u* V, ?+ y7 J* {7 E; x
1230056 ALLEGRO_EDITOR GRAPHICS Bug: 3D View of Mechanical Symbol with the drill hole defined
3 d* @* E) o3 F3 |/ V3 X3 _3 d6 l3 b1230432 CONCEPT_HDL CORE No Description information in BOM# w; f9 Y1 t( n; Z4 _# k W+ o
1231148 F2B DESIGNVARI The variant.dat file is not updated with library PTF changes# b8 S/ r) t2 s
1231625 F2B DESIGNSYNC VDD at command line needs to support sch2sch and test variable to write out report files( W8 ^4 z" E6 n. D
1231697 CONCEPT_HDL CORE If any locked files exist force a pop-up dialog restricting certain commands
& e3 V! K! [$ o2 p. d4 y1231767 CONCEPT_HDL OTHER Unable to find under the search options single bit vector nets2 J2 z+ L; ?) {, Y$ K
1231961 ALLEGRO_EDITOR SHAPE Shapes not updating to smooth unless we use force update and as a result false DRC's appear in board.
1 W6 b" ~) D( M9 B0 w7 @, f4 H1232100 CONCEPT_HDL SKILL Unable to execute the SKILL commands in viewer mode+ V- i/ k8 t' C/ C8 ^9 A0 z
1232336 CONSTRAINT_MGR CONCEPT_HDL cmFeedback takes 5hrs to complete during Import Physical5 X0 W; i# ]) D& g! `0 f
1232710 F2B DESIGNVARI Dehdl crash while moving component in variant viewer mode
: W' B5 g. @2 z3 b, @1233894 F2B PACKAGERXL The page data is missing in the pst* and PCB files6 W m& W4 K1 E+ P! H
1235785 CONCEPT_HDL CREFER cref_from_list custom text is not subsitituted in complex hierarchy
$ t2 ]( L1 g# u. p" T; @0 L+ `1235928 CAPTURE SCHEMATIC_EDITOR OleObject modifications not saved* Z1 {" z8 S O6 m, F
1236065 CAPTURE PART_EDITOR Mirrored part after being edited get pin name locations incorrect# {! X6 {9 `% B
1236071 ALLEGRO_EDITOR SHAPE Airgap for Octagonal Pads ignores DRC Value when Thermal set
6 E/ j' a8 I9 t; {, f' o1 U1236072 CONCEPT_HDL CORE Page 122 cannot be saved as logical page 119 has different page mapping in connectivity data and schematic
0 s" Q- ?# U* u7 h( s/ F1236161 CONCEPT_HDL CORE Import Design shows the current project pages
4 n0 P& e7 T# X0 s6 G1236432 ALLEGRO_EDITOR PADS_IN pads_in doesnot translate via and shape in some instances.; ~" \0 A* ~4 H
1236557 CONCEPT_HDL PDF Running Publish PDF on command line in linux doesn't output progress until completion3 Y6 N `: L( {1 ^% M1 w" d
1236589 CONCEPT_HDL PDF Enhancement license failure error should appear in pdfpuplisher log file6 E S6 m9 g4 Q- a
1236644 ALLEGRO_EDITOR EDIT_ETCH create fanout deletes shape
6 f- T& S! r" k6 _# E3 X9 N4 t% x1236689 ALLEGRO_EDITOR GRAPHICS Graphics displays extraneous lines when panning or zooming5 f# X5 B5 v" ?$ ] n s
1236781 F2B PACKAGERXL Export Physical produces empty files
9 M3 x9 z( j2 [4 j9 M6 r1237331 PSPICE ENVIRONMENT pspice.exe <cir file name> - hangs when run% D% D/ e! {% Z" t n- x3 t# {
1237400 CIS EXPLORER Capture hangs on 2 consecutive runs of `refresh symbol from lib? command$ W% c+ G: v/ f; T
1237437 CONCEPT_HDL CONSTRAINT_MGR CM Crash when saving after restore from definition
5 }/ k6 i8 x- _! w$ a1237862 CONSTRAINT_MGR OTHER A way to remove the RAVEL markers from the Constraint Manager.
4 {: S4 L2 l, a* w) P8 {1238852 CAPTURE GENERAL signal list not updated for buses* Q* X0 A& {3 ~0 Y' Z4 _
1238856 FSP DE-HDL_SCHEMATIC FSP schematic generation crashes, n9 n: C& N9 \, v
1239079 ALLEGRO_EDITOR INTERACTIV The 16.6 Padstack > Replace function leaves old padstack.
1 S" q- U+ U2 @ ~3 ?% `, P1239706 CONSTRAINT_MGR ANALYSIS The reflection result on a differential signal in the CM when Measurement location is DIE3 K2 R/ N, a( X$ f9 n, b- `
1239763 PSPICE PROBE Cannot modify text label if right y axis is active$ o+ ~1 D+ `1 y6 s* Q0 \0 Q
1240276 ALLEGRO_EDITOR GRAPHICS Printing to PDF from SigXp is giving unreadable images
/ g, N5 D# s1 j# |" {) o* y1240356 CAPTURE IMPORT/EXPORT Can縯 import SDT schematic to Capture./ T' K& l8 q- {$ d
1240502 F2B PACKAGERXL Corrupt cfg_package does not stop PackagerXL from completing' V4 b- x/ n. ]
1240607 ALLEGRO_EDITOR OTHER Footprint of screw hole got shift in DXF file
( n+ O$ l" d) B7 T6 ]1240670 ALLEGRO_EDITOR PLACEMENT Select multiple parts and Rotate makes them immovable
; ^$ }3 c4 E0 E+ X: h8 P1240773 CAPTURE DRC DRC check reports error for duplicate NetGroup Reference in complex hierarchy; t! f- b- Y2 A3 B' |+ {! w% p
1240845 SIG_EXPLORER EXTRACTTOP Narrowband via models for Mirrored BB Vias not extracted in in the interconn.iml and this gives bad ringing in waveforms
. K2 z$ x4 U4 E7 |& J) s1241634 ALLEGRO_EDITOR OTHER Netshort for pad-pad connect not working
9 `' P- Z8 u4 J7 o1 S) a- o1241776 CONCEPT_HDL CORE In hierarchal design not all pages are getting printed.
3 Y) Q3 H$ @+ n1241788 CONSTRAINT_MGR CONCEPT_HDL Issues with changing focus in Constraint manager using keys on keyboard5 f% F0 l4 a" J0 I% K x
1242683 ALLEGRO_EDITOR INTERACTIV Color View Save replaces file without warning
# M6 N4 d/ K- B2 h1 h3 A) h# X1242818 ALLEGRO_EDITOR PLACEMENT Placement edit mirror option places component on wrong side
+ r1 e+ \2 m+ P' h& M1242847 ALLEGRO_EDITOR GRAPHICS Need an option to suppress Via Holes in 3D Viewer- D5 B9 g" G, y$ e
1242923 ADW COMPONENT_BROWSE UCB reports Missing From DB only after selecting the Row in the search results. U: f4 |/ W0 e6 U$ c, f1 \
1243609 CONCEPT_HDL CORE autoprop for occurrence properties
! u) d% N% C4 I/ B$ ]: A1243682 F2B DESIGNVARI after undocking variant icon cannot be redocked back to GUI* A2 P( r' i4 b' f1 l
1243686 ALLEGRO_EDITOR GRAPHICS Invoking Edit->Text, the infinite cursor disappears until edit mode is changed.
7 @5 C, ]0 d( x' C0 U; ~$ V/ @1243715 CAPTURE PART_EDITOR Pin name positioning get changed after rotating or mirroring
0 {/ M4 |' M, g: A1244945 CONCEPT_HDL PDF PDF Publisher does not include image when file is not located in the root folder) e5 S R" V- `2 ]
1245568 CONCEPT_HDL CORE Dual unselect needed for wires attached to other net/source and property is not deselected when component is9 Q1 w& E& ?# ?5 l/ o; N8 a
1245819 F2B PACKAGERXL wrong injected properties information passed during packaging of the design: U# S# _. ?+ j4 ~2 `: T" `" C
1245916 SCM CONCEPT_IMPORT Where does the folder location reside for DEHDL imported blocks?' e! \5 ^! d) a0 u( `
1246347 CONSTRAINT_MGR CONCEPT_HDL DEHDL crash if environment variable path has trailing backslash character: p0 l! W8 d/ g
1246896 ALLEGRO_EDITOR DFA DFA_UPDATE on Linux reports err message if the path has Upper case characters
( S |; [' W/ _+ Q1247019 SIP_LAYOUT DIE_STACK_EDITOR SiP Layout - refresh/update symbols is mirroring the assembly drawing data on DIE that is placed ChipDown
: X e, t# h9 t1247037 CAPTURE LIBRARY_EDITOR Copy & Paste of library parts resets pin name and number
4 s5 f" F2 ^# f% B1 t1247089 CONCEPT_HDL CORE Group Align or Distribute > Left/Center/Right crashes DEHDL
; z: p1 t9 K/ `8 v) T/ }7 v8 c& }1247163 CONCEPT_HDL PDF Physical Net Names in PDF not maintained# a; P7 w1 X9 l
1247462 CONCEPT_HDL CORE Text issue while moving with bounding box
$ j, d2 d6 A1 Y1247464 ALLEGRO_EDITOR UI_FORMS When using the define B/B via UI the end layer dropdown arrow is partially covered- ?7 H4 j& A' m* c; W
1249063 CONCEPT_HDL CONSTRAINT_MGR CM and SigXP doesn縯 respect PACK_IGNORE at components
4 M, L# S R _8 W) Y* w1250270 CONCEPT_HDL CORE Part Manager Update places wrong parts
1 s9 G4 m' T) O7 Z1251206 ALLEGRO_EDITOR ARTWORK Aperture command cannot create appropriate aperture automatically from design.+ |1 W" {& Z5 y
1251356 ALLEGRO_EDITOR INTERFACES Some STEP models are missing in 3D view of footprint, although all components have STEP model mapped in footprint- I( v8 D3 P, Y0 h' V
1251845 ALLEGRO_EDITOR EXTRACT Crosshatch arcs do not extract correctly
9 ~) J; X2 ^) }: f1252143 APD OTHER When using the beta "shape to cline" command the tool is removing the shape instead of converting it.0 t5 u) I5 Q5 `
1252737 SIP_LAYOUT OTHER SiP Layout - Option to create shapes from Pins for WLP wafer level packaging technologies \" O! ]: }7 L7 g
1253424 SCM SCHGEN Export Schematics Crashes System Architect
- q- x, Z6 j% G2 B0 T6 g6 X* y1253508 ALLEGRO_EDITOR INTERFACES Bug - Export IPC2581 exports Crosshatch shapes as filled
2 Z7 k3 z _& g1253554 SIP_LAYOUT OTHER SiP Layout - Add Netlist Spreadsheet export to SiP layout to help with connectivity auditing* Y- l) @, B+ q, \' T
1254578 SPIF OTHER Specctra crash with Error -1073741819 for Auto router1 G. u5 V$ E. V( g! V7 i
1254637 ALLEGRO_EDITOR DRC_TIMING_CHK adding nets to a net group causes constraint assignment error1 l- u: I% a8 E: m* X
1254676 GRE IFP_INTERACTIVE Rake Lines disappear when Auto-Interactive Breakout is enabled.
9 G3 W+ r" M- F1255067 SIG_INTEGRITY REPORTS Allegro hangs on Net Parasitc Report generation) n. D z7 o7 { Y# |: Z" F
1255267 ALLEGRO_EDITOR SKILL axlDBGetPropDictEntry does not return a list of all objects! K% }! D" t0 U5 k3 W
1255383 SIP_LAYOUT IC_IO_EDITING cant move bumps or driver in app mode
, t$ H& k1 t( k G; G* ?) w- K1255703 ALLEGRO_EDITOR SKILL axlCNSSetPhysical and axlCNSGetPhysical return nil if a constraint set name is provided5 l i* k Z& b1 n& ]
1255759 ALLEGRO_EDITOR INTERFACES Change the silkscreen OUTLINE from layerFunction DOCUMENT to layerFunction BOARD_OUTLINE( K% K' N5 T6 V- J R0 L
1256457 CONCEPT_HDL CONSTRAINT_MGR Extracting a XNet from CM crashes the tool3 o$ w/ G% M* Z9 I* O
1256597 GRE CORE Allegro GRE crashes while running Plan Spatial, on a particular design
% R4 D) x# r" n" g1256650 ASI_PI GUI PFE - Cannot generate model file error when using company decap library
+ R; j+ r- R1 `4 H1256837 SIP_LAYOUT DIE_EDITOR Open and close of die editor takes too long
6 e8 J" f2 o$ B8 _1257732 CONSTRAINT_MGR OTHER Bug - Export Analysis Results in CM makes Allegro crash# j: e* U, \* z$ ^
1257755 ALLEGRO_EDITOR OTHER Editing time in Display > Status seems to be logging wrong time, j3 U: ]. X7 `6 u0 h! v
1258029 APD WIREBOND The bondwire lost after import the wire information g' _) J4 u9 `/ _! U/ |
1258979 APD NC NC Drill: There is difference of number of drills.
+ m$ P1 s! h2 e/ I2 Y8 h1259484 SIP_LAYOUT OTHER SiP - calc min airgap calculate minimum airgap beta feature improvement; y: [! c2 S& C$ ?2 L4 _2 E
1259677 CONCEPT_HDL CORE hier_write -forcereset cause component prop change.
, R, H1 I$ M0 U! _" D1259913 ALLEGRO_EDITOR UI_FORMS Unable to save setting of "use secondary step models in 3D viewer", X" Y) G7 D5 A- ~
1261758 ALLEGRO_EDITOR EDIT_ETCH Auto Interactive Delay tune (AiDT) is deleting clines
. C( _( ?# o3 g" J1262543 ALLEGRO_EDITOR MANUFACT merge shape results in moved void! P! T @. F. V r# _
1264767 ALLEGRO_EDITOR DRC_TIMING_CHK XNET is choosing to resolve to a different name from 16.5 to 16.6 and is causing constraint loss
5 F' \( k7 u: W H9 K
( }" B: P( ?: \- G6 W |
|
/1 
发表于 2014-4-26 15:15
QQ好友和群
QQ空间
腾讯微博
腾讯朋友
微信
收藏
支持！
反对！
发表于 2014-4-27 21:59
