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|
: Q- J5 \$ i8 ^3 Q- xDATE: 12-8-2011 HOTFIX VERSION: 041# g# \/ Y! P1 m0 _5 L0 c6 N
===================================================================================================================================. d& f) i& w+ ~9 \5 m6 m
CCRID PRODUCT PRODUCTLEVEL2 TITLE6 b. w& |- c$ T8 e
===================================================================================================================================
- f5 Y3 _- S" ^) [875695 SIG_EXPLORER INTERACTIV Enforce Causality check box doesn't work.8 @; B% K" Y9 S \+ V- u; R: g
944006 ALLEGRO_EDITOR EDIT_ETCH Vias added to shapes behave differently
0 C% M& g1 t2 X946293 CONCEPT_HDL ARCHIVER Archiver hangs if there is a whitespace at the end of the path of cref.dat* [! J: m/ y6 ^7 K
951919 ALLEGRO_EDITOR OTHER Exported package symbol soldermask and pastemask padstack locations not the same as original7 u% s w, ~% y' w. W
952057 SCM PACKAGER Export Physical does not works correctly from SCM) d3 H' [4 E1 S) r: I5 l8 W, E1 Z
953018 APD REPORTS Shape affects Package Report result.
( |8 d% o5 c. A" t% u. J3 z: {. }953279 SIG_INTEGRITY LIBRARY mkdeviceindex is adding dml file listing in env file% Y. x, h4 U s. e
953827 ALLEGRO_EDITOR EDIT_ETCH Snake Breakout function crashed Allegro) U& }) y0 U0 ~0 A$ _3 i
953917 CONCEPT_HDL ARCHIVER archcore should handle errors correctly
4 J6 I. ^2 w$ W& I4 Y* K3 N' W2 o953971 ALLEGRO_EDITOR MANUFACT NC Drill files not generated correctly when using the option "“separate files for plated/nonplatedholes”" L& N5 Q5 g/ ]% r/ c; L7 q
954055 CONCEPT_HDL CREFER Crefer fails with UNC install path$ O5 Q; l) ], c* h `0 q5 Z
954858 CAPTURE LIBRARY_EDITOR Closed polyline used in pin shape is not appearing while using custom pin in part.
$ R( F+ S Z; [3 p6 o, i955029 CONCEPT_HDL CORE custom text font size not recognized in symbol view3 X' y- j7 j: [, o/ @
955133 SIG_INTEGRITY FIELD_SOLVERS The Field solver creates the differential trace model which is reversed T(D1) and T(D2) of bottom side.2 A' R! \- K8 M6 J9 O9 U
955299 ALLEGRO_EDITOR DRC_CONSTR drc text to smd pin does not work any more on this database in 16.3 S039: I& D/ m+ [ \
955338 CONCEPT_HDL CHECKPLUS Need to change PART_NAME' l% F& j# }0 x
956751 ALLEGRO_EDITOR ARTWORK Import Gerber command does not work correctly9 z. @$ h( @7 H( d+ \; Q8 ^
958252 ALLEGRO_EDITOR TESTPREP Resequence testprep with the option - Delete probes too close crashes the design) g# G) ]6 _, y. c
958945 CONCEPT_HDL CHECKPLUS Checkplus from 16.3 is not running with our "Allegro Design Entry HDL XL (16.5 licenses)
- t M# ?5 V& w3 s6 H, S" Q" f# O% N. Q. r
DATE: 10-21-2011 HOTFIX VERSION: 040# ~7 l8 I$ a1 ?
===================================================================================================================================
: ~) D) E" z0 f& u- ]4 G+ V! f5 h" x& HCCRID PRODUCT PRODUCTLEVEL2 TITLE$ M- G# ~3 R- d9 _& Y6 D$ Z2 K' [
===================================================================================================================================: E# `4 `4 q9 a) W) t! i
735439 PCB_LIBRARIAN CORE PDV Moving line-dot pinshapes by arrow keys breaks the pinshape- X( y5 W* I; q6 Y
935438 CONCEPT_HDL COPY_PROJECT Copy Project changes read-only hierarchical block permissions
) B% x* d" }/ @3 {! v935836 SCM SCHGEN ASA crashes when generating Flat Document Schematic
( s7 K) |3 x& j937165 SCM SCHGEN Can't generate Schematic
, \. L' _: w6 `941426 CONCEPT_HDL COPY_PROJECT Copy Project fails - Updating opf view This can't happen!
% y6 K* j% c0 E4 ~; M941814 CONCEPT_HDL CREFER CreferHDL crashes during ScheGen1 [6 P; y* D5 C3 ]
942522 CAPTURE GEN_BOM Export in excel check mark doesn't invoked BOM in Excel
4 P6 z, [/ T" K7 c3 s% H- v# M0 a943032 SCM OTHER ASA is not passing the correct reuse_module name to Allegro PCB layout.
" \- g& T N' A946350 F2B DESIGNVARI Variant Editor rename function removes all components" Q8 z! S8 S% K0 \
946419 SIG_INTEGRITY SIMULATION Cannot select component on BoardModel for controller in bus setup form- z9 t( d& m. q- I7 u) ^: X9 Z
947789 ALLEGRO_EDITOR MENTOR mbs2brd crashes during translation on the attached design., g$ ]9 ^/ b8 B. k: @
' C9 C2 u. O+ L K% \
DATE: 10-6-2011 HOTFIX VERSION: 039
- [- }) q! A2 F! E===================================================================================================================================, _" F. S( l% x1 |; u" j- i
CCRID PRODUCT PRODUCTLEVEL2 TITLE
" O. r5 i1 W% J& i3 L( H4 v( V% ]- v===================================================================================================================================/ M+ Q, b/ b; ~: i* E* J
841096 APD WIREBOND Function required which to check wire not in die pad center.
1 x8 m% u. K9 h& K: V o, C912942 APD WIREBOND constraint driven wire bonding
" B6 U/ i: Q$ _917887 PCB_LIBRARIAN VERIFICATION Part should not be released if the alt_symbols has errors o. m+ K/ W9 N" P1 k
923315 SIG_INTEGRITY GEOMETRY_EXTRACT crosstalk simulation fails with TMP popup failure+ Y, W1 x. ?6 N [1 j
927950 APD DATABASE My customer name their layout cross section subclass name as “wire” in Die type.( A; e& r* }2 j) G: m
929348 F2B BOM Warning 007: Invalid output file path name) |) W P8 G1 I. \, Q; \
930783 CONCEPT_HDL CORE Painting with groups with default colors
4 n$ l, k2 |; A7 z932091 CONCEPT_HDL CORE Prop attached to SIG_NAME property8 M- d. `3 a( t
932871 APD GRAPHICS could not see cursor as infinite
! h* r5 H- E- u, N: S933356 CONCEPT_HDL CORE Net prop display size become 0 if it was attached to SIG_NAME prop.
0 m6 j, y3 S* Z* t: H933532 ALLEGRO_EDITOR COLOR Bad color assign and initialisation during creation of new subclass. P L' q: p' i, c5 ~
934008 ALLEGRO_EDITOR REFRESH refresh symbol updates symbol text to some unexpected values- k# c g! [7 N( C
934533 F2B DESIGNVARI The Variant Editor errors are not written to the variants.lst file
* g' ^4 G6 K# H1 B! t+ I935911 CONCEPT_HDL CONSTRAINT_MGR Mapping of constraints fails after importing layout constraints! x( A2 _/ o; L3 L. _$ K& B
936098 ALLEGRO_EDITOR SKILL axlDBCreateCloseShape does not work correctly.
5 x; i+ c' s' Y7 P9 O; U936794 CONCEPT_HDL CORE Unable to select Allegro Design Entry HDL XL
7 W, ], ]4 {. _& M! k937087 CIS DESIGN_VARIANT Upreved design becomes very slow in Variant view mode. DELEET THE DESIGN AFTER RESOLVING THE ISSUE8 \3 Q$ D& v Q: G; k
937173 CAPTURE OTHER Wrong license information "UNLICENSED" in Capture >> Help >> About
& z1 Z. i% C0 p# B6 X2 L/ l7 B937290 APD PLATING_BAR Plating Bar checks does not recognize connection made through etchback through shape.
7 d u# [5 V* c8 s! e937411 ALLEGRO_EDITOR DATABASE downrev_library reading from one directory and writing to another hangs the command.
7 H% G5 Z" R# }5 j) \2 Z. p8 e( F938143 ALLEGRO_EDITOR CREATE_SYM Why is this Extra Property 'ECSET_MAPPING_ERROR
! f" q; d$ `/ b938281 SIP_RF OTHER export_chips creating bad data when symbol is split and contains V- V+ pins
' S+ N4 y; M6 E8 P939918 PSPICE PROBE Print > Preview for output file causes Pspice crash.4 f* T5 \( I; ^
940217 CONCEPT_HDL COMP_BROWSER UCB reports 'No Symbol found for the part'$ Q1 F1 s6 l( Q/ C- G% p6 k1 A; O
/ q C; l+ ?0 ?/ C$ s3 SDATE: 09-21-2011 HOTFIX VERSION: 038! @, O/ ~5 G: [& G- k* h
===================================================================================================================================6 W5 D% r2 D8 a' ]: _: N- b
CCRID PRODUCT PRODUCTLEVEL2 TITLE* K G" h2 R7 l' `$ |) ?
===================================================================================================================================
& s A1 A2 s. P1 ^0 j924448 F2B DESIGNVARI Design does not complete variant annotation% U! X7 r9 ?, i# f( w5 F) c
927104 F2B DESIGNVARI Tools > Annotate variants crashes when there are ASCII characters in the property values* w; I( t5 i0 E* I" W7 K' @
928738 PSPICE PROBE Y-axis grid settings for multiple plots0 Y% B; Q, |- _( o4 q$ @* [* ]( W
929284 CONCEPT_HDL ARCHIVER archive does not create a zip file8 f, m1 d4 X/ _, D! s. _. Z. m
930063 ALLEGRO_EDITOR TESTPREP Test prep crash Allego when it can not create pin escape1 @6 {" m2 k4 @1 m
930180 CIS LINK_DATABASE_PA Visible property position on schematic get reset on "link database part" operation e, Q9 x7 ~4 s. l% }/ R% T6 f- m- h; f
930355 SIP_LAYOUT WIREBOND about "wirebond add nonstandard" command
/ A) E( Z& B( Q. g \930894 CAPTURE TCL_INTERFACE PDF export doesn't creates property file if some symbols are used in page name/folder name
) A9 I( f- z7 L5 z w$ \# Q930978 ALLEGRO_EDITOR SCHEM_FTB 3rd party netin error - Pin is connected to net <netname> not reconnected no longer happens
% d2 a! O! ?; \# Q+ Y931248 ALLEGRO_EDITOR DRC_CONSTR Match Group was removed if member nets became xnets.
5 d ~$ e' H: f931274 ALLEGRO_EDITOR DRC_CONSTR Negative Plane Islands waived DRCs reappear after performing update DRC.
/ E" G. }: \+ a, `0 O1 l# B932639 SIG_INTEGRITY OTHER Add Connect command hangs for about 14 seconds and then returns.* k/ n g1 ]" H
933145 F2B PACKAGERXL Add Subdesign list is truncated in Force SubDesign Design Name pulldown
& w# j8 m! b* W# B. b9 }+ K% K$ R. K4 @ v$ y
DATE: 09-9-2011 HOTFIX VERSION: 037
, B0 l! B/ y6 ~5 Z' f! i===================================================================================================================================
) H" U& [9 {1 e; gCCRID PRODUCT PRODUCTLEVEL2 TITLE
$ a0 v+ p2 ?& } P===================================================================================================================================" T) I5 y& @0 J" v! \
734687 PCB_LIBRARIAN IMPORT_CSV PDV Generation of entity view fails after CSV Import" ~0 p6 B* B9 H. }% @- r! x5 D
734718 PCB_LIBRARIAN IMPORT_CSV PDV Import CSV corrupts parts and generates duplicate $PN on some pins
, i3 b: r7 e1 ^1 a& u820131 CONCEPT_HDL OTHER Moving symbols to other page will make Allegro components unplaced because logical_path changed.
/ W6 Q, n7 O6 U0 K3 n, c868712 SCM UI Why can't I modify CAP associated component?; O) [3 u0 |0 i. ?; Z) \ I8 b
920327 CONSTRAINT_MGR ANALYSIS The TotalEtchLength predicate in Constraint Manager does not work for a netclass with a bus.
+ u# C" i+ X3 {+ [2 v922066 CONSTRAINT_MGR ANALYSIS Custom measurement Actual not being cleared when layout changes.
) B5 G6 j$ H& o5 b1 y925338 CONCEPT_HDL CORE This application has requested the Runtime to terminate it in an unusual way# I0 z7 D/ U Z3 Q& i" Q
925530 SIG_INTEGRITY OTHER Why the single line impedance value for Top and Bottom layers are different for this design?
X* ~4 V+ C0 B( W% _( |* y% c925976 ALLEGRO_EDITOR MENTOR mbs2brd fails to import data$ T- A* p3 d6 T1 C3 t
926503 CAPTURE GENERAL Memory leak Capture/Pspice
1 U A9 A. t2 Z% b6 C; n926887 CONSTRAINT_MGR CONCEPT_HDL Pin pairs lost after Export Physical
! v; F/ o# b8 M+ a) `927637 SCM CONSTRAINT_MGR ASA crashes on change root and also performance is too slow.
3 b8 `# K0 o% f! s. R: w928286 CONSTRAINT_MGR INTERACTIV The value of pin-dealy has gone with long match group name.; _8 r& D. A" G
928483 ALLEGRO_EDITOR DRC_CONSTR Running Update DRC removes Via List DRC Error when via is actually not in the list
8 }/ G9 d C7 K, E1 p' G" m1 h929174 ALLEGRO_EDITOR OTHER Display mesure get different result between 16.5 and 16.3
" v. u, X9 \4 e929656 ALLEGRO_EDITOR PADS_IN PADS translation fails with Microsoft Visual C++ Runtime Library error8 K: H. r# K! Q5 q( X3 H$ q
. ~; S& z2 W- P
DATE: 08-26-2011 HOTFIX VERSION: 036
6 A0 j& L1 {' c. W; f, }( r===================================================================================================================================
& w0 F. X" D0 TCCRID PRODUCT PRODUCTLEVEL2 TITLE
& P! i/ U+ C4 T R===================================================================================================================================7 G* q; f! o9 R
891079 CONCEPT_HDL CORE DEHDL crashes with large number of commands in Winodws mode! I4 w& {* E: l9 }# q1 U
909595 APD LOGIC Inconsistency between export die text out and show element after pin swap
^ o+ z' ]4 N! l& k$ ]% X914870 MODEL_INTEGRIT OTHER mergedml fails to merger 2 DML files from the model integrity' w! }5 i. O9 i: b3 t- J
916321 CAPTURE GEN_BOM letter limitation in include file
2 z! e: L# e$ y, d9 C7 ~! x0 W917967 ALLEGRO_EDITOR REFRESH Update symbol resets refdes location for bottom side components only.# | T2 t" D+ A! J0 ~+ Z
919976 APD DATABASE Update Padstack to design crashed APD.# d& a* T2 L. S* Q, [
922519 ALLEGRO_EDITOR SKILL add_bviaarray command fails for some clines but not all
# \, {3 G* {6 q) `. O/ i; r* e& `/ i923910 CIS PART_MANAGER Copy & Paste operation from Part Manager copies properties only to first section of the part.
( K! C/ z7 c+ |924458 SCM OTHER Project > Export > Schematics crashes! e1 ]/ b5 v o3 Y
924621 ALLEGRO_EDITOR SHAPE Dynamic shapes are disappearing upon updating them to smooth.' f" P& U/ [' R: i( I
925193 SIG_INTEGRITY FIELD_SOLVERS Diffential Impedance (DiffZ0) values computed in the layer stack-up is incorrect; J1 J; G7 h% H! J1 k' {
926443 CONCEPT_HDL CONSTRAINT_MGR In new 16.3 "035" ISR Concept2cm will crash with error.- e4 k7 G) q o* ~8 i" |
0 U& z$ e0 t0 w ~: {) l' z
DATE: 08-12-2011 HOTFIX VERSION: 035: T: N6 p/ _ e
===================================================================================================================================6 b/ F6 g! p7 h9 V% Y! |
CCRID PRODUCT PRODUCTLEVEL2 TITLE
: E: B" z# U. m+ T) n===================================================================================================================================0 t& D) \) n+ v5 c+ ]
861956 CAPTURE IMPORT/EXPORT V16.3 is not respecting if the net names were written in LOWER CASE or UPPER CASE in EXPORT FPGA.9 E/ I1 X2 f- n& e: l
868216 PSPICE MODELEDITOR Encryption of subckt names, internal nodes, comments% X1 X; O1 B/ O2 q7 |
870247 PSPICE SIMULATOR Encrypt a model and simulate it, info about inside nodes being dumped in the probe file1 K: w) {9 e/ p0 I! r
874010 SIG_INTEGRITY OTHER PCB SI crashes when the Xnet is extracted with VARIANT_TO_IGNORE property.
1 a7 a# p+ e; k& [+ s882567 SIG_INTEGRITY OTHER PCB SI crash if boolean type prop was specified to VARIANT env.; C) U* E5 }( y+ V
895902 RF_PCB OTHER Alphanumerical allegro pin numbers are unusable in ADS 2009 Update 1
3 U. q9 G( H6 W0 B9 i895919 RF_PCB OTHER Round trip Allegro to ADS to Allegro requirement/ L, I- m, d9 O) v4 @
903102 ALLEGRO_EDITOR OTHER Zcopy shape command for cline seems not to work correctly.& ?4 d' {/ `! S+ D$ ?& T! h/ H
905533 ALLEGRO_EDITOR INTERACTIV Pin numbers for components on BOTTOM Side are moved in Preselect mode,when the BOTTOM layer is invisible$ `; T2 k1 y1 F! s( l6 _* o
905562 SIG_INTEGRITY SIGWAVE Noise margin seems not to be measured correctly with Eye Measure function.1 p1 y. |0 Q! ^/ A B' }+ v1 v
905777 SIG_INTEGRITY SIMULATION User gets popup message that halts an analysis until it is acknowledged
) e" z4 ?% N% N; o4 t. F+ l915630 PCB_LIBRARIAN OTHER Error when running SI Model Interface Comparison using IBIS models" _* \( T+ z7 f3 r
915755 CONCEPT_HDL CONSTRAINT_MGR Cannot view net in SigXP
: C% E" Y, B1 n916462 ALLEGRO_EDITOR DATABASE Edit>Split_plane>create hangs Allgro PCB Editor; O, N' q' V; v9 {+ `7 C& R
916495 ALLEGRO_EDITOR INTERACTIV Pick selects components from invisible (Off ) layer( m) u6 p. h- Z6 f7 X- v! \
917434 APD OTHER Stream out GDSII has more pads in output data.* f8 x9 k! ^& G; Q! O- c
918187 CONSTRAINT_MGR OTHER Missing acGetTotalEtchLength predicate.
: o8 y! M' B9 R! S/ j8 @918576 CAPTURE DRC Incorrect DRC is reported for visible power pins which are connected to power symbol- w) C+ X5 i) D, u. u
919343 ALLEGRO_EDITOR PLACEMENT Place Manual is crashing the board file
( |2 P8 e" F" _919481 CONCEPT_HDL CHECKPLUS CheckPlus isGlobal function is not working/ K# P k. \- S: M7 ?1 a1 s7 U
920712 ALLEGRO_EDITOR ARTWORK Program has encountered a problem ... error when creating artwork, T3 {$ D% e7 @: v+ H
1 H4 H, ~- C4 L& K9 ?' E& |, K2 m$ @DATE: 07-29-2011 HOTFIX VERSION: 034: @3 o! B: g3 M* M4 [! K: r
===================================================================================================================================
: O7 `* |9 S) O9 V7 c/ I) ^" zCCRID PRODUCT PRODUCTLEVEL2 TITLE
$ B7 \( l! {; q% U" S; C===================================================================================================================================9 ~: i, Y$ A) g3 F/ h* b
882677 EMI RULE_CHECK bypass_plane_split fail if BYPASS_XXXX_EFFECT_DISTANCE; k0 x" W/ u |! N
897196 CIS LINK_DATABASE_PA Schematic Contents are not shown in CIS window while link Dbase part for parts placed from library
8 U. {1 I D$ S4 \: ^% x4 X902066 ALLEGRO_EDITOR DRC_CONSTR Shape in Region not follow the constrains% P7 g# j$ l8 [( Y3 D$ _
903719 ALLEGRO_EDITOR INTERACTIV Nets highlighted by netclass cannot be selected on the canvas to dehilight
0 f+ w9 @6 n- x9 ]% z) M, I& D Z903898 PCB_LIBRARIAN GRAPHICAL_EDITOR PDV move symbol graphics and Undo causes corruption in graphics0 @' I- N5 r0 {: ?( V3 X; v
904287 ALLEGRO_EDITOR ARTWORK some cline with arc is missed, when creating artwork.
. U) r9 ?; A, {0 n! L905796 CONCEPT_HDL CONSTRAINT_MGR Fujitsu CM issue inaccurate concept2cm diff pair issues& P/ E( x* l* ~" o8 H* G" N2 d
907885 SIG_INTEGRITY OTHER Matchgroup targets lost when importing netlist to Allegro layout in HF31
. J7 V$ I2 k$ V1 h' b908057 CONCEPT_HDL CORE DE HDL crash with the cut and paste of a signal name
3 |, C% M9 ]* G! l$ B$ X908060 CONCEPT_HDL CORE CTRL+LMB Option not working correctly in 16.3
3 h( ^+ v. R( _$ R908680 SIG_INTEGRITY OTHER Extra prop delay due to resistance
7 q4 \! p1 ]! b# }+ f1 G( p908874 CONCEPT_HDL CORE Part Manager - No Part Found error when using CCR# 775788 feature( C' A6 |) k. I7 f" s, K |% t
909635 SIP_LAYOUT DIE_STACK_EDITOR Add Interposer crashes in SiP Layout( K1 ?, h9 Q X& l) }( Q& I8 v
910713 F2B DESIGNVARI Variant Editor crashes when you click web link under “ hysical Part Filter” window.8 m/ h4 r' E$ k( T8 W9 A
910936 F2B PACKAGERXL ConceptHDL subdesign net name is inconsistent* r! D) x1 u+ E; Y
911415 ALLEGRO_EDITOR COLOR assigned color cannot be removed
8 I6 C d( Z7 I0 z* i) ^912343 APD OTHER APD crash on trying to modify the padstack1 V; U/ e4 p2 T- u# Y, f
912384 PCB_LIBRARIAN CORE PDV Symbol Editor often freezes when moving groups objects by arrow keys3 U, j5 } k1 _+ s! u
912459 F2B BOM BOMHDL crashes before getting to a menu* d; Q; D1 b- W0 o5 y4 p5 p
912853 APD OTHER Fillets lost when open in 16.3.
$ Z* z9 P3 W5 n2 q$ d2 R913359 APD MANUFACTURING Package Report shows incorrect data3 S; O/ Y0 ]* x& D( C
913521 ALLEGRO_EDITOR SCHEM_FTB Netrev error “(40) Object not found in database” for a part which is packaged correctly in FE0 Q, |2 z6 S" |" E( z9 B; \
913586 ALLEGRO_EDITOR ARTWORK Cannot create the drill figures in this design.
$ D7 [( G- K0 x. }0 x! ~# M' V; ^914009 ALLEGRO_EDITOR DRC_CONSTR Diff impedance worksheet showing almost zero impedance for differential pair in attached testcase.
% J: a4 [% m* l9 M2 o& G w914558 ALLEGRO_EDITOR ARTWORK Gerber6x00 output creates unpainted niche in a shape8 J/ t T% D& Q" e2 r
915742 CONCEPT_HDL HDLDIRECT I get a newgenasym error and crash when trying to save the symbol9 u- n- ~7 J6 Q
916469 ALLEGRO_EDITOR REPORTS One Unrouted pin does not show in Unconnected Pins Report& N6 L# K+ v& a: q! n- o
% m2 d5 Y k9 I& {. t2 zDATE: 07-15-2011 HOTFIX VERSION: 033
! q) G3 a; M% M===================================================================================================================================" x0 z3 I4 ^8 P9 l# \( V9 [0 o
CCRID PRODUCT PRODUCTLEVEL2 TITLE% W3 i' g. ?+ b% B
===================================================================================================================================& `- n& o+ j. @0 E$ ^0 q
746562 CONCEPT_HDL CORE Deleting attribute causes other property value to move/change. r8 l. @2 N; O! X5 q6 V/ g$ G
902349 CAPTURE LIBRARY Capture crashes while closing library- E7 d4 D3 t& s( ?8 w" |, X
903171 PSPICE NETLISTER Why Capture is treating hierarchical power ports as floting nets in complex heirarchy designs?4 @$ F& x3 H7 v8 N
903713 ALLEGRO_EDITOR PARTITION Placement Replication do not work fine in the Design Partition
$ W4 a: O, ~8 X+ Z" q905337 CONCEPT_HDL CORE ConceptHDL crashes after Import Design process.
+ s1 P+ P4 G( C; @906153 ALLEGRO_EDITOR SCRIPTS Unable to run allegro script in batch mode on the attached board.
) I6 d) X( e9 w, o; d) H3 w5 h& |906517 PSPICE PROBE PSpice new cursor window shows incorrect result.! E, I# A. O- \: e b
906627 ADW COMPONENT_BROWSE ppt options are not read if ucb is launched from FM. works fine if launched from dehdl.
6 N" v/ Y( Z$ I6 L* ]9 `906750 ALLEGRO_EDITOR PARTITION Importing design partition removes the testpoint reference designation( c9 ]3 w E8 x( l# c% p: Y
906874 PSPICE NETLISTER Error less than 2 connections for unconnected hierarchical pin
6 |. W. |7 ?. `. h& G8 ]% x907095 F2B OTHER Part Manager does not show Error as Undefined when directive ptf_mismatch_exclude_inj_prop is used
! N5 A+ e; s1 {908000 SIG_INTEGRITY OTHER Inconsistence z-axis delay reported on Tpoint when define at via location.
3 S! r8 e4 |& U" z7 j908595 APD 3D_VIEWER Cadence Design 3D viewer" screen pops up and is all black because the colors have all converted to b
" M0 a2 ]& n' O" C908849 CAPTURE ANNOTATE Getting crash while annotating the attached design
( G, f5 d2 ^& o1 w+ v0 b/ z" b8 ?% ?909760 SIP_LAYOUT MANUFACTURING Create bond finger solder mask doesn't follow the mask opening as defined in the padstack* U( j' P5 i7 l5 E, E& k
909861 F2B PACKAGERXL NetAssembler broken within the latest 16.30.031
0 c+ L$ m6 J5 A# t% [. c
$ X4 T3 P# [" ~$ QDATE: 06-22-2011 HOTFIX VERSION: 032
& Q2 M7 A, _- V/ F3 {4 e6 i===================================================================================================================================
, j. v# w. o f0 [4 [& E9 TCCRID PRODUCT PRODUCTLEVEL2 TITLE
5 i! Z) d! F) r9 }* ]) Q5 E$ q, k===================================================================================================================================
5 @% T& m+ M* l774270 F2B PACKAGERXL Require to ignore space in Pattern setting to prevent duplicated Refdes.
1 [( x5 w. E8 ?! ?9 A: Y% K6 O833542 CONCEPT_HDL CORE PDF publisher font is NOT WYSIWIG with respect to what seen in DE HDL
" a, B' D+ [& O# Q6 I1 M- r893544 ALLEGRO_EDITOR INTERFACES IPC-D-356A netlist issue with BB vias.* |; U' j5 f) x0 s$ u
893765 ALLEGRO_EDITOR PARTITION Mail command not sending out email on Linux platforms.
- n( \" O9 W! x0 ~, t3 N! ^8 y895933 APD DATABASE Update Symbol shifts the center of the Dynamic Fillet and creating DRCs
5 z- ] K* e" y, \* G$ V0 [. x5 Y897484 SCM CONSTRAINT_MGR No match found for 'fileops.txt' in the search path& N# n5 X/ N8 x/ t" Q6 a
899556 ALLEGRO_EDITOR ARTWORK Import artwork seems not to work correctly.
2 [5 H- M# N: n8 D902959 CONCEPT_HDL HDLDIRECT HDLDirect Error while saving design
6 x6 R$ w1 i0 g% H4 j% O2 Q903680 CONSTRAINT_MGR ECS_APPLY Constraint Manager not passing all hiearchical member objects to a custom measurement.
5 L5 V0 e0 I" o2 C' S7 T" I1 w904403 ALLEGRO_EDITOR DATABASE Allegro crashes when refreshing module' |8 M; o- K) A' i' ]! F; `. B" ?
904771 ALLEGRO_EDITOR MANUFACT Pin Number display issue.
& T5 Q% X3 H4 m) p905144 CONSTRAINT_MGR ECS_APPLY Min Line Spacing is larger than Primary or Neck Gap less(-) Tolerance but No Warning in CM
6 h( L( r9 h5 l; E: Q905273 ALLEGRO_EDITOR MANUFACT Drill legend creates more tables than nclegend creates tapes4 I0 U1 p7 N4 @4 h; ?
905314 F2B PACKAGERXL Import physical causes csb corruption2 A# l: Q* M- k% p
3 P2 \7 h- [+ b
DATE: 05-28-2011 HOTFIX VERSION: 0312 w4 R- I+ Y( R6 |7 c) ~) l; H0 d8 [* T
===================================================================================================================================
. x* }1 g/ M* q n! c% b# s; A! u* dCCRID PRODUCT PRODUCTLEVEL2 TITLE
$ d2 I# U1 f# |5 ]===================================================================================================================================1 }. B! [0 o+ j3 ^
606959 ADW COMPONENT_BROWSE Key properties with blank values are not getting read in shooping cart) H2 H2 y5 V: b+ L
644122 SIP_LAYOUT OTHER SiP Layout - xsection - ERROR Adjacent conductive layers are not allowed, but these are diestack layers not conductor( y+ d! }. d4 m/ L
799014 CONCEPT_HDL CONSTRAINT_MGR concept2cm errors not shown in export physical after hier_write3 r5 Q, h9 c$ B
866830 SCM REPORTS Multiple lines added as separator between title block and report header instead of single line
& U. ?: J" z# {7 d( @% i866833 SCM REPORTS Extra indentation is left in the left side of the report when the Line Numbers are set to OFF
. }1 J" ]. S% R4 p; f) }9 s868618 SCM IMPORTS Block re-import does not update the docsch and sch view6 b* p: u2 ?% E! F8 R
869971 SCM OTHER Lower level hierarchical block schematics missing $LOCATION values- i/ G2 i% c) s. F- h
877091 CAPTURE SCHEMATICS DSN file size becomes very large after placing picture and not change after deleting it- f) J) g, p! y# l6 ]
879361 SCM UI SCM crashes when opening project& }' a; D5 Z6 m0 k' I
879496 CONCEPT_HDL OTHER Customer wants to have “the tabulation” key as separator in HDL BOM.
# |: E: [3 c- K' i; c7 s- O883760 PCB_LIBRARIAN METADATA Incorrectly formatted revision.dat file in the metadata folder
+ N9 P/ o5 V8 k& [/ A! |+ l5 F885391 SIG_INTEGRITY SIMULATION RLGC data sampling algorithm and w-element interpolation.
) g2 q& Q; X5 X* X' g886007 CONCEPT_HDL CORE All the read only pages are called PAGE1 in our hierarchical design9 \ T' s5 ?1 `2 q: I0 O# s
889426 CONCEPT_HDL CHECKPLUS CheckPlus does not find single node net
, h7 `/ D3 ~( [ s4 v( b- X) }892375 ALLEGRO_EDITOR PLACEMENT Place Replicate Update disband other groups, irrespective Fixed property added or not.4 g& K- \8 n1 s2 b6 s
892541 SIG_EXPLORER OTHER Export/Import layerstack through the technology file is changing the layer thickness
: h- [9 o5 Q, [1 b5 A1 L# V, f) f893743 APD EDIT_ETCH Route behavior when spanning pads not as expected.
5 s3 z1 o3 u% l t) p894499 SIG_INTEGRITY LIBRARY Tool crashes when moving a cline or selecting the Info icon with OpenGL on.9 H6 l- h- _3 ?$ {8 d
894582 APD SHAPE When making a dynamic xhatch Via shapes surrounding are abnormal.
) K9 ]( x7 z# |& {# @) I895542 SIP_LAYOUT WIREBOND SIP design crashing when moving bond finger using blur mode BLUR_BONDFINGER_PRESRV_CON$ F1 ?( L, e. d' u2 o
895591 ALLEGRO_EDITOR PCAD_IN Importing PCAD file fails to get to the point where we can map layers
+ d8 c2 [. V9 w% r% y) X* e895757 APD ARTWORK Import Gerber command could not be imported Gerber data' m# `/ ?$ e% j
895964 CONCEPT_HDL CHECKPLUS The CheckPlus command “getFileSubstrings” is not working correctly# e% r: { |7 R) s( S2 P: {, f
896302 CAPTURE LIBRARY Pin spacing option in Generate Part from spreadsheet0 D c/ O! G9 K7 s9 ~
896428 SCM UI Changed Ref Des value not maintained in DEHDL block when part is replaced$ I. z; T9 `& ]
897362 CONSTRAINT_MGR TDD Unable to create Region Class in Constraint Manager
7 v, C5 L2 r' c6 f$ O( v897654 CAPTURE EE_INTERSHEET_RE Capture crashes on adding intersheet refernces in abbreviated format on attached design.
8 X! j- w* k. u898941 ALLEGRO_EDITOR REFRESH update symbol moves refdes location of component placed on bottom side# }$ o) ?. E- D( J: D2 P
899344 RF_PCB BE_IFF_EXPORT dlibx2iff does not provide the component boundary drawing
) K1 G( [6 s/ u0 n900175 CONCEPT_HDL CONSTRAINT_MGR Few Xnets are lost from Match Group after packaging and importing the netlist to board file.
6 ]9 r* h+ ~+ C1 X900481 CONCEPT_HDL CORE Genview creates a larger symbol without taking the no. of pin in consideration
/ @$ j/ f8 `/ h. P900813 ALLEGRO_EDITOR DRC_CONSTR With rotated pads, pad (pin - via) soldermask spacing DRC is unreasonable.
% @ f, @% C5 R/ S% g8 g900905 PSPICE STABILITY Simsrvr crash and RPC Server unavailable error while running simulation.; v" c+ J5 Z" y
901909 APD EXPORT_DATA The "package_pin_delay_length.rpt" with Z-axis delay turned on seems wrong. N: q1 r- ~; S2 X/ q
902133 CIS OTHER The visible part property value are being shown very distant from part graphics on schematic
2 B J+ I3 r0 W/ ?& q& z1 C902166 SPECCTRA ROUTE Specctra crashes when reading in "bestsave.w" file
1 o; T9 P1 Q: b% ?# [$ M902177 CONSTRAINT_MGR CONCEPT_HDL Option to view the layer thickness in CM worksheet through worksheet customization
) V9 t; p% h5 |2 R' s x! r902463 ALLEGRO_EDITOR INTERACTIV APD crashes when we click ( show element ) on certain components
$ S a3 a* _ y1 P7 I902909 APD WIREBOND die to die wirebond crash
4 \2 \ i4 m" o4 X( [902933 ALLEGRO_EDITOR PADS_IN Pads_in fails while reading PADS ASCII file body/ `5 ^9 |2 V# t) `" ~" @3 t j {, K
; V( j/ F9 d1 N+ t$ J6 PDATE: 05-14-2011 HOTFIX VERSION: 030
g( r' `6 S) q ]) |===================================================================================================================================
# n$ X) Q) \3 JCCRID PRODUCT PRODUCTLEVEL2 TITLE* }9 n+ @" l; ]( |/ O! m
===================================================================================================================================" U* r! ]7 g5 y5 i
738247 CONCEPT_HDL HDLDIRECT Generate View hangs0 ~- r1 `. U9 W# r6 N; L9 \7 D$ u
803147 CIS LINK_DATABASE_PA Link DB part should not change RefDes of multi package part3 f! U# D7 s: @3 |
837640 CIS GEN_BOM date format of CIS BOM has broken macros of 16.2 in 16.3 version# U' N; R2 D, \6 }
838763 CAPTURE GENERAL Deadlock situation is reached while opening BOM reports ("<something>.BOM" cannot be opened)
* { `& M; q; C7 q' S1 [3 S5 @1 l858245 CAPTURE IMPORT/EXPORT PCAD import does not work in 16.3/ o' |) `3 G3 s$ Y
860905 SCM UI Part cannot be replaced after it's added
4 O4 Y6 U( r: ]) M+ [9 ~! V% [1 |! U869528 CAPTURE SCHEMATIC_EDITOR Refdes increment on copying part is not with respect to occurence value.
% e/ `% C9 Q, B/ a) N8 H873402 SIP_LAYOUT LOGIC pin swap for co-design die in SiP
& ]! f0 o7 e6 e2 |) u2 ?877994 CONCEPT_HDL CONSTRAINT_MGR Assigning ESpice model to active component with Class, L6 t$ R; G, L8 N% g7 x8 X
883164 ALLEGRO_EDITOR INTERACTIV Vias marked fanout moves away from position when moving component
' C1 u( _! y% i; E* g887442 APD SHAPE Copper pour of Dynamic shapes on Top layer which contains many existing signal traces fails.
8 ]5 ?3 L2 w- q2 y887477 CAPTURE NETLIST_OTHER Other netlist is missing some nets and components after refdes changes in the design2 ?+ ~/ e/ F! q. J- l8 [, T: y
887578 SCM AUTO_UI Component Replace pops-up the DSPANE-204 Message6 ?& ?3 T9 V7 ^; y$ X1 L
887926 SIG_INTEGRITY GEOMETRY_EXTRACT Field solution failed if diff trace on bottom doesn't have reference plane.
K, w, t: l" x888414 SIG_EXPLORER OTHER View Trace Parameter display the thickness of dielectric incorrectly.
: K5 i M7 A! I3 N8 t888600 CONCEPT_HDL CREFER Cross References not added to Schegen schematic
3 H; F/ e4 f. g. i% v$ |8 U: m2 S& V888804 ALLEGRO_EDITOR OTHER Fillet will become static shape after import from partition board.) v7 U. C7 u2 R) h2 Y& X' M
888945 CONCEPT_HDL OTHER unplaced component after placing module6 |% J3 o( r) W+ t# }. p; Q `
889365 SIG_INTEGRITY GEOMETRY_EXTRACT top/bottom trace impedances extracted to sigxp are wrong in 16.3
; d# ~! R ]0 e+ S9 a2 X3 [9 N889404 ALLEGRO_EDITOR OTHER Incorrect pad size for Top conductor padstack written to column 59-62.
: z, F9 J ~, I/ L889636 ALLEGRO_EDITOR MANUFACT Incorrect spelling of "Visibility" in "Film Control" tab in the Artwork Control Form7 n' z( q, _* [4 `0 a' y
891235 F2B PACKAGERXL Packager crashes without creating a pxl.log file
1 z4 A7 l, T; O! K2 l B3 _891856 ALLEGRO_EDITOR EDIT_ETCH crash when sliding diff pairs
9 @7 v# ]% y3 `& S/ J5 N. S892455 ALLEGRO_EDITOR SYMBOL Why the overlapping pins are not reported with DRC?7 a. S- D" R5 y9 V7 D
892766 APD WIREBOND Excuting Finger moving cannot push aside finger to move with together by shove all mode8 M# `; {$ p* s8 R: j7 q
892907 ALLEGRO_EDITOR DRC_CONSTR DRC not reported for etch_turn_under_pin violations
0 \: F0 _" N0 s I% ~892991 APD BGA_GENERATOR BGA Text In Wizard creating two refdes text at the same location.
8 F& I8 R @! U" k& O# W893295 APD WIREBOND Why move wirebond command does not shove wirebonds? This result in drcs.
# s, y2 u, O* \% w! C# R$ z4 p/ l. i& |3 v! g
DATE: 04-22-2011 HOTFIX VERSION: 0298 a( R4 ^# F4 ]$ G: [ E1 J
===================================================================================================================================
' A* T, I6 B* [' V* d% ~' u* XCCRID PRODUCT PRODUCTLEVEL2 TITLE
8 L/ l& F$ f; k1 ?4 r( H; `7 P===================================================================================================================================7 F* P4 c) J/ N! ?/ j
789198 CAPTURE PROPERTY_EDITOR Newly added user property to a symbol can not be moved on the schematic page.# D+ N$ O+ x! q
812501 CAPTURE NETLIST_OTHER Extension of PADS netlist is .NET in V16.3. It should be .ASC.( U- M$ j. T* Q0 A
842161 CIS GEN_BOM CIS standard BOM taking long time
4 c; p2 v6 C6 d5 [844125 CAPTURE NETLISTS Normal and convert view placed in same design don't get netlisted due to duplicate power pin names.
1 M" w( a; ]3 b* }4 z847688 CAPTURE PROPERTY_EDITOR Property Editor changes selection on Display
$ U6 @! [0 B3 t' I6 u0 @6 X851044 CAPTURE GEN_BOM "Export BOM report to Excel" does not appear in the Standard Bill of Material Window.
~4 D% N8 V# B/ `; ]862785 CAPTURE NETLISTS RINF netlist with net attributes generetaed by capture 16.3 is not getting loaded in CADSTAR tool4 v, _" f0 C* M1 z* A
868118 CAPTURE NETLIST_ALLEGRO Differential pairs not getting netlisted in hierarchical design.
' v. H/ C& B/ G; E3 h880219 CIS GEN_BOM Standard CIS BOM does not viewed properly if underscore presents in Part_Number property
5 l$ d) v* q* U& c( ~( l" i881792 ALLEGRO_EDITOR SHAPE Cannot Delete the Islands on the shape. No Error reported.9 I4 h: v/ Z0 h9 y* m
882128 SPECCTRA HIGHSPEED Difference in length report between Allegro and SPECCTRA
% ^/ B+ T. l, K0 c" X* w* ]2 [883224 SIG_INTEGRITY SIMULATION crash while reflection simulation from Constraint Manager
& a: Y6 U0 N! z$ }9 }" i( E883291 SIG_INTEGRITY OTHER Z-axis delay causes incorrect actual values for delay% C' d2 W; u+ k v
883971 APD EDIT_ETCH APD crashed when I tried to add cline in (-6674.79 -7506.74) via.! }' N: j. d7 U: h4 `
884061 CAPTURE SCHEMATIC_EDITOR multi-line text zoom doesn't work correctly
8 E$ K$ x6 j4 {6 ]4 \6 C884181 ADW DBEDITOR Parts get released anyway without any errors flagged.) E* X3 _( Q4 s
885019 CAPTURE GEN_BOM Create BOM causes Capture crash with include file
) V! E3 m6 u! w/ F, H" F886437 ALLEGRO_EDITOR SHAPE Change of behavior of NET_SHORT between 16.2 and 16.3
* v. Q2 H8 \2 N887190 ALLEGRO_EDITOR PADS_IN getting parse error during PADS to Allegro Import
( L: y6 b& r/ S! t+ U( p887348 ALLEGRO_EDITOR MENTOR mbs2brd translator crashing without any error message in attached testcase -v16.3s027# G* D( d/ g( ~* D, S6 j
) E2 T- m9 a: z7 Y/ y4 C
DATE: 04-8-2011 HOTFIX VERSION: 028
3 I7 u5 L- w8 e/ V===================================================================================================================================
# I5 g; p" k4 o1 g* T" p9 Y# _/ |" Y8 NCCRID PRODUCT PRODUCTLEVEL2 TITLE
5 ]5 f X1 |0 V===================================================================================================================================
+ ?" `# T$ F$ y1 s* i704398 CONCEPT_HDL CORE In Windows mode basic shortcuts do not work when in German language1 ], B0 ?: `6 c! X% V+ y
771137 ADW LRM LRM reports 'Injected Mismatch' for a value based on capitalization of ptf value
- o- b, V# \4 G* z; @4 Q872547 CONCEPT_HDL CORE Document schematic - Published PDF is missing Bookmarks# }2 M W' E6 A2 ~, \" K
875001 CONSTRAINT_MGR OTHER Click on the Constraint Manager selected net filter icons crash software.6 J. k; v% [* q) _6 _) X! _
875039 CONSTRAINT_MGR ANALYSIS RPD margin is not calculated in 16.34 n( v, _" m5 G$ Z j- `8 u
876275 CONCEPT_HDL CONSTRAINT_MGR Constraint Manager not retaining target net
& ] w6 h% F& K( V- `5 ~+ f877912 APD DRC_CONSTRAINTS Shape to Shape DRC seems to be behaving inconsistenly above 90 um spacing on mcm database.
7 U1 L6 X" T5 K! |( X/ A {( ?878022 CONCEPT_HDL CONSTRAINT_MGR NO_XNET_CONNECTION is not working unless defined on last discrete before receiver# D, } S. ?' P! x
878519 SIG_EXPLORER OTHER View Trace Parameter - stripline trace model display incorrect distance to the reference plane- m. V1 ~7 z& E# @. _- @
879529 CAPTURE NETLISTS Misleading bus/pin ERROR [NET0081] message from PSpice netlist" ~8 v4 q2 P& I
881455 ALLEGRO_EDITOR INTERFACES Some Drill Figures missing while Exporting DXF. b. T4 R/ _+ D9 x* r
881711 ALLEGRO_EDITOR SCHEM_FTB Spacing constraints(Net Class) from schematic are not transferring correctly to the layout% N# G$ y' ]3 r8 D- y; }
882277 ALLEGRO_EDITOR DRC_CONSTR Get Bogus (false) "Thru Pin to shape spacing" DRC for Oval slotted pads.
/ i- w( L+ P( q8 K+ T; N0 |882408 SCM SCHGEN Export physical fails due to netlisting error with the ASA exported schematic
2 K' m7 C! X4 N9 i9 g882796 APD OTHER GDS stream import results in a set of bumps misplaced... possibly rotated 90 degrees3 d3 S& b" i- D6 {
2 d% M' ~, Q0 {8 wDATE: 03-25-2011 HOTFIX VERSION: 027
0 z0 X! x4 i6 [) `) R2 @===================================================================================================================================5 X- w5 a9 G4 r
CCRID PRODUCT PRODUCTLEVEL2 TITLE" |1 p" o4 j' A/ @1 C) x: y) d
===================================================================================================================================
9 i- d) F! E0 h7 w- v820901 EMI SETUP Request EMC system.conf file that can be read from CDS_SITE.# @7 C! r( P2 h; C9 j' o. r
861999 ALLEGRO_EDITOR DRC_CONSTR DRC hang after padeditdb
. c4 f) s. e2 T) l+ c6 Y862463 CONCEPT_HDL RF_LAYOUT_DRIVEN Rotating and Mirroring RF components in DE-HDL requires RFFLIPMODE property to be correctly updated9 v2 n" f; C& U( y+ n
867223 ALLEGRO_EDITOR SHAPE Shape fill disappears when Negative shape is converted to Positive in Cross Section
6 f- A. L8 z8 s- b* H. k868733 CONCEPT_HDL ARCHIVER ASA Archiver not saving the entire design.9 h5 ]4 |* q7 T$ c
871548 ALLEGRO_EDITOR MENTOR Shapes missing after mbs2brd translation
2 j+ K1 `9 A, }2 U# |# w872003 SIG_EXPLORER SIMULATION TDR simulation results were different between 15.7 and 16.3.9 h3 C; {0 ~+ F0 k0 L: e! @
872464 CONCEPT_HDL CORE DEHDL script works in SPB16.2 but not in SPB16.3
/ ?2 ~0 t$ F" |2 b1 Q873772 SCM CONSTRAINT_MGR Importing a block results in subblocks coming in without properties
' f# E- d0 p- O$ M1 g6 U874335 SPECCTRA ROUTE Route Custom crashes SPECCTRA after routing for some time during "Running Route Phase".
3 B2 R6 l, [7 g# i0 R874989 CAPTURE SCHEMATICS Schematics jumps to another page after a mouse click
; y/ |1 M) d4 v7 W6 R/ v% e875161 CAPTURE NETLISTS Creating Allegro netlist hangs Capture8 g; s; h# [8 N7 s* Y8 w
875411 ALLEGRO_EDITOR NC NC drill produces Error processing extract . Program terminated.
. K2 V8 P0 A( t* f1 d. ]* c' Q) h0 c876004 ALLEGRO_EDITOR SHAPE Unused pad suppression problem in Allegro v16.3 since S020~S024
5 t% e; a( C# `# F876045 ALLEGRO_EDITOR SHAPE Oval hole drills do not void shape with hole shape drc when the regular pad is smaller than hole
( @9 X H2 Q4 B4 F876168 SPECCTRA_MENT_ IMPORT option to have a switch to prevent merging of plane layers during mbs2sp
( q: z6 Q/ n- b- b% a0 ~ o3 U3 G876210 ALLEGRO_EDITOR SHAPE When updating shapes to Smooth the tool will hang.
2 o) B3 j8 J9 W! r1 y876284 ALLEGRO_EDITOR DATABASE Executing SKILL file crashes Allegro
) S" H/ ^, M4 G# ?3 \877057 ALLEGRO_EDITOR MENTOR Footprints are shifted when importing from boardstation& @0 u( R I. k- V" n1 i
877549 SIP_LAYOUT WIREBOND Wirebonds not moving correctly when on an Interposer smaller than the die.- C7 `2 w7 u, t* S- l5 P- A) L) g! h2 O
877862 APD WIREBOND APD crashed when add Wirebond without any dump and cannot record script.8 {! q% n. m% g1 e; T2 U# F4 H6 P {
878199 CIS DERIVE_NEW_DB_PA Change in Regional Setting causing problem in derive database6 g8 D3 u3 C; R& l
878216 APD OTHER stream_in - Stream file scan failed
; [; q+ {3 h- f: \878400 APD WIREBOND unable to add a wire bonding on few die pad
) X' N" ~4 ]& I$ W8 d( {
- s6 x9 h3 L; n" [' {/ u. A! sDATE: 03-11-2011 HOTFIX VERSION: 026
" e' ~0 \5 H( E1 t) z* a===================================================================================================================================! l/ |7 O2 e+ f# x) q
CCRID PRODUCT PRODUCTLEVEL2 TITLE
. N% [+ D3 ~: Z# X6 U& B===================================================================================================================================
2 a+ o n3 j; |6 O: [$ ?, ~0 X5 X( A8 \851882 SCM SCHGEN Multiple issues with the ASA generated schematic in preserve mode while using square bracket2 V ^* B, j& U* E
852063 ALLEGRO_EDITOR EDIT_ETCH What is being displayed in the HUD when a percentage is specified as a tolerance?
. v, G8 J2 M8 b* y6 {7 I& m854502 ALLEGRO_EDITOR DRC_CONSTR DRC not detected until DBDoctor is executed. Status form and sum dwg report are incorrect.4 o8 X# g/ R2 X7 q* o, v& w1 D
856797 EMI RULE_CHECK Arc segments were detected as warning by bypass_plane_split.1 B0 o9 a* k( V
859213 PCB_LIBRARIAN CORE $LOCATION size in PDV and DEHDL differ
) Q4 G6 `( M8 v W2 F860772 ADW PCBCACHE Save Shopping Cart (pcbcache) is crashing component browser! b0 q7 J$ X/ @+ o6 ^1 `
862259 SIG_INTEGRITY FIELD_SOLVERS EMS2D run twice during View Topology.
" L# I! Z) u$ _+ {5 m1 p, B865158 ALLEGRO_EDITOR SHAPE Shapes are not voided with Dynamic Shape Fill modes with Regions+ ?/ t; C+ \, i1 Y0 S
865295 PCB_LIBRARIAN CORE Part Developer crashs with symbols having Japanese notes
) H: Z/ {- h4 l3 w4 L7 J; F, o) y866095 PCB_LIBRARIAN EXPORT_OTHER Export DE HDL part to Capture Part Crashed+ Y7 F- M( Y @% U
866835 SCM UI User arguments not used over project arguments for new tool
2 |# z- C! j# T867102 CAPTURE LIBRARY Incorrect pin number gets assigned to pin if a PDF is opened before writng the pin number.: [0 f Y6 @2 w+ c
868092 CAPTURE GEN_BOM Capture BOM in V16.3 is different than that of V16.2 for attached test case.) L1 ~( e ^6 P3 V
868517 ALLEGRO_EDITOR ARTWORK A pinhole was made in the artwork file., h V' ~" G9 [6 @5 {* g" L
868646 ALLEGRO_EDITOR SCHEM_FTB Change in the PIN_GROUP at the chips level not propagated to the board file does not allow the swap
. v( y. e1 f p8 K868844 PCB_LIBRARIAN CORE BUBBLE_GROUP with no value causes problematic symbol
+ T% m5 Q6 z/ q! H3 ], k- d869326 CIS DESIGN_VARIANT View Variant is not showing part as Do Not Stuff
8 y9 [1 H( N7 \869547 ALLEGRO_EDITOR SCHEM_FTB Error while parsing the alternate symbol
+ _1 W v8 C9 g6 }7 b9 n869931 SIG_INTEGRITY OTHER DML Library Management rewrites library longer then 512 characters into multiple lines.( v& k- @: h) J5 w
869960 F2B PACKAGERXL PART_NAME property added to Export Packageable schematic parts/ ]2 I) d5 C; i9 g+ H( [
870392 APD EDIT_ETCH Route > Slide not performing as expected in 16.3
6 D: f/ T5 f: o) P" {5 a' n) Y870704 ALLEGRO_EDITOR PARTITION 2nd import of parttiotion unplace components in master
8 S5 \3 G/ Z+ a2 }: y$ j ~871177 CAPTURE LIBRARY Keyboard shortcut for closing the Place Part window
/ D8 O" Q' R$ Z871552 PSPICE SIMULATOR Pspice tool crash
% C5 ~$ G' j$ ~) Y- H& r3 O# E+ F871643 ALLEGRO_EDITOR INTERFACES IDF in batch and GUI for dra files fails to calculate extents correctly
4 T. B4 Q. A; _) C' H1 Z871968 ALLEGRO_EDITOR COLOR After using Clear All Nets, Color Dialog box needs to be reopened for adding custom colors.
( b* e6 Q9 Q3 @872352 APD WIREBOND Move Guide paths crashed APD.. r( C; q) w* g' |1 N6 p
872380 CONCEPT_HDL COMP_BROWSER DEHDL crash when editing the ppt_optionset.dat file from Part Manager.
) s4 k. i- X, J9 P8 C7 l872450 APD WIREBOND Wire to die edge angle remains highlighted in red for wire bond status window in v16.3/ N1 v+ h9 Q! s/ P+ ?6 Y( ?2 m
872787 APD WIREBOND Some Unused Wire profiles be purged but still existing in Bond Wire Profile of Color Visibility?4 z5 o. o6 W; q2 Y( C8 J* m
873217 ALLEGRO_EDITOR TESTPREP Testpoint generation not working correctly
* p% D3 @1 e( H \9 p5 G873500 APD REPORTS Total Plating value is 0
8 H4 S7 H \9 i% o, D, N873505 APD MANUFACTURING fillet size changed when recreate Plating Bar
3 C$ P' r9 f0 t F$ X2 ^$ j/ X873600 APD OTHER When attempting to Display Pin Names the tool takes a very long time.
7 x0 j) E9 ^* P874341 ALLEGRO_EDITOR OTHER "Gloss>Convert corner to arc" command made an unnecessary circular arc.
; s m$ e! F2 x& X
: O- p' \* L7 T$ v; E& i2 @6 {+ bDATE: 02-26-2011 HOTFIX VERSION: 0252 z/ l+ j, ?2 l2 ^( t7 r# G3 y
===================================================================================================================================
/ p4 L3 m6 ?, `* L5 Y0 FCCRID PRODUCT PRODUCTLEVEL2 TITLE7 k1 u3 M) [2 L, I/ X+ K) F a
===================================================================================================================================7 m2 V$ u3 X* V2 Q0 n5 H2 t
746063 CIS OTHER CIS Query Does not display initial search results
9 I+ p/ H+ |, @ ]% H( n" c% i779588 ALLEGRO_EDITOR PLACEMENT Symbol outline not rotated with component.$ @) i% t" ]% _. Q) ?' n
805616 ALLEGRO_EDITOR ARTWORK Allegro produces warning about database extents exceed film size5 O1 X% m: c1 ^/ U6 z
843145 CONCEPT_HDL CORE Cannot copy grayed out properties in the Attributes form to the buffer+ v! f: y$ Z5 B: @9 f* M" H* u
845607 ALLEGRO_EDITOR EDIT_ETCH Sliding with arc gridless enabled leaves extra segments behind and 45 degree segment.+ Q: h) j/ l9 \: X) T, M/ d
850428 SIG_EXPLORER SIMULATION SigXP failed to simulate the topology with designlink.
. e# T) t; u3 j; M! V" i853665 SPECCTRA CHECK Scheduling violations reported incorrectly.% p% u, k& I( _ V% V" Y2 Z
855534 CONSTRAINT_MGR OTHER formula result does not update when length changed- j! {! i' `# c& Z K
855793 CONCEPT_HDL CORE Rename Pin on Block is not working in DE HDL with HF 21+ \8 \5 F* |) |3 M5 _) V* I/ y1 |
856306 ALLEGRO_EDITOR INTERACTIV Modifying pad instance corrupts db
. T: Y: a5 O7 D; {; A: z `859437 SIG_INTEGRITY GUI Log Scale setting of EMS2D was cleared by re-open design.
- c: h3 Q; r- F859850 SIG_INTEGRITY GEOMETRY_EXTRACT Allegro freeze during topology extraction with EMS2D.
+ d2 e( b1 q( t7 d3 @+ X$ P. D860366 CAPTURE CONNECTIVITY Netlist is different in V16.3 than in V16.2
: i: L/ _4 }! ]6 P s, U860809 F2B BOM Bomhdl failed to create the design view check for existance of the packaged directory
: I$ G- s* u2 i) \5 d+ a# n861027 CONSTRAINT_MGR CONCEPT_HDL Unable to synchronize the constraints" j% V# X6 r* ^" ~" r A: K
862137 SIP_LAYOUT OTHER SPB 16.3 SiP Logic - Derive assignment is unable to resolve connectivity of shapes; |* c6 x6 x8 r& B# h/ `. H [
862980 ALLEGRO_EDITOR EDIT_ETCH When sliding a via the potential DRC behaviour is inconsistent.
. O) y0 F. R J7 G6 \863400 SPIF OTHER SPIF does not translate the oblong pads correctly
! ^ R$ ^& g8 [; ^) A6 d2 I864363 APD REPORTS The Wirebond report is failing because there are Non-standard Bond wires present.) g2 Q. Z, ]+ s% A/ n
864621 ALLEGRO_EDITOR DATABASE Database corrupted after adding layers in Cross Section and trying to save the board file.
4 \) Y* f* T, ?! I& M# \' R865875 ALLEGRO_EDITOR MENTOR mbs2brd translator results in broken/unrouted nets even though the BoardStation design is fully routed
; p2 @# E6 O& f4 p/ U" s; `8 f866202 CONSTRAINT_MGR OTHER Worksheet File import fails with error message due to character limit
8 _5 Y/ I6 T3 k3 q866726 CONCEPT_HDL CREFER TOC (table of content) not generated in schcref_1 schematic (CREFER flattened output).% o# s" |4 x) R. P0 M2 c! D) ?
867238 CONSTRAINT_MGR INTERACTIV Split Xnet for diff pair crashes PCB editor3 O/ K* U0 k% q1 S6 Y
867696 SIP_LAYOUT DIE_STACK_EDITOR When doing an Info on this design it will crash.- K' f% p3 L+ j: q- m
867742 ALLEGRO_EDITOR DATABASE Thermal Pad view for shapefillet on Negative layer
4 e7 |/ U) L3 v' U( t2 w867842 CAPTURE PROJECT_MANAGER Capture crash with 'Open File Location"5 w% _* j9 `2 c0 y
868306 CAPTURE CONNECTIVITY mirror vertically removes junction creates extra nets7 f4 v6 \+ a4 n" t9 H1 \8 y; r
869758 CAPTURE GENERATE_PART Generate Part option "Copy schematic to library" does not copy schematic page attributes
7 q0 h+ w) d" H, S869941 ALLEGRO_EDITOR PADS_IN PADS_IN unable to import Power PCB 2005.0 file in 16.3 but works with 16.2
( ^7 b# N& Q2 }870301 SIP_LAYOUT SHOW_ELEM When selecting Info and then a rectangle shape, the tool will crash.
+ X, X% r6 j* ~# F$ L% ^( u9 o
& J1 `5 }$ L/ b; j5 ^DATE: 02-11-2011 HOTFIX VERSION: 0245 J" T" X; ^0 ^9 X7 d: @8 R: F& p- Q
===================================================================================================================================
/ |0 y* z0 A& w* S, G2 UCCRID PRODUCT PRODUCTLEVEL2 TITLE) f- y+ _. g+ Z1 @
===================================================================================================================================3 I# l$ t ]# v7 O( E2 Q
858051 ALLEGRO_EDITOR OTHER Allegro's Help>About... System Info... doesn't work on Win7, C, I F) K- z# ~9 _2 f& R! U: }
862703 ALLEGRO_EDITOR DATABASE crash when doing a save_as$ {. L( _( s3 V1 }5 u
866288 ALLEGRO_EDITOR NC Drill customization table won’t let you add characters in lower case% d$ B @' v4 w! N
866310 ALLEGRO_EDITOR DRC_CONSTR Testprep doesn't create a DRC for Testpoint > Component
$ o2 K6 b7 {7 Z& c5 u866652 ALLEGRO_EDITOR SCHEM_FTB Allegro Spacing net class not updated with new logic! ~* q& S* v) |2 ^
7 @7 V b" m9 a1 o; _* @
DATE: 01-28-2011 HOTFIX VERSION: 0233 f& @" K1 k, j* L
===================================================================================================================================
( S0 C. V! u; M; M. _* n* e1 DCCRID PRODUCT PRODUCTLEVEL2 TITLE
0 i8 K9 k3 V' a0 V9 c=================================================================================================================================== N {* i! M, s
739067 SIG_INTEGRITY SIMULATION about modal delay of diff pair net
. z' e/ R( e: X4 w7 T, k* ]2 c742237 CIS FOOTPRINT_VIEW 3D Footprint view in CIS Explorer
6 H1 l% m4 i% _5 G! O2 i- L# F9 U762702 CONCEPT_HDL CORE Unable to change color settings
1 b: y4 J% q( n; Q800333 CONCEPT_HDL CORE Text change cursor not working on Solaris and Linux& s5 b- E$ G3 Y% S8 t
837479 CONSTRAINT_MGR DATABASE Import dcf with custom column cuases a problem
! k. l3 _. X8 ?5 Y) \& `# A846679 ALLEGRO_EDITOR SHAPE Through Pin can not be voided correctly in dynamic shape.
0 P( N4 S: D0 J: i7 ?4 v852255 CONCEPT_HDL COMP_BROWSER DEHDL crashes when adding part from cat file5 d# q* ^6 |9 |# O0 Q
855553 ALLEGRO_EDITOR DRC_CONSTR Multithreaded DRC shows different DRC counts
! l0 e# F0 g% B( s3 {856459 SIG_INTEGRITY GEOMETRY_EXTRACT No waveform was output if users set the Via type to Analytical type' R$ Z! ~# t5 q# |% \' [$ h
857030 SIG_INTEGRITY OTHER Inconsistency when signal model has "legal" spaces within it.) d7 Z/ Q- d" t" ^/ F* b2 G
857120 APD WIREBOND Enhancement for Redistribute Fingers.' ^8 i1 A/ I+ ~
857165 SIG_INTEGRITY OTHER Model Name Changed Warning appears every time after Export Physical
* ]/ g" b* x, a& Y857237 ALLEGRO_EDITOR SCHEM_FTB UserDefined mapping mode' ~3 k9 V% _6 y7 @) M
857650 ALLEGRO_EDITOR DRC_CONSTR Hole to line DRC unavailable on inner layers for mechanical pin with no regular pad definition.
! _! O: v1 J# K$ L5 L8 P1 a858046 MODEL_INTEGRIT TRANSLATION Ibis2signoise fails translation when the unit of Pin section is "ohms".6 Y) ~" k8 s7 e! K; X4 [! k: b
858154 GRE DETAIL Net not following the plan during Plan Topological+ S' Q, L' y# z* _* `4 {
858192 SIP_LAYOUT SHAPE Program crashes when attempting to add polygon shape.
1 n0 `3 ?. j! J) O858307 CIS DESIGN_VARIANT Homogenous part not showing correct DNI on schematic
$ @8 `0 ~: ~1 q4 m858624 ALLEGRO_EDITOR PAD_EDITOR "Save Padstack to 16.2" command is needed in 16.3 pad_designer.( z/ C! C( P% x/ D" ~( M+ N
858814 ALLEGRO_EDITOR MODULES place module not placing figures present in mdd
8 u/ u" I5 {) r859514 APD IMPORT_DATA Die Text-in cannot change unnamed Begin Layer to selected pad layer in step 47 U8 N/ v, d+ }0 I1 ~7 U0 w8 _
859640 ALLEGRO_EDITOR PLOTTING Shape based pads not output as polygon in IPF) F3 ~; J7 \# W& w; \
859680 ALLEGRO_EDITOR DRC_CONSTR Multithreaded DRC shows different DRC counts$ X% G! b. ?2 I5 T F3 l
860069 ALLEGRO_EDITOR OTHER Import Logic hangs then crashes and displays Netrev warnings.
2 L# c# Y3 `2 c$ l m860535 APD DXF_IF a2dxf got an error message8 a6 r8 ~9 |/ I5 L2 q
860860 CONCEPT_HDL COMP_BROWSER Component Browser freezes
8 z" x5 \# R, I+ Q# B0 s& }861295 CONSTRAINT_MGR ECS_APPLY Diff pair PCSet value overrides ECSet values in constraint manager spreadsheet.
9 a* D) t0 {+ \! u; I$ i862279 SPIF OTHER running 'Allegro PCB Router' Crashes3 e( O. x, j) k( A4 F+ [7 X
e) @7 P2 ~% |9 F, Q) @
DATE: 01-14-2011 HOTFIX VERSION: 0225 f; o: A# j: a: W" z
===================================================================================================================================& B. n) ]% J; \" s f. t2 g2 W9 b0 G
CCRID PRODUCT PRODUCTLEVEL2 TITLE7 a( z6 t: }9 I* Q) \3 A
===================================================================================================================================
, m- K2 a& H3 `0 G6 @, X372240 CAPTURE SCHEMATIC_EDITOR Allow component move with connectivity change should be checked by default
, B% Q7 t" B& a Y% ]8 } ^+ J5 P769139 SIP_LAYOUT DRC_CONSTRAINTS Wire to Bond finger rule in the CM needs profile to profile constraint capability
% W& N/ ]- ?0 O0 |, P772299 ALLEGRO_EDITOR GRAPHICS Via doesn't get highlighted properly with OpenGL disabled
% i- R3 d5 k6 n b% a! F- W830519 ALLEGRO_EDITOR GRAPHICS Disabling openGL causes highlihting problems.
, D+ Q2 a k7 t) O5 i0 |; \833981 RF_PCB FE_IFF_IMPORT DE HDL Import IFF unit conversion and unit display in RF schematic( |; s1 a! M& g. ^* ]1 r
835698 RF_PCB FE_IFF_IMPORT DE HDL Import IFF to assign simple sig_names like RF001 RF002 etc
' n: h e" r8 H/ ~3 g840094 RF_PCB OTHER dlibx2iff does not translate complex polygon pad/ Q; B# F h: w1 [& h+ ~9 r
844504 SIG_EXPLORER INTERACTIV EMI Regulation setting of the board is not reflected correctly when the net is extracted into SigXP9 Q+ [! o/ Q$ @! w- [3 D
846210 PDN_ANALYSIS PCB_STATICIRDROP IR Drop mesh is not correct.4 [( o9 e4 N. f+ I/ ~: I# {7 G
846228 SIG_INTEGRITY OTHER ZAll and Wirebond calculation in the Prop Delay formula
( f+ X7 J [. `/ l8 N" D, X846259 CONSTRAINT_MGR CONCEPT_HDL Why dont I see the P1_8V_DIG net in CM ?: r1 U* Y+ H: x- b( V- J" v. x
847278 CAPTURE TCL_INTERFACE TCL/TK PDF Export Change Page Size
B6 X5 E9 J8 W847942 SIG_EXPLORER OTHER The solder resist layer was not included in Interconnect Model of SigXP.. E0 m/ H0 D3 {% p& N& m
848181 PSPICE DEHDL Model association for concept symbols with a chips view doesnt work( T" o& O$ h' |2 U
849707 ALLEGRO_EDITOR MANUFACT Thieving creates unwanted thermal reliefs in this design.
7 |) G3 }6 J5 g851070 CONSTRAINT_MGR CONCEPT_HDL The Match Groups are not visible in the CM
# N: }! P+ M6 ^851171 F2B PACKAGERXL Design will not package with exclude_cdsNotOnSym
8 @0 a& g, K' e9 G: J851290 APD PADSTACK_EDITOR APD/SiP crashes when the user defined mask layer is edited with padeditdb.: u% r& `/ k+ C: [0 v1 }
851477 SPECCTRA ROUTE Allegro Router runs out of memory during route passes0 v/ \/ D3 M! [8 b/ T; R/ D0 T9 B; y
851658 APD EDIT_ETCH bunceback behavior while slideing cline
1 x# q* i3 d9 C+ t0 h8 X851725 ALLEGRO_EDITOR DATABASE Number of DRC is not consistent on each DRC update.8 L8 c% w; W0 D, u* Z' ?
851789 ALLEGRO_EDITOR SKILL Skill axlAirGap for Via & Text causes Allegro to crash$ h% n! m% D5 n7 e
852325 ALLEGRO_EDITOR DATABASE Perf advisor doesn't check high pincount devices for RATSNEST_SCHEDULE. @" [4 H* L; M Q0 T# m Z7 R5 P
852360 SIG_INTEGRITY OTHER Appling toplogy template to a diff pair object reports UserDefined in CM
4 ^* l. v- W- s% Z7 G! q852395 ALLEGRO_EDITOR DRC_CONSTR Same net via spacing broken drc shows up to date- \: V3 p/ W- E9 @8 r5 H
852764 ALLEGRO_EDITOR SKILL axlHttp beeps and gives error E - http 42/ d D! l. L: v! F( Y5 `
852787 CAPTURE ANNOTATE Tool is crashing during annotation if Ref Control is set- |! j. M i# f' }" z3 ]3 \: o
853110 ALLEGRO_EDITOR ARTWORK Allegro Crash on selecting Mfg > Artwork if any Parameter syntax is wrong in art_param.txt
( O, I7 T2 z& M4 ?% `9 @3 \854031 ALLEGRO_EDITOR MANUFACT The stream out data xxx.scf seems to be incorrect.
2 j9 R3 Q- S' u R, Z b/ K854246 ALLEGRO_EDITOR MANUFACT Stream out data of Oblong pad is strange.
2 j+ V. h8 J" K2 A: x854293 APD OTHER dynamic fillets were disappeared when open in 16.3.
4 B/ h. I: X4 r- m m- D" t854356 ALLEGRO_EDITOR OTHER Fillet adding doesn’t check same net spacing rule in both static and dynamic mode.1 R0 Y) o& W" s, Z5 l3 l/ C
855101 ALLEGRO_EDITOR OTHER Drill figures now smaller than expected( e. q) e. K5 p, g7 o, C/ X5 R5 f$ p
855124 APD PLOTTING The "load plot" command did not import Drill symbols(Figure) and Characters in APD., o: F' R- G; T, o
855348 ALLEGRO_EDITOR EDIT_ETCH Differential Pairs do not slide to correct geometry
; ^; k1 b4 z6 L$ |5 ^# |% I856220 ALLEGRO_EDITOR INTERFACES Export DXF in the 16.3 S021 build rotates some pin locations* r2 {1 p# U% R2 _2 b/ k: A3 H
856256 SIP_LAYOUT WIREBOND When editing a single Wirebond all wirebonds attached to the finger get highlighted.9 H8 ^* M' C" r( I1 Q: r0 ?6 L
856674 ALLEGRO_EDITOR AUTOVOID drill hole to shape autovoiding clearence is wrong for Same Net Spacing
% R) h4 w Z9 i L* x
; _% M4 b. G/ h0 `( V1 SDATE: 12-10-2010 HOTFIX VERSION: 021
+ e1 n6 F9 l: c- a# Q+ {) }===================================================================================================================================7 ^4 |( P+ M6 o4 W
CCRID PRODUCT PRODUCTLEVEL2 TITLE
2 h3 S( z, I0 S# t4 J===================================================================================================================================
, ]# P7 {( w3 D3 T708992 ALLEGRO_EDITOR SCHEM_FTB Design Differences fails with Error #534
" _# B* U/ R* I0 N- z% F- \# K t8 {748982 CIS FOOTPRINT_VIEW Respective pin number from schematic does not get highlighted on 3-D footprint viewer.2 d# _! d4 |' B( J
775788 CONCEPT_HDL COMP_BROWSER Component Browser search is too slow
9 X! V& e q& L7 l2 j802152 PCB_LIBRARIAN IMPORT_EXPORT cap2cond design translator is also looking for Capture feature string in license - this is break from 16.2' j2 p& z/ k4 B
803910 ALLEGRO_EDITOR GRAPHICS Request Rat like display for REFDES text to component.
; C/ ?' E3 C; K, t7 m823599 SCM REPORTS Ability to generate DEHDL style BOM report; @& B3 E7 {4 V' f' R# ?
826558 CONCEPT_HDL LWB-HDL Module definitions for cells is not included in the simulation verilog netlsit on LINUX
4 r9 `+ x5 P) y1 s2 R! t828689 CONSTRAINT_MGR OTHER formula constraint lost when Constraint Manager closed% M% w9 s2 b7 D4 y5 ?
831192 SIG_INTEGRITY GUI Cannot close Analysis Preferences window.
9 D4 L$ W' k2 M# R9 C/ A831229 ALLEGRO_EDITOR INTERACTIV When mirroring sym PLACE_BOUND shape does not mirror til placed
5 w+ }8 Q& \; T5 z: ^. `( J832315 ALLEGRO_EDITOR SCHEM_FTB ECO.txt file should not list net names if schematic and board files are synchronized.
6 S0 l2 B M4 d! c832644 ALLEGRO_EDITOR DRC_CONSTR DRC error disappears when the size of Constraint region is changed.# V ^7 ]4 ^3 C) [* C/ `
833061 MODEL_INTEGRIT TRANSLATION Model Integrity IBIS2DML fails to convert data correctly for pre-emphasis using Driver Schedule$ c' _; n, d ]+ |7 Q* c: H' F
833487 SIG_INTEGRITY GEOMETRY_EXTRACT Probe sim failed if VARIANT_TO_IGNORE was set.. D) C9 [; V( j# J- q% _) G
833922 CONCEPT_HDL CORE Move pin on blocksymbol using Block -> Move Pin command change the Pinname textsize
1 y; S7 L+ `. R9 u C; X' D/ t834103 ALLEGRO_EDITOR DRC_CONSTR dynamic diff phase highlight not showing
1 `- Y& }3 {% Y6 T& J v' d834868 SIG_EXPLORER OTHER View Trace Param crash if sweep param was set for loss tangent.1 C2 E* R d# Q" Y& r$ N2 k
835006 CONCEPT_HDL OTHER Locked BACKGROUND directive is changed in DEHDL session, D0 v4 ~$ m' _* m* R
835326 APD SPECCTRA_IF Specctra does not open from APD using Allegro Package Designer XL (Legacy) license/ v v$ \0 f. E
835622 CONCEPT_HDL CORE DE-HDL crashes when selecting wire having global sig_name in opened block schematic
' q# Q2 ?( N! o' q, [836962 CONSTRAINT_MGR ANALYSIS Simulation will crash
% p0 q+ s: ?4 z837216 CONSTRAINT_MGR OTHER Custom measurement Rslt lines being duplicated in a different worksheet.
( g1 X5 J6 J) |5 J1 f/ E% i: D. j837322 CAPTURE LIBRARY Library is not getting freed even when user has closed it., {& _ p0 d8 K, i! b+ c
839517 CAPTURE MACRO Macros (for place part) created on 16.2 version works differently on 16.3( w7 a; Z* r5 |9 e' V; S, H
839749 ALLEGRO_EDITOR MANUFACT Drill entries are repeated in .drl files
4 }3 G& c) S2 a840738 ALLEGRO_EDITOR ARTWORK Shape symbol in padstack moves when Artwork is generated - Break again after fix in 16.0
5 J, Q2 {6 q& M- S% z841176 CAPTURE ANNOTATE Homogenous parts are not getting packaged correctly in annotation in 16.3
0 N1 d3 M! b5 ^# o g5 u841355 SIG_EXPLORER OTHER Trace model parameter does not update when linear Range are entered.# {5 t; d) y. A- F9 c( `
841730 CONSTRAINT_MGR OTHER Allegro Crashes while working with MGs in CM
6 S2 V* O$ z% U" p% F/ P+ B841759 F2B BOM BOM creates an incomplete output when design packages without errors% G0 @9 ]. t8 q& t8 i
841928 CONCEPT_HDL CHECKPLUS CheckPlus fails when pin name contains _N in the middle of the pin name
+ P9 T+ l8 P. d. I8 m841991 ALLEGRO_EDITOR PLOTTING Offset of text and line on importing a plt file+ \# t5 q/ O3 f! z4 D
842204 ALLEGRO_EDITOR DRC_CONSTR Arc creates false DRC on edge of Constraint Area
# a3 I, f" ]8 Y9 A843114 SPECCTRA ROUTE Specctra rules file taking very long time to load
. z2 ~" q' z' |, v, \3 Q) a) C843254 CONCEPT_HDL CONSTRAINT_MGR Unable to invoke CM from DEHDL CM Crashes with an error Olecs.exe The application has quite unexpectedly- q5 P3 b+ ^0 |, L8 i. ~# S
843518 F2B DESIGNVARI Variant with FAIL_OPEN
3 b3 {+ S! Y4 d. L) {* ?843933 ALLEGRO_EDITOR DRC_CONSTR Cancelling drcupdate will either hang or crash Allegro
+ p0 |# d$ ?+ u* H i844074 APD SPECCTRA_IF Export Router fails with memory errors.
1 @- w/ [1 X5 u! A6 Q- ?. ?( M844246 ALLEGRO_EDITOR SHAPE Long Thermal_Relief connecting to XHatch shape
% e$ z% W, ] k( z- g0 C' e5 K# x844355 CONCEPT_HDL COMP_BROWSER User seeing CDS_NA appear when placing component
: G, k' X- P% f! i* q4 t, r844381 ALLEGRO_EDITOR SCHEM_FTB 3rd party netin - Pin is connected to net <netname> not reconnected.8 X, s% P' Q5 G6 R
844662 SIG_INTEGRITY OTHER Cannot uncheck options in analysis preferences.
# _* d& ~' P9 ^; Q ^0 w1 G844796 SIG_INTEGRITY OTHER Get an error E- Illegal model name. Cannot add model RE_RES_0402-16570580,when doing Auto Setup during Model assignment
/ g) r1 l0 ^8 x846172 APD OTHER Cannot generate the dxf file from this database1 A7 Z6 a4 b" f y
846270 SPECCTRA GUI SIGNAL_15 layer missing from the color pallete in Specctra
2 D. ?& s! X" ~! S9 i" t' H846352 ALLEGRO_EDITOR DRC_CONSTR Route connect does not select the pin-pair width for routing.
" `; ]/ b3 U( R, H: ]846420 F2B DESIGNSYNC Design Sync failes due to FUNC_VIEW_FILE missing messages
% [$ h( K3 V3 M7 z/ V846918 ALLEGRO_EDITOR PADS_IN Pads_in crashes when importing ASCII file, Runtime Error& B( ]! K" }! U9 z; l" m o
847079 ALLEGRO_EDITOR DATABASE Allegro Crash while trying to unlock the board file
; v. K) p0 O1 ^5 j848143 F2B DDBPI Adding part crashes DEHDL
, p& A1 Z/ E8 r# P2 z4 u6 y848415 CAPTURE STABILITY Crash on Mirror Horizontally* f/ J# T! | L$ {
& \( _2 d- ]" ?$ j
DATE: 11-11-2010 HOTFIX VERSION: 020
& Z( K5 _3 N7 e1 j===================================================================================================================================) j' b" z% t0 H4 A0 t+ q+ ^( L
CCRID PRODUCT PRODUCTLEVEL2 TITLE
( \' d. C5 y: g8 @4 N" c- L===================================================================================================================================8 A5 p' o' n3 x& ]; M. I7 }
501606 CAPTURE OTHER Descend Hierachy does not open first page
% W% u; A' F$ F) F* l1 f764482 SPECCTRA CHECK Allegro router same net checking different then PCB Editor.* G/ N9 C- i9 q8 z* I( ?2 N/ V
809055 APD EDIT_ETCH Shove Preferred changes trace widths of shoved traces during routing
7 o3 j; l* h5 r2 x& W" Q. o4 Z* k816920 ALLEGRO_EDITOR PLACEMENT Update symbols causing Allegro to crash& w% L/ l9 I4 W- p3 y; ]
826762 SIG_EXPLORER OTHER The rotation of element are different between pre 16.2 and 16.3.' G) b5 Z1 \9 u3 ^/ e+ I N3 M; m
827769 CIS FOOTPRINT_VIEW 3D footrpint viewer doesn't shows circular geometry on footprints( Z" w6 ?8 }+ T2 k" W! z7 X
828830 F2B DDBPI LRM does not update Parts which have a ALT_SYMBOLS value Added
1 Z) o% _- W9 \9 O830319 SIG_INTEGRITY SIGWAVE Sigwave load errors out with "Requested resource was not available" after large bus simulation
+ g9 j) u$ _ p8 e) p830359 CAPTURE GENERAL Crash on link Database Part
/ r; x3 h+ C0 Y ~2 a% H R830627 ALLEGRO_EDITOR DRC_CONSTR Incorrect thru pin to shape SPACING error
: N5 D9 n3 g3 p" J) b! g( W/ g" D830716 CAPTURE PRINT/PLOT/OUTPU Capture crashes while printing a Capture CIS Standard BoM with ISR s0017.
6 \* @0 v& x! t( }1 r) N830791 SIP_LAYOUT LEFDEF_IF Improve the LEF Library Manager to import passivation layers* O. o1 U0 r) r* N! U O) f
831210 CAPTURE OTHER Users get an error message everytime While running Update Cache with V16.3 and V16.2 with latest ISR1 P; h& u4 M. X4 d; o! j1 T
831231 PSPICE SCHEMATICS pspice com wrapper error9 ^- ]2 @9 q# y# P! w" J; c6 e
831692 ALLEGRO_EDITOR PLACEMENT Application becomes sluggish to nonresponsive when trying to place mechanical symbol
- ]' L0 X! h! y) X! T2 r* w831704 CONCEPT_HDL CORE ASA stuck in an error condition.& \$ h/ W$ A. B }5 Y
833116 PCB_LIBRARIAN IMPORT_EXPORT Getting LMF-02018 Error while Importing Capture Parts5 n5 v) { Y/ F- \2 @5 T0 }+ b
833433 ALLEGRO_EDITOR TECHFILE techfile in/out round-off a value of Conductivity(Xsection).& L! R4 G2 @1 e# S; G' y- E* W' @
833921 ALLEGRO_EDITOR ARTWORK Gerber filled lines stick out from filled area on Fillets: z8 b2 _: w# A$ Y
833950 ALLEGRO_EDITOR ARTWORK Artwork process create recrementitious circle for AutoSilk data.: {6 k! V7 \& V3 ~: ~
833975 SIP_LAYOUT DATABASE pad not on subclass4 c( k: f+ ]" J! k5 m% S
834152 APD EDIT_ETCH Route Slide of a Diff_pair section moves all of the cline instead of just the segment that you want.
- y+ ]# G/ R2 M' i0 O6 V. R3 B834861 APD OTHER package integrity runs for hours. results in no more room in database7 W! P: L6 J" P) P+ ^9 k: o* A
835367 CONCEPT_HDL SECTION Packager-XL reverses the pin numbers of connectors$ k' ~# J) X2 H7 z2 k& k
837805 ALLEGRO_EDITOR EDIT_ETCH Add Connect crashes Allegro when routing from a cline (not on a net) through a region.' a" ~6 l# x; i7 |
838057 CONCEPT_HDL CHECKPLUS CheckPlus crashes with long parameter.
$ ^+ D$ O8 v1 F6 q i838356 SPIF OTHER File > Export > Router Crashes Allegro and dsn file creation stops
, ~; e) j2 Y( L3 Z838521 APD MANUFACTURING When creating pbar some clines are gone.; ]; y0 Z- [. g# a( P- H2 e! A) p2 w8 j
838766 ALLEGRO_EDITOR EDIT_ETCH Sliding with arcs making sharp corners instead of arcs.: [' o& C" {3 E% E
838830 SIP_LAYOUT ASSY_RULE_CHECK Assembly rule check flagging a DRC for item not near edge border
4 l o3 p! A: t& j- ?6 g5 ]3 O838836 ALLEGRO_EDITOR SKILL Pb to check license with skill core function
5 {# E: E% Y/ r# m9 v839218 APD 3D_VIEWER 3D view of this mcm file is not getting rendered and the 3D GUI screen shows up blank in APD2 Y* t" F. e' d: s
839362 ALLEGRO_EDITOR EDIT_ETCH trying to slide a bbVia crashes Allegro
$ b0 `/ c2 q3 v. G* T" x% {839984 ALLEGRO_EDITOR ARTWORK Some pinholes were made in the artwork file.
( H* [8 L9 r" p9 B% s2 L840016 CONSTRAINT_MGR INTERACTIV Cannot manually create pin pair for unspec pins of Xnet.
) j5 c# t2 d6 O' i840455 ALLEGRO_EDITOR INTERFACES IDF exported/imported from symbol have no drill information for pad.1 p# _; v. v% N7 V+ L
841431 CAPTURE NETLIST_ALLEGRO Upgrading from Capture V16.2 to V16.3 some nets get shorted on the schematic page.6 F9 B: z* I4 \$ K
: |0 h% E1 a8 V( ]0 lDATE: 10-20-2010 HOTFIX VERSION: 019
0 Y+ @) H+ B# m' F" x; \===================================================================================================================================
7 S1 d p5 R7 L% F2 V. T! k/ QCCRID PRODUCT PRODUCTLEVEL2 TITLE" [3 \ S/ |7 h0 S2 m
===================================================================================================================================
0 R& B% m9 W# J, _) I4 x; N6 s0 {' k717365 SCM SCHGEN Option for Schematic Block to have the defined Sheet symbol/Page Border: L; ~! `) D' b, T
751477 ADW COMPONENT_BROWSE UCB in DB mode does not read local worklib for block symbols# i& S7 @; E' w3 K H. a
792545 APD PADSTACK_EDITOR Can not rename user defined Mask Layer in APD/SiP.0 F2 B1 r7 u' s* [
813436 SCM OTHER Option to have a directive in the cpm file to distinguish an SCM project from a DE HDL Project
6 j4 P- U3 r" J- {* p$ n820640 SIG_EXPLORER OTHER SigXP Crash after doing Transform For Constraint Manager5 ~ \ X( c- S! q
824527 CAPTURE PRINT/PLOT/OUTPU Part ref-des resets when trying to take variant print from Part Manager: H/ B' `- \$ [6 d, t! ~/ q
824688 SIG_INTEGRITY GEOMETRY_EXTRACT PCB-SI crashes when running more than 2 simulations
: a) m4 A5 F) `0 c# C, i826571 CONSTRAINT_MGR OTHER Import of .dcf crashes in 16.2 but not 16.35 \/ g! f, r& @5 ?0 \
826626 CONSTRAINT_MGR OTHER Creating a Netclass from a custom worksheet breaks the Netclass object upon the next invocation of Constraint Manager.
. ~ e# m9 q2 k5 }. n826799 SIG_EXPLORER SETUP_ADV can not close Analysis Preferences form when Advanced Setting button is opened and closed once
" Z l- y; b, }. J' ]3 P827375 ALLEGRO_EDITOR DATABASE Need to check why Net class assigned on the Net are not visible in CM& Q7 O0 @9 d R
827521 CONSTRAINT_MGR OTHER Allegro crashes when trying to open Constraint Manager.
2 z0 f3 h2 R/ B827713 SIG_EXPLORER INTERACTIV Cannot move object by click and drag after RMB>Note.
$ ^/ d B5 T3 n1 p5 N" B7 |828803 CIS UPDATE_PART_STAT Crash on update part status from Part Manager) G% r5 i2 \9 O+ k5 L/ a9 A: V, W
829005 SIG_INTEGRITY FIELD_SOLVERS SigXP crash when RMB click on the Trace Model with EMS2D.. d% r! P; g" X9 E( F
829008 SIG_INTEGRITY FIELD_SOLVERS SigXP crash when RMB click on the Trace Model with BEM2D.
; [, o9 X1 d9 p, N; L1 g829233 CONSTRAINT_MGR UI_FORMS Physical Csets applied on a diffpair is not followed while routing, though visible in CM.
; E4 Y: z4 w- x# ?6 R# N829340 CAPTURE LIBRARY_EDITOR propertries are shifting after being placed5 r6 r1 }" {3 |* x- e4 r
829747 SIP_LAYOUT DIE_EDITOR Move pin incremental coordinate
7 G2 g; F3 m4 j829991 SIP_LAYOUT OTHER The "axlAddAutoAssignNetAlgorithm" function is missing from the Allegro SKILL documentation.
5 p& c; _' u7 r" W7 ^830509 APD ARTWORK The measured airgap aren't between features in the design aren't consistent in Import > Artwork.3 M3 L( [4 I. u$ W( d: C1 _6 v- ~8 h
830809 ALLEGRO_EDITOR TESTPREP In the testprep report the Pin type is getting appended with net name
0 H' I7 O/ }& A# K$ r& Y7 q! Q830907 SIP_LAYOUT DIE_GENERATOR SiP will crash when adding a Standard DIE using the Die Generator.
+ n- p9 f$ i d5 a& [9 q831176 ALLEGRO_EDITOR MANUFACT Testprep Resequence crashes this design.
' Y2 y p8 C& Q3 k9 E831199 SIG_EXPLORER OTHER error in _sxUtilGetAllegroPart message was displayed.
4 O" q" D* O$ e8 N% C' {831610 ALLEGRO_EDITOR EDIT_ETCH Sliding with Diagonal Entry (45 Degree) is sliding the the adjacent vertical segment when Constraint region is present
! @% A0 E/ ]# k9 ]831946 ALLEGRO_EDITOR OTHER Cannot re-open Command Browser if it was closed by Undo.
: k! N" k' s0 i' E5 h& ^ j1 T831998 ALLEGRO_EDITOR SHAPE Allegro crash when user execute shape vertex add command.6 f2 U! j, V% I2 t+ r
832059 APD SHAPE Shape does not keep Shape-Via(w/ Fillet) spacing.
' @1 n; M: W6 j3 G9 B# V832169 ALLEGRO_EDITOR EDIT_ETCH Sliding with Diagonal Entry (45 Degree) is sliding the the adjacent vertical segment when Constraint region is present
' U9 J% M5 E B7 @* n832197 ALLEGRO_EDITOR EDIT_ETCH Sliding diffpair slides adjacent segment: I7 G$ q2 {- k7 p* _. F$ j
832613 ALLEGRO_EDITOR EDIT_ETCH Adding microvia and bbvia crashes allegro at location where overlapping shapes exist on other layer5 Z+ L" R0 C& V5 u
832922 ALLEGRO_EDITOR PARTITION Import partition board crashes Allegro.
4 f* T, Z. v- Q$ ^1 D* D8 w833127 ALLEGRO_EDITOR SYMBOL With 'unused pads suppression' the padstack (clearance) does not get rotated in the internal layer4 _" g" S# X/ r% _- n
833251 ALLEGRO_EDITOR SCHEM_FTB Power planes on Layer E3 and E18 change to dummy net after Refresh Module.
2 [8 E3 V& f5 n1 Y( u833586 ALLEGRO_EDITOR PLACEMENT Allegro crashes while placing jumper
8 V2 g) x% f# P# ~+ [; C4 C7 _* x7 P
DATE: 10-7-2010 HOTFIX VERSION: 0181 N2 p' _; p; j% M6 N% |: ^
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CCRID PRODUCT PRODUCTLEVEL2 TITLE
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398114 ALLEGRO_EDITOR INTERACTIV Need to differentiate between tracks and shapes on an etch layer.
9 F1 I. Z' E& P" ]6 b3 }6 E2 ?530659 ALLEGRO_EDITOR UI_FORMS Allegro Place Manually and Update Symbols GUI missing checkboxes on Windows Vista! R- ?) U, o3 W* G& Z& U! {! d: R ]
770576 ALLEGRO_EDITOR INTERACTIV Design Partition - Place replication not working correctly
`7 M8 R) x( c7 o" t u( h( H, u777925 CAPTURE OTHER Capture crash immediately after invoking* Z c: \6 ?- g8 ?9 x
807089 FLOORPLANNER INTERACTIV Logic > Net Logic hangs tool in Linux. K2 M$ r+ {/ n+ x$ r
809118 CAPTURE NETLISTS ENH to compare two schematic Capture designs
" m( ^/ y+ {6 o9 U812046 CAPTURE NETLIST_ALLEGRO Design not getting netlisted in V16.3 due to illegal characters in pin nmaes
, V- n6 S+ n. N3 ~0 i6 P( d3 p814607 SIP_LAYOUT IO_PLANNER update genfeed to add options to dumbp all chips files from design
6 s, m/ Q1 T6 h814750 ALLEGRO_EDITOR DRC_CONSTR BBvia and Microvia overlap DRC issue
! n3 B- F. L0 s" V. K8 _815621 SCM OTHER Enhance time shown in session log to support DST: R8 _1 T D$ S, z+ x4 K0 Z. U: O
815681 CONCEPT_HDL CORE The TOC symbol shows multiple entries for the pages; \6 \* A9 w3 a3 I3 h* @- D$ i5 D
817380 ALLEGRO_EDITOR DRC_CONSTR Incorrect or bogus line to line DRC errors are appearing between the nets of a diffpair: C5 b- T- J' [/ f' _+ T1 B
817881 APD ETCH_BACK Create Etch Back Mask failed, ?% M0 X' Z& z) a# N. |+ W
820771 ALLEGRO_EDITOR PLOTTING axlLayerPrioritySet does not provide the same capability than the 15.7 Color Priority system
3 W# h2 B. @0 }' R820773 ALLEGRO_EDITOR INTERFACES Import 3rd Party Logic $SCHEDULE removes visible ratsnest from database when using T-Points
! `% {( [4 f; T( R: ^820792 ALLEGRO_EDITOR INTERFACES Import $Schedule command is returning illegal loop error for pin-pair based rules; u0 f- t( v4 Z6 k0 ]8 C
821133 ALLEGRO_EDITOR MANUFACT Output artwork for pad data that are suppressed unconnected pads with Gerber 6x00 format2 h! d: e& V( P) }% }$ `
821504 MODEL_INTEGRIT TRANSLATION dmlcheck failed when .dml translated from .mod was opened by MI.1 k r' ? ?+ Q4 @# A3 |$ v
821827 ALLEGRO_EDITOR EDIT_ETCH Allegro Crash on routing Diff Pairs
0 }* ?& |1 @( q7 {& ~821836 CONSTRAINT_MGR OTHER Why the min/max propagation delay analysis is failing for one of the pin pair in this design!
- u' e& {, d1 j$ m822090 CONCEPT_HDL CONSTRAINT_MGR Crashed the Constriant Manager and SigXplorer from DE HDL
% J8 S3 e$ A( v5 D9 |822744 CONSTRAINT_MGR DATABASE Xnet lost after DCF file imported into Constraint Manager; p) a! [3 W' B5 c
822827 PSPICE SIMULATOR Simsrvr crash upon running simulation
) K2 `$ U" o& u& Y! x6 U4 L822844 ALLEGRO_EDITOR SCHEM_FTB Constraints are not updated in the brd file when working with Library defined diff pairs
" }9 `+ M! S5 W" L. F! Q) `& q822942 F2B DESIGNVARI Variant view does not show DNI on functions( c C4 Z9 ^3 u. ]% s* P
823177 SCM BROWSER PPT_OPTIONSET_PATH defined using environment variable is not recognized by ASA, f' R7 J6 Y( k- P9 P: Z2 _
823200 ALLEGRO_EDITOR OTHER Import Logic hangs when dynamic phase control set
- D- r% n) s) G/ G823589 CONCEPT_HDL CORE The operation could not be performed because no object on the drawing was selected
7 Z( `* g9 h5 m# ?9 Y- Q823821 ALLEGRO_EDITOR MANUFACT Allegro crash when trying to Gloss -: S5 H1 [% t2 p; T
823833 CONCEPT_HDL CORE show vectors command
8 N1 V% x2 j# W( T5 Z824902 ALLEGRO_EDITOR DATABASE Lose connectivity when copied via and cline structure
' c- \4 w G) L- r0 @# B! |9 [: k/ Z825289 ALLEGRO_EDITOR DRC_CONSTR duplicated drc and waive drc
( n- z; T' Q8 i5 P7 D825969 CAPTURE SCHEMATIC_EDITOR Refdes are getting reset after doing a replace cache/update cache for a generated pat1 q M/ C* {8 B) {9 E8 ~! M* F5 @
826068 ALLEGRO_EDITOR MANUFACT Adding Thieving on the negative plane layer doesn't show up
! @7 |! z3 E* m4 ]: l826266 ALLEGRO_EDITOR DRAFTING Datum Dimensioning Crashing Allegro in Linux0 {5 G! V! m+ y, k5 g
827032 SIP_LAYOUT ASSY_RULE_CHECK SiP Layout crashes when running Assembly Rules checks
7 B1 c0 q2 d; P7 [$ a827494 CAPTURE GEN_BOM Include file is overwritten for the STD Capture BOM if .txt file used as include file
7 M% A* y. \( j7 ]9 m9 [827575 CONCEPT_HDL CONSTRAINT_MGR PINUSE3 `' G4 V9 N( k# G: @8 B
827708 APD 3D_VIEWER 3D viewer assign black color for all layer8 P0 O9 w9 K/ v3 c/ |
828263 APD DXF_IF When the DXF out is executed, offset of the padstack is not correct.6 B! s0 W* ]) b, p
828788 ALLEGRO_EDITOR DRC_CONSTR Soldermask Waived DRCs reappear in 16.3- O2 {" j1 h4 O. m& G) W. p) W
829046 APD MANUFACTURING create plating bar makes net name changed to dummy net+ |+ y/ l: Y$ [* B
829331 SIP_LAYOUT PLATING_BAR Create Plating Bar is deleting existing fillets.5 t0 M3 ?' A/ |8 W5 u4 s
829336 APD OTHER Request the ability to merge two nets together into a new net.
" f4 |# |' w4 K8 a6 M- i0 Q& B7 M( t+ j6 T
DATE: 09-23-2010 HOTFIX VERSION: 017, w9 X+ B6 w& f2 c. ?, E
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CCRID PRODUCT PRODUCTLEVEL2 TITLE$ ^9 d6 o0 Y$ u7 v4 X& u' d. I
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676210 CAPTURE PRINT/PLOT/OUTPU Enhancement for correlate lower level pages with H blockes in PDF
% X: ~' N2 C# b8 X$ A736942 ALLEGRO_EDITOR INTERACTIV Autosave is not working with every application mode.# B2 g, r7 N. T8 @/ N" Z+ I w: `
746256 CAPTURE ANNOTATE Intersheet refernces change their position in V16.3 even on unchecking ‘reset position’.
7 [9 {( v8 d' ~785417 CONCEPT_HDL COPY_PROJECT copyprojectui crashes with a Windows runtime error; U/ t4 c: h5 S5 G% C! x, Z5 W
791549 PSPICE PROBE PSpice cursor does not remember value outside zoom area, s' c2 `* p& k! O
802639 F2B DESIGNSYNC BOMHDL crashes if colon is used as a sub design suffix separator
; d7 _0 J4 V" Q, q$ i804475 CONCEPT_HDL OTHER RMB+MMW doesn't zoom in/out anymore with ISR012( s2 p1 m* B0 t# ~# n+ n/ l/ {3 M; ~
807025 PSPICE PROBE Loading dat file slower in 16.3 as compared to 16.2) _& Y( B8 I1 j$ ^$ {
808550 CONCEPT_HDL OTHER On Linux Import design does not obey umask or setgid settings
$ Y6 |' k( ]& g+ g810568 ALLEGRO_EDITOR PADS_IN Can PowerPCB 9.2 - Basic file be converted to Allegro?% u; g1 [3 m* n+ ?
812089 CONCEPT_HDL OTHER The colors on the Options form dont seem to match the colors displayed on the schematic canvas# f. B) ?2 {& Z1 @$ R
812475 ALLEGRO_EDITOR INTERACTIV Saving .mdd always results in working directory# k; A, K! T( U& }7 N& L4 f
812836 CONSTRAINT_MGR DATABASE CM Custom Fomula -Handling of Pin_Delay is inconsistent in Analyze
; \4 S( @& P1 F3 }% B812994 SPECCTRA ROUTE Max_total_vias constraint not working correctly when wiring option is set to "starburst".! J( d0 h9 p b2 Q: ]
816561 CONCEPT_HDL CONSTRAINT_MGR OLECS.exe Runtime Error occures when attempting to launch SigXP from a net in CM
# W) L- n8 z% H6 n5 z% R816879 SIG_INTEGRITY SIGNOISE Program has encountered a problem and must exit in 16.3 S014(v16-3-85AT).
' F+ g3 z c, m817006 SCM UI SCM copy signal changes existing signal names
' G% x, E. D$ e3 y' C( f9 a817896 APD ETCH_BACK Etch back - improper use model
3 C( f M# N4 e0 q1 h' T$ @818242 ALLEGRO_EDITOR SHAPE Thermal relief connections not orthoganal and creating acute angles.1 F& B7 `' |; f8 |0 L5 A5 y: ^
818429 ALLEGRO_EDITOR PLOTTING Pins created from shapes do not plot solid.
& z8 @) n5 W- c) i6 z818513 F2B BOM Alphanumeric BOM not placing REF DES in proper order% @8 Q6 K: I) ^7 p4 L) Q
818818 ALLEGRO_EDITOR INTERACTIV Place replication does not recognize mixed case characters in file path
- `7 G% Y, f" M7 {$ l @# k# ?& y818910 CAPTURE FPGA NC simulation flow is not working with 16.3 release8 ]5 y$ ~' Z$ _' w" H
819108 SIP_LAYOUT DATABASE Wirebond profile constraints lost after saving and re-open sip
0 D( r [# D- H; a: _" Z819151 SIP_LAYOUT ASSY_RULE_CHECK ADRC is showing X-D DRC markers on good Soldermask Shapes when doing a min. shape check.
" I1 M8 X! w' i; L* m$ y819183 ALLEGRO_EDITOR MANUFACT NC Drill file generated for Backdrill layers show wrong Quantity of the drills
; q$ o9 S2 _/ V4 Z2 C7 Q3 j819269 SPIF OTHER File > Export > Router Crashes Allegro and dsn file creation stops* i$ U7 s7 p7 E3 F0 {
819463 ALLEGRO_EDITOR DATABASE VIA has illegal connections.
! U+ d" s+ C2 q/ r819842 ALLEGRO_EDITOR INTERFACES File Import Logic fails on syntax check when following documentation for $schedule command: q$ K! F) O$ H
820177 CONSTRAINT_MGR CONCEPT_HDL Net_class objects that are changed in CM at Front End are missing after Import Logic% _0 Z+ q& r% j- A( Q/ ^: `* k
820231 ALLEGRO_EDITOR DRC_CONSTR Allegro hangs when multi thread DRC is performed after updating padstacks( P. O" f6 J4 F; `! M7 @, ^
820373 SIP_LAYOUT OTHER Update symbol flags the "edited pins" error but still updates the symbol and then crashes.7 u' t% y. L0 M$ e
820381 SIP_LAYOUT WIREBOND When opening a new design, with a design already open, the tool will use the first designs profile settiings- k& ]" O2 ?8 d# ^2 {+ X5 x
820634 CONSTRAINT_MGR OTHER Netrev fails without any useful message when importing ECO netlist- j% L8 V! E* L6 h. G( J! Z4 ~
820665 ALLEGRO_EDITOR REFRESH Qvupdate is not working in 16.3
( ~+ a2 `) }9 ?: [( ]" O9 K# F820849 ALLEGRO_EDITOR MANUFACT NC Drill has wrong quantity and also a drill is missing
# F4 i; B# u+ T) _6 h* o821154 CONSTRAINT_MGR CONCEPT_HDL DE-HDL CM Import Analysis Results fails without any feedback
' M% O! i4 @( t% N1 |821195 CAPTURE OTHER Updating Cache generates errors including CAP0027 on Capture DE CIS with ISR s0014 and onwards.3 F' `- ]+ b: Y( J
821856 APD MANUFACTURING Create Bond finger Solder Mask issue. z. H+ @' X- \$ H5 x. |9 F% o
821936 SIP_LAYOUT COLOR Can not clear custom color of bondwire profiles1 r8 b+ ^/ w+ k3 o* ~! K
822841 ALLEGRO_EDITOR ARTWORK An issue about Gerber6X00' K6 {. s2 y7 G4 b; T
822842 SIG_INTEGRITY OTHER CM and Show element report different lengths
1 b# t. y- n$ O" c- K2 X5 B c! \823559 SIP_LAYOUT BGA_EDITOR When doing an Edit > BGA the tool will shift the BGA's position when at 90 or 270 rotation.
- w1 U( \; f: z: F. c' B' \/ R# I9 @823688 SCM SCHGEN Schgen changing the physicals bus name in the preserve mode for some of the bus
6 H( U" k, l9 o/ k823792 CIS OTHER Capture CIS performance over WAN for bulk operations are slow8 r& o+ ~; M* A1 j+ W6 ~6 W
, N7 Z2 S I% _7 l6 e0 FDATE: 09-10-2010 HOTFIX VERSION: 0169 d# R( J4 `% j# g
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CCRID PRODUCT PRODUCTLEVEL2 TITLE7 c9 _' H2 c& b+ I) }! e
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7 x7 y0 ]' w$ B0 Y L604662 VLS-L VIA When changing Rows/Columns values in Edit Via Properties form, different value are assigned.
% M' e* ^* L* H6 o1 _3 Z8 f# o) l. ]747191 PSPICE AA_SENS Pspice crashes when starting Advance Analysis' P8 V3 e$ O3 z* `! |$ i" x1 ~% A
756103 CONCEPT_HDL ARCHIVER Archiver does not include all the Parts when design blocks are copied from one location to another
( e2 r% f; _1 e3 W7 ~758487 APD 3D_VIEWER package substrate (BGA) outline should be on a separate layer, not on bottom conductor layer.
: b, A/ u) g' O9 w% I# I764417 APD EDIT_ETCH Routing with Diagonal entry (45 degree) to Constraint Regions does not work
: k8 n; j) U5 j! F( E/ Y6 k766409 PSPICE PROBE Copy to Clipboard changes the label text colors0 A2 F$ [3 q2 ^% I
784577 CONCEPT_HDL COMP_BROWSER SingleclickAdd 'true' places does not pick the correct version _, ]9 u V, c1 ~
784814 SIP_LAYOUT ASSY_RULE_CHECK accuracy of acute angle DRC
$ \1 O2 m" m6 F0 ?792039 CONSTRAINT_MGR OTHER Doing a File->Import->Worksheet Customization from Constraint Manager will change the working directory.
9 q4 F! M" m9 f7 i) r796517 CONCEPT_HDL COMP_BROWSER Component Browser showing wrong symbol' V9 |5 I9 a( l& S$ u0 P% c! N
801944 SCM UI SCM dropping terminators and pull-ups when renaming signals (copy - paste special)$ N8 `3 Z. M& d5 Y
804627 PSPICE PROBE Printet text labels have wrong location/ E. h% c+ `" S0 g; ^* p% F7 ]" @
810479 FSP DESIGN_SETTINGS Not able to connect some peripheral signals to FPGA manually, w9 z; [4 n6 R! t
810814 CONSTRAINT_MGR OTHER T-point does not create when import DCF file.2 z" a+ s4 a$ X3 l8 ~: R% x
811032 ALLEGRO_EDITOR EDIT_ETCH Enable enhanced pad entry to support pads as shapes
" `* D! g" o" i1 _1 V8 l8 M ~. M812643 SIP_FLOW CONSTRAINT_MGR Physical Constraint values disappear after entering constraint mode; E7 u1 s+ z0 r6 ]) P
812835 CONSTRAINT_MGR INTERACTIV CM Custom Fomula - "Analyze" on the header of Actual does not analyze pinpairs. w6 o* c) a+ J- e. b7 @
813435 SIP_LAYOUT DIE_ABSTRACT_IF Invalid parameter passed to ICP utility API
0 D; P! M2 ?* _- n; v; M814060 CONCEPT_HDL CORE Read only library becomes writeable when updated
" \. R) H% A8 t1 ?% f( A; F814347 ALLEGRO_EDITOR ARTWORK It seems like not work ”detailed text checking” on 16.3.
$ H" M4 @! R; @# N0 w3 t814451 ALLEGRO_EDITOR DATABASE Allegro get crash when run dbdoctor& l) T1 B3 C( M% j& {( Z
814496 CAPTURE ANNOTATE Lower level part refdes resets to ?% M/ i# g9 V$ j4 f
815150 SIP_RF OTHER sip layout export chips output is not correct
# D' U% N+ H ~/ T816034 ALLEGRO_EDITOR MANUFACT Backdrill Passes not work from bottom8 r' D4 Z1 Y7 v' M5 Z
816065 APD DATABASE Export Libraries with no library dependencies selected creates package symbol without pins.$ E8 j; j) f$ X3 n
816426 ALLEGRO_EDITOR SHAPE Dynamic shape not updated when component is unplaced
2 ]9 G. }- d4 y9 q- k/ C816616 SCM SYSTEM_OBJECT codesign incorrectly maps primary and secondary codesign object
* @+ f% T L! Z# o! y816686 ALLEGRO_EDITOR TESTPREP Probe Spacing rounds off 3 place decimal to 2 places9 U. B1 \' W; t4 J
816917 SIG_INTEGRITY LIBRARY Issue for loading interconn.iml u2 J: H+ C& f3 w& n: d
816986 ALLEGRO_EDITOR MANUFACT Mfg>NC>Backdrill analysis with passes set at Bottom layer is automatically switching to top, hence failing!" Y3 U# D: G% H& k: p8 c+ F( @$ D
817473 CAPTURE NETLIST_ALLEGRO Backslash (\) is considered as illegal character for netname but it was allow in SPB 16.30.010( r0 U& T9 b8 z
817606 SIP_LAYOUT WIREBOND When moving Bondfingers the Via's are sliding too when they should not.
: e! ?. p* K4 E: n) Z/ t+ [* w+ t3 s8 g7 P7 O. x* g4 E: m7 @ E
DATE: 08-27-2010 HOTFIX VERSION: 015
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5 O) {# ^6 ]: S: u. a9 mCCRID PRODUCT PRODUCTLEVEL2 TITLE- |$ v; a$ h& I5 p, R' K, ]2 p
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664821 CAPTURE NETLIST_ALLEGRO Improve error messages when netlister finds illegal characters in the pin names6 ]. F! n Y' E8 `0 ]9 f
753867 PCB_LIBRARIAN GRAPHICAL_EDITOR PDV crash when graphics from one symbol to another4 f# D8 L1 f/ m F
777559 CAPTURE OTHER Why the Reference designators get lost in project with external references.5 u B5 {9 U1 V: k
777657 CAPTURE PROJECT_MANAGER Archive Project causing Capture to crash
: R) u+ s2 D; h/ C3 r785748 SIG_INTEGRITY OTHER 16.3 SI model library path directives behave inconsistently if the ~pcbenv/env file is present7 p, B, f* |# |2 n/ L8 v# M
789529 ALLEGRO_EDITOR EDIT_ETCH Neck Gap changed to Primary Gap when executing Delay Tune command.
0 N7 d" [# A# R' T8 H! M/ L791853 SIP_LAYOUT EDIT_ETCH via slide clips to 45 angles near BGA) z1 F! N5 n# i' o' Q
796604 MODEL_INTEGRIT TRANSLATION ibis2signoise replace V_fixture_min with V_fixture_max based on the value.1 Y _% H( {! `% ]: h. ~' ?
797657 CONSTRAINT_MGR CONCEPT_HDL constraints from the brd file are not passed on to the schematic.
{$ ]4 z2 y! I802760 ALLEGRO_EDITOR NC nc route not generating the circle correctly
$ j! M( c! @+ N: q6 L2 X) E* E803572 MODEL_INTEGRIT TRANSLATION quad2signoise fail if MODEL name include backquote.9 O! H V# J6 V8 ]1 o
803869 SIG_EXPLORER OTHER Trace parameters form does not update with correct stackup data, H8 r: s( I6 D' d2 v- Z
804070 ALLEGRO_EDITOR SKILL The skill setting objects not match to all items in CM.7 c. Y( P* O) h8 Q
805641 ALLEGRO_EDITOR COLOR Clear all nets fails to remove the custom color on the Color Dialog form
p9 N' V: Q3 `5 Y- V3 [1 H) A5 V806115 PSPICE MODELEDITOR Cannot generate a Capture symbol from Model Editor because no Capture license.4 ^" O7 ?6 X& j% x
806196 CONSTRAINT_MGR OTHER Netrev fails with warnings.
8 h, R8 G& a# ~* w; K1 y7 G806864 CONSTRAINT_MGR CONCEPT_HDL "Selected nets/xnets only" option in CM connected to DE-HDL
: c, v$ W3 F, r( B807960 ALLEGRO_EDITOR COLOR Click OK to Color Dialog box and Shadow Mode ON/OFF setting will be lost.) w) m2 U; V# z% T" w
808155 F2B DESIGNVARI Variant Editor variant.lst and BOMCompare not the showing the same data
) n- D7 W3 v y5 U$ C! q3 A' i808392 SIG_INTEGRITY OTHER Cross section impedence not calculating for SPB 16.3 with single license for OrCAD PCB Editor. y3 ] r6 f! n' z
808978 CAPTURE STABILITY Unable to Place > OLE object > Visio drawing file. Capture crashes as well
8 g- w' T! i3 w809163 SCM PACKAGER scm crashing when running export physical8 G& ]( y5 O+ @3 p
809526 ALLEGRO_EDITOR DRC_CONSTR multi-thread DRC hangs when replacing padstacks' v7 x( Q% H) J/ I
809587 PCB_LIBRARIAN GRAPHICAL_EDITOR PDV crashes during Text Cut/Paste operation in Symbol Editor" j; o' c( Z! E" d9 d
809636 ALLEGRO_EDITOR DRC_CONSTR drc update reports incorrect DRC count when run after deleting unused region in constraint manager.4 Q3 q7 e7 I: Q; o1 ~5 v
809847 PCB_LIBRARIAN CORE "Auto add SWAP_INFO to chips" problem
$ I# b) H7 O9 K; m- o i* ?810024 ALLEGRO_EDITOR SKILL axlGRPDrwText does not work for left justification
, l1 u% k* Y" r1 [% D810530 ALLEGRO_EDITOR EDIT_ETCH Sliding vias on differential pair is not selecting both nets# l- p l2 N$ a _; J
810860 ALLEGRO_EDITOR DRC_CONSTR Improve Update DRC efficiency
0 |1 v8 V- S% t5 c" s* H811506 CIS ICA Using Capture V16.3 ISR0013 “Save Schematic Part” option is missing in "New Database Part Wizard".
% `1 X3 L1 S5 ^7 s812259 ALLEGRO_EDITOR SCHEM_FTB scm crashing when running export physical- AGAIN) L7 ]8 x* p: `( k) {# _' X* K
812269 APD WIREBOND Wire diameter and wire profile automatically is changed when executing wirebond add command* o4 I! \7 y, j/ p' @/ f
812597 PSPICE SIMULATOR Pspice crash.
/ R! E( v4 i6 l, \: D% C) [6 i! Z812655 SIP_LAYOUT IMPORT_DATA Importing Stream data multiple times into a .dra will have inconsistent results, each import is different.
. G F& S/ K' m: C t813253 ALLEGRO_EDITOR DRAFTING Datum Dimensioning Crashing Allegro# v' ]( ~( H* h5 x6 p
813265 APD WIREBOND Wire Bond Report fails with wires present that were added with the "Add/Edit Non standard" option.7 W0 @( b8 S' O& w6 Y5 ~: j
8 T2 ]. F( m1 Z6 l; bDATE: 08-13-2010 HOTFIX VERSION: 014
- M# c: x6 |/ w0 [7 K# ?0 c===================================================================================================================================
. C9 d; `: }5 ECCRID PRODUCT PRODUCTLEVEL2 TITLE$ y5 Q0 R% r# O6 l, y: Y7 Z
===================================================================================================================================- U% A1 p* @4 W2 l
792354 CONCEPT_HDL CONSTRAINT_MGR Viewing a second net in SigXP from Design Entry HDL constraint manager generates an error( _' |( J( ?# {2 j7 p* N' ^! o
800336 GRE CORE GRE's Plan Spatial crashes Allegro.
( ?9 M& I+ t+ v/ O+ f801116 SIP_LAYOUT WIREBOND Wirebond -> change characteristics with only wires selected should not modify connected fingers' placement at all.
& [2 q+ F8 f: {5 h1 Q- b801463 ALLEGRO_EDITOR EDIT_ETCH The Allegro axlShoveItems SKILL function behaves differently in 16.3 than it does in 16.2.
7 z: K# ~5 x/ j803049 MODEL_INTEGRIT TRANSLATION quad2signoise cannot translate OpenDrain Model correctly.4 E6 ]' U, M" z7 _
803878 ALLEGRO_EDITOR DRC_CONSTR 'Via_At_Smd_Fit' not working correctly when the via fully covers the pin.
1 ~! U8 n5 o( |' Z804273 ALLEGRO_EDITOR DATABASE Running update DRC gives different number of DRC.
6 U; B1 m: z& g/ e804330 F2B PACKAGERXL Packager is changing the refdes in preserve mode for components in hierarchical block- {% O, z! d' N3 u
805335 F2B PACKAGERXL Packager fails reporting empty location values when the location values do exist
7 [% F6 t H( @, i2 x5 o! G805676 ALLEGRO_EDITOR DRC_CONSTR Update DRC hangs while updating differential pair checks with dynamic* g0 C3 Z' }7 e! q- p6 E8 H
805747 SIP_LAYOUT EXTRACT Extracta crashes with this testcase and command file.
! i) O' Z ?% c806028 ALLEGRO_EDITOR TESTPREP Allegro testprep parameters causes crash6 M/ v* }9 O; U
806120 PSPICE NETLISTER “Enable PSpice AA Support for legacy" option results to undefined errors$ x, v& f) \: Y$ q
806182 ALLEGRO_EDITOR SKILL axlPolyFromDB will crash if object is a pin on an unplaced component
M! Z6 J6 \ A8 C) G807543 ALLEGRO_EDITOR DRC_CONSTR Via at SMD Thru DRC not working correctly in Solaris
^% o1 b( S% @+ {' p n0 @808047 SCM SETUP scm not loading all parts from pcb after running brd2asa
3 `9 w7 g. ^9 h, c: }808831 ALLEGRO_EDITOR DRAFTING "Oops" command(in dimension angular command) crashes Allegro.
' P! h$ a# K7 ]' I/ I2 w8 p9 J
7 g- x C8 |" P9 kDATE: 07-31-2010 HOTFIX VERSION: 013: o# w h' e6 u6 w6 g" G
===================================================================================================================================
5 C' N; b1 f Q9 P9 a: v7 oCCRID PRODUCT PRODUCTLEVEL2 TITLE
# q+ R, l8 q C, c, ]1 c: p===================================================================================================================================
( D+ O0 y& H3 H' D. V7 z! m( O576133 CAPTURE ANNOTATE Annotations in the design getting reset to ?
9 W+ F& u- w, E L688692 CONCEPT_HDL GLOBALCHANGE Global Change does not respond to RMB> Done
- @8 n8 I6 F! x& }731045 CIS EXPLORER Double click in CIS explorer places two components" D) B3 A4 J1 G! D$ d$ i/ n" U
763550 CONCEPT_HDL SKILL nconcepthdl in 16.3 no longer recognizes skill functions that worked in 16.2( D7 }3 B$ `. Y' ^7 J, `9 n
764130 CONSTRAINT_MGR OTHER Export Excel from CM hangs/crashes Allegro on attached design
+ | N3 ^3 I& G0 K' J) P( d766750 ALLEGRO_EDITOR INTERACTIV Request to enable datatips when constraint manager is open and a command is active$ z2 L! m8 d+ r6 h3 G1 ^) d4 ]3 f+ ]
774466 CAPTURE CORRUPT_DESIGN DSM0008 - Unable to open design in 16.3
, ?, g3 O! ?' e5 M777862 CIS PLACE_DATABASE_P Absolute path in field Schematic_Path causing incorrect display property9 N: J! N1 O0 T9 P( Z
782370 CONCEPT_HDL OTHER CreferHDL $XR hyperlinks do not work in PDF Publisher - they did in SPB16.2
5 ^4 A% D2 C9 F( o783036 SIG_INTEGRITY SIGNOISE Problem for Waveform saving with -w option in signoise command.
; m. l6 g" ~& V e6 I8 d5 D8 I784205 CONCEPT_HDL CORE Schematic block generated from SCM needs to have DIFFERENTIAL_PAIR property on the ports
2 y; o! ?1 t% g786387 CAPTURE OTHER Update cache does not update the parts on schematic( ^6 Q# p5 x& T+ F$ o4 [5 v) b/ K
786560 CAPTURE NETLISTS Sqare bracket [] is not allowed in PADS netlist.0 v4 x9 W: n& d8 b* K
786808 SIG_EXPLORER OTHER RMB > Via_Model_Name doesn't display the generation param of the via.6 w' X9 D6 l$ L. Q# o
787414 CAPTURE PROPERTY_EDITOR Part value can’t be moved on schematic if a part has been copied to a new design and not saved yet.+ w0 [4 p( t/ f! I' B
791965 CONCEPT_HDL CORE group move should not snap to center of group
0 ~3 z9 l7 P- Q+ d: d792126 CAPTURE PROPERTY_EDITOR Attempt to change display for occ prop resets& {' ?9 \7 a7 u
794900 CAPTURE NETLISTS Attached design is not getting netlisted in V16.3. It works fine in V16.26 ?1 b2 c* V* J; T* G: g
795914 PSPICE SIMULATOR Getting RPC Server Unavailable Error; t7 H! O F) ?! J) h1 F. A
795997 ALLEGRO_EDITOR TECHFILE crash when importing dcf file
# s7 r. {# L# Y/ w796124 CONCEPT_HDL CORE Messages overflow console& x9 \" _8 Z. X' x
796168 CONSTRAINT_MGR CONCEPT_HDL Create ECSet in DEHDL CM moves focus to DEHDL
4 K4 x2 {) q1 t8 F5 g( a' D# J796378 ALLEGRO_EDITOR PADS_IN Pads_in has error while translating PADS 2007 asc file
6 j, k- c5 o# [5 h! Z* p796658 APD OTHER Allegro can not import the property section of 3rd party netlist correctly.8 O; h1 u ~. t# I0 s
796926 CONSTRAINT_MGR OTHER Importing Custom Worksheet file does not overwrite the Description field.; s0 n- y7 t) e# Z6 ~ y6 E
797387 SCM SCHGEN Increasing the grid units from 25 to 100 breaks the bus into bits on the generated schematic.8 b" @0 g' G# g2 T+ j1 h
797529 SIP_LAYOUT IMPORT_DATA import BRD to SIP fails if database has partitions. even if only silkscreen and documentation exist0 K) \- P1 F$ B9 p3 w, K
797634 SIP_LAYOUT DIE_EDITOR rat control buttons in edit die mode are invisible until user selects an action
4 T, `/ j+ T( P: K797663 SIG_EXPLORER OTHER Current probe could not get from sigxp left symbol panel.) B! b1 e/ k. `$ b
798118 SCM REPORTS SCM report not resolved with CCR 6977096 W- y+ v, Q( E; u
798464 ALLEGRO_EDITOR SKILL axlDetailLoad not filling shapes in 16.3 s108 M# b; \* w; Z4 R v
798980 ALLEGRO_EDITOR DATABASE Unable to open board file as it fails with a error message Found bad data pointer, run dbdoctor.
( _6 L# D; d3 M1 ^2 w) ]1 t799445 PSPICE MAG_DESIGNER Magnetic Parts Editor crashes while saving newly created Magnetic component; y% m. y# t- m5 y2 ?' P+ G: j
799539 CONCEPT_HDL COMP_BROWSER PPT Options settings lost when cancel done in PPT Options form
8 l, p: a* H* T5 ?799957 CAPTURE CORRUPT_DESIGN Capture crashes while doing save as in 16.3
m9 \% }5 b3 C' A0 ^3 n$ c800280 SIP_LAYOUT WIREBOND Swappoing Dies in the die Stack will cause the bondfingers to move and create DRCs
! k" g# ?0 e2 x( d/ R1 E) h800542 POWER_INTEGRIT SIMULATION Multi Node Simulation does show actuall waveform2 e+ u$ S2 K" v/ t4 w; e
800695 CONCEPT_HDL CORE Genview changed behavior in 16.3 HF 11 breaking the design hierarchy
8 k" c- N* X( o7 ~' A" t5 D# _800751 ALLEGRO_EDITOR DFA DFA placement does not understand package keepout
% c" F/ u; _- U" @/ o$ P5 T( Y801017 ALLEGRO_EDITOR REPORTS APD Crash when creating Unused BB Via Report9 }& d6 W! J$ _1 }* l1 ^# i
801043 SIG_INTEGRITY OTHER SigNoise Case Update seems to check ActiveDesignLink value incorrectly.% P' \5 }9 b3 |- O6 e8 Y& z
801433 ALLEGRO_EDITOR MODULES selected figures do not end up in the module
2 f) v5 J4 {9 b% l801705 ALLEGRO_EDITOR SYMBOL Shape symbol was specified with RegularPAD of the PAD stack become "Null".
0 ]4 Y. N4 a: v3 B! G" a802319 ALLEGRO_EDITOR SHAPE Shape status cannot be changed to smooth using suppress pads.
& @; G- Z, [& U9 ?' M9 A802474 CONCEPT_HDL LWB-HDL Testbench generator not working in Linux0 v5 M: h# ]2 G9 |
802887 ALLEGRO_EDITOR OTHER Adding the No_Shape_Connect property to via causes the application to crash.
& {" U! ]9 l/ q$ L+ H803393 SIP_LAYOUT DXF_IF Cannot generate a dxf file
( M" a4 s1 T8 g- R$ ]/ [) A, N0 G1 C5 z
DATE: 07-16-2010 HOTFIX VERSION: 012
7 m* n2 Z: H# U+ ]9 b6 ]" L" U% L===================================================================================================================================
0 `8 O+ q! C2 \. h! L( U* t) V) ZCCRID PRODUCT PRODUCTLEVEL2 TITLE5 I W4 |, ~% T$ c( [1 ~* N
===================================================================================================================================
0 i( S. @# i- \( `$ t757157 CONCEPT_HDL CORE Zoom (using SHIFT + mouse wheel) to work such that the tool zooms based on cursor location
7 f' J6 ]* G1 ]* O5 k& m766639 ALLEGRO_EDITOR EDIT_ETCH via structure disappearing after selecting place manual hide icon.
( c* l. o: K' W& a4 Z770910 PSPICE PROBE Printing from probe yields text label with too small size
/ [4 }/ ]/ }! e$ v0 k773603 SIG_INTEGRITY SIMULATION The characteristic of S-parameter model is different.
. y/ {$ {. Z/ ?( x, d' r774363 CONCEPT_HDL CORE hier_write didn't report error.6 B, r' y( L4 B7 C4 _
776991 CONCEPT_HDL CORE The Wire> Bus Name command does not use the Net Name font setting
$ y4 m- @9 l' z' m. j9 k0 f% \781965 PSPICE PROBE Unable to add trace expression with small letters; D, S- ~- t, E# f- J0 A2 c% a0 r
782847 SCM PACKAGER PKG-10002 - Cannot associate a logical part from chips.prt
. C+ B: c5 X0 m4 Y783245 SIG_EXPLORER EXTRACTTOP extracting net with trace on plane layer giving unconnected topology
6 F, s5 n8 s% _* \: Z: H785320 LAYOUT TRANSLATORS L2A translation fails with error "output directory is not writable".8 t8 `4 x4 S+ K9 |/ N: \8 O
785401 SIG_INTEGRITY OTHER The "View Geometry" or sigxsect command is not working in SQ 16.2
) P% T. F- C7 o y) z( p785715 ALLEGRO_EDITOR PADS_IN PADS_IN fails to convert some components on Bottom Layer and adds two components at same location
5 M' M: H* ^( ^7 s( a785868 SIG_INTEGRITY OTHER Unable to generate Parallelism report as the report seems to have hung the SQ Session.
1 ]$ f; L% ^/ \' k1 q788523 CONCEPT_HDL CORE selecting QuickPick toolbar button should not reset canvas zoom( F/ i! e0 l( d: t/ C
789333 CONCEPT_HDL CORE Font colors not being used as set in the SITE .cpm file
2 x6 b8 U/ b( H789348 ALLEGRO_EDITOR EDIT_ETCH Via Structures removed from database when switching to any App mode from Placement App mode* C- u4 p' M5 t9 f% B- S5 L
789473 SIG_INTEGRITY OTHER Via delay is not included when t-point is at the via! z! m! x* v' E! H
789744 ALLEGRO_EDITOR SHAPE Update Symbol with cline at symbol level do not connect clines properly
* B8 _1 Y. z/ Y9 m$ k2 s6 I: Z790170 F2B DESIGNVARI Function of Variant Editor and Annotate schematics
: V& l9 g9 l f: x# M, L790811 APD ARTWORK Some Void shifts by the artwork output.
8 i7 y9 E9 G9 Z M8 `& V791371 ALLEGRO_EDITOR REPORTS Dangling line with cpoint not reported in the dangling lines report.7 |. \& G* D' E$ A4 z. N+ J
791486 CAPTURE PLUGIN_INTFACE Unable to open a PSpice Project by double clicking the .opj file, if Capture is already open
, F9 d( D+ F/ W* b791663 CIS RELATIONAL_DB Relational view doesn't appear when capture opens second time, B! }! r' {. L0 |
791690 ALLEGRO_EDITOR EDIT_ETCH etch editing/routing in placement mode, allegro looks for all libraries adding delay in routing.
* e. m4 i3 |8 B: M! d5 Y791720 ALLEGRO_EDITOR DATABASE Color Net param file does not have some nets with special characters in the Net name.8 j' e, B5 c4 x8 V
791987 ALLEGRO_EDITOR PADS_IN PADS Translation fails with no error message3 G2 n# X9 p* L' @" K' l
792232 ALLEGRO_VIEWER OTHER Import parameters not bringing in plane colors in allegro viewer4 d- e8 m- y- \# D( O
792559 ALLEGRO_EDITOR DATABASE Error when executing refresh symbol command# f4 X$ R6 F0 S( Q& }; S0 @
792923 ALLEGRO_EDITOR OTHER sted fails Can't open STED stroke file ~pcbenv/allegro.strokes+ U- m8 A d( B+ c5 n
793358 SPECCTRA PARSER When I try to invoke Allegro PCB Router it fails to invoke with errors./ O6 f" n2 o# I0 \- _' q
793605 CONSTRAINT_MGR OTHER Importing custom consmgr.wcf file crashes Allegro.
/ M3 V1 R: e- d0 J793955 ALLEGRO_EDITOR DRC_CONSTR add connect launch signoise even so electrical drc are all at off8 B% f# o& T; y+ i1 O
794748 LAYOUT TRANSLATORS import fails with message not valid Allegro subcls) W- U( ^2 M5 t; z0 E$ J, B# ^
794775 ALLEGRO_EDITOR SCHEM_FTB Import logic runs forever or get a netrev error without any explanation
8 c* D$ x8 I/ I, f795261 CAPTURE NETLISTS Create netlist hangs in SPB16.3$ h' w8 r9 [- Y5 N- @
795364 CONSTRAINT_MGR OTHER bookmarks are not getting saved in CM
8 q+ ], S# f$ V795410 APD BGA_EDITOR Using the Edit > BGA tool I cannot get it to modify the pin numbering of a BGA
0 c# n3 a1 S$ K) T8 Q795501 PSPICE PROBE Unable to see the Multiple Mark-Labels in Probe
2 o6 p' B+ U# e$ X/ C795761 ALLEGRO_EDITOR DRC_CONSTR Design is crashing while executing Tools > Update DRC
5 s7 |" |/ l; \9 B8 U! A795770 ALLEGRO_EDITOR DATABASE void moves when upreving from 15.7 to 16.3
6 D0 I' e& n( W" l796026 CONCEPT_HDL CHECKPLUS CheckPlus reports text overlaps inccorectly on Linux% ^5 b8 z: x; j- T
796092 MODEL_INTEGRIT TRANSLATION ibis2signoise crash if Submodel section exist next to Component section.9 q# Q7 a+ I! @* V W! l
796361 SIG_EXPLORER OTHER When dml file is loaded "Illegal format in device file" is outputted.) N- V" Y, M( Q( Q0 W8 L' ^
796366 CONCEPT_HDL CORE UI windows in DEHDL are scattered" d, [( h* m- q1 S+ L
796590 APD DRC_CONSTRAINTS CM Hole Spacing rule always set to 1905 in a new design.9 _4 }; \7 o) m7 b& j
796858 ALLEGRO_EDITOR DATABASE Deleting layers that has only vias moves etch from other layer on it and prevents the layer from being deleted.
# J6 C6 f# P# t& L2 {, [) x8 u3 V) u' i1 L4 m* J
DATE: 06-25-2010 HOTFIX VERSION: 011
( t6 p1 b& T9 g7 F===================================================================================================================================2 h4 j1 l. E5 s' O8 g5 l- i$ O
CCRID PRODUCT PRODUCTLEVEL2 TITLE8 k5 Z, l7 w+ T* e5 M6 {
===================================================================================================================================
) }5 ^: I# T- U: v6 M644128 ALLEGRO_EDITOR MANUFACT Enhance Backdrill for HDI Buried Vias7 {6 R, ^8 g$ o6 n! B0 R4 U7 y3 W
743746 ALLEGRO_EDITOR MANUFACT Sub-laminate back drilling -Arbitrary from-to layer drill capability needed
$ w( B, B. E! `0 @8 y0 z% w773066 CAPTURE EDIF PinSwap information written in EDIF does not back to Capture schematic- u3 o7 S* g# o- r
775690 CAPTURE STABILITY Design is not properly translated in 16.3
0 `' M }; H& `782854 ALLEGRO_EDITOR COLOR Component Keep Out for the Top & Bottom layers not showin in the Color Dialog box, only ALL shows.
) \. r" N3 b/ i* u8 c784439 SIG_INTEGRITY OTHER CM of 16.2 recognizes the differential pair nets as Xnet.7 K& n1 Z5 ?2 w3 s8 R$ x' n
785135 CONCEPT_HDL CONSTRAINT_MGR Applying an ECSet to a diff pair crashes Constraint Manager
. k1 U0 e' l0 I( P$ E O( R785179 SCM OTHER Changing a differential interface signal to local corrupts the con file and ASA is not able to load P. h L" ^" c; O
785332 SIP_LAYOUT LEFDEF_IF unable to def in to sip layout
. C1 Y R/ N0 |0 f4 U785423 SCM SCHGEN Schematic having incorrect connectivity
: j& a5 V. G! L4 p# O" Q& i786858 SIG_INTEGRITY SIGWAVE want to select license at launching sigwave
D# z. L. w1 J/ L786871 ALLEGRO_EDITOR SHAPE Allegro dynamic shape not updating
& w- ?/ m# p$ Z$ O786957 CAPTURE MACRO If an off page connector is renamed using macro the net name attached to it is not getting changed6 A" i% f; @1 b/ O; y: z
787003 CONCEPT_HDL CONSTRAINT_MGR olecs crash in CM when rename librray defined diffpairs on this design.
0 i4 W- `) u, S) U6 v6 }5 R% }787087 ALLEGRO_EDITOR DRC_CONSTR Diff pair Static Phase tolerance Error
7 y( d9 |* \2 r3 b787174 ALLEGRO_EDITOR MANUFACT Reading filmsetup.txt file crashes Allegro
K& G3 b; s4 p788521 ALLEGRO_EDITOR DRC_CONSTR There is a difference of DRC between SPB16.2 and SPB16.3.
* A+ U' s7 o* \- h# g% e& K' p788652 F2B DESIGNVARI Variant Editor cross highlights incorrectly to Concept
7 ~3 j4 r1 P6 y788658 CAPTURE NETLIST_OTHER OrIntegra.dll netlist has inconsistent behavior
! D r! \6 e# d0 J# Y788718 ALLEGRO_EDITOR DATABASE Board crashes upon deleting Cline segments within BGA using Allegro PCB Design XL License.
: w7 A0 M& X. d" U, ]) c789206 ALLEGRO_EDITOR SYMBOL Merge shape option causes attached *.dra file to crash
; w% X) G7 o) ?789324 CONCEPT_HDL CHECKPLUS CheckPlus output producing wrong values! n! G1 s$ u- Z) k8 e E8 Z0 y
790049 SIP_LAYOUT EXPORT_DATA Offset wire tack points disables wire in AIF Output
: F, r; d7 f/ b, w* e790503 ALLEGRO_EDITOR SHAPE Shape Void not correct
2 K+ ?( B& b4 J# L) a& S9 X790567 SIP_LAYOUT TILING unable to run the ndw tile die generator
; C% C5 L6 G7 h1 |+ d/ r790622 ALLEGRO_EDITOR SKILL line width of internal segments within hatched shapes not correct when created using SKILL
. N. O( L# R& e6 \; E% b" B791075 SIP_LAYOUT EXPORT_DATA The shape that connects Merged Bond Fingers is missing in the DXF output.
$ C3 S0 S* _' [
& X ?$ T$ G8 e& J! p2 J/ c9 Y- wDATE: 06-11-2010 HOTFIX VERSION: 010( d( t. t. @' q4 S& l/ g7 f
===================================================================================================================================9 B& S% w% b9 i9 O( Q
CCRID PRODUCT PRODUCTLEVEL2 TITLE& ], C" V$ p" }4 W
===================================================================================================================================* d; l/ V" K) f+ R
701724 CONCEPT_HDL CORE Page Down (PgDn key) Key is unresponsive
t8 p2 o' ?( r' y6 Q722773 ALLEGRO_EDITOR DATABASE How can i add DUMMY NETS to a Net Class ?2 t) o* i% a* Z. s
767874 ALLEGRO_EDITOR OTHER Component Geometry/Pin number not imported.6 z4 h2 y6 K& x* V/ r
769644 ALLEGRO_EDITOR SCRIPTS Why Command line script in non graphical mode prints everything to the screen when working with Windows?1 j' m: T# C! }3 H: X9 w
778086 SIG_INTEGRITY SIMULATION extracted net yields unrealistic resuts +/- 100v swings! ~0 q2 [8 q2 x1 I! v$ M3 x
778915 ALLEGRO_EDITOR OTHER Export library dumps symbols with mechanical pins instead of connect pins# N& _: }( s0 s5 t4 X" F
779119 PSPICE ENVIRONMENT MC Analysis does not seem to honor Custom Distribution8 v/ {+ o5 L+ W: t9 _2 S( V
779161 ALLEGRO_EDITOR OTHER Getting error-"illegal arguments passed to a dba routine" when connecting CLine to via% X- p1 [" k# v3 p9 b! {
779335 SIG_INTEGRITY SIMULATION HSPICE sim from PCB SI caused netlist error.0 C/ b; u! W# ]( J: ~% @( r
780314 SCM UI ASA crashes on paste special./ s! o; i& V ^6 ?7 j
780345 CONCEPT_HDL CORE Pins look garbled when part is vertically mirrored
5 G, P- h0 r+ p9 I' p780811 ALLEGRO_EDITOR SKILL Request 1k limit of SKILL API be removed.
9 Y6 S. o3 S$ L4 U2 t% ?4 y4 [5 S781111 SIP_LAYOUT IMPORT_DATA Import Brd to SiP failed8 [$ w7 k0 U/ w. G# S
781259 CONSTRAINT_MGR TECHFILE Import tech file crashes Allegro
6 `* q9 [. D, @$ Q8 Y781287 ALLEGRO_EDITOR DATABASE dbdoctor removes tespoints from odd angle clines leaving V/L drc
; Y( ?; E8 w$ Y+ J. {4 A6 v" T+ Y781331 ALLEGRO_EDITOR SCRIPTS Script executed by command redirection operators is giving different o/p for v16.01 and 16.3
! Y, T K1 G0 h& H0 O, r2 F% l& l* Y781647 ALLEGRO_EDITOR MENTOR mbs2brd is defining extra additional testpoint that is not present in Mentor database7 D, i1 }; p/ r* h# ?( f) K
781650 ALLEGRO_EDITOR DRC_CONSTR Update DRC hangs while updating differential pair checks with dynamic phase tolerance added from the logic import
) Y3 d8 Z( m# R, v. x3 T3 O- R781665 PSPICE DEHDL_NETLISTER Error simulating delay component5 J9 }. S3 J6 `. h, {$ X! j
781688 CONSTRAINT_MGR ANALYSIS Application hangs on Solaris when executing DRC update" v3 z6 {# s _- r1 d+ U( _3 B
781799 ALLEGRO_EDITOR OTHER Unexpected results when exporting and importing text parameters6 I/ J* j$ M3 i
781922 ALLEGRO_EDITOR SHAPE Pin doesn't connect as a thermal.
' C7 G3 y5 f1 U782124 CAPTURE PLUGIN_INTFACE Bias point display not getting updated for projects on network
0 n1 n+ ^+ T! ^) ?/ w- Q782415 SPIF OTHER File > Export > Router takes 5 hours to create a .dsn in windows....1.25 hours in Linux." u2 Z+ H" A# a: B2 L3 x- R
782566 ALLEGRO_EDITOR PLOTTING It seems like not work PLOT parameter "Auto Center" on tight paper size.1 ^4 Y' J& G+ ?9 W+ V
782628 SCM NETLISTER Connection change not updated in the Verilog Netlist
+ h2 L3 R& }6 g( f/ T {1 l783059 ALLEGRO_EDITOR DRAFTING Create Detail with "filled pads disabled" doesn't work with irregular shape pad.
- V0 k: C/ s. K+ ?5 ?$ d V783142 SIP_LAYOUT IMPORT_DATA import bga text in on connector crashing sip layout" V5 N5 S8 ^( I8 {0 ~
783222 FLOWS PROJMGR Edit Physical and Spacing constraints
5 E) F" U- a% S0 |- I783241 ALLEGRO_EDITOR PAD_EDITOR Pad Designer hangs when attempting to save to file.
% k; @# p! D7 Y" z' L, _) L" x783283 SCM IMPORTS scm crashing with import physical: c% t1 b: ?+ D' w8 f& c* X
783301 SIP_LAYOUT WIREBOND All Bondfingers not sliding along path.
# S z; Z) `0 K. g7 t783496 ALLEGRO_EDITOR MODULES Problem of module placement.
$ j9 p0 G5 m& S; Z1 ?783813 SIP_LAYOUT BGA_GENERATOR Request to add new JEDEC BGA sizes to the BGA wizards standard JEDEC pulldown menu.
0 q, h, |; u& N% P M784441 APD OTHER Users cannot delete layer even everything was deleted
# L8 r+ B( \( E- ^+ R3 r784639 ALLEGRO_EDITOR DATABASE both dbdoctor and allegro are crashing while opening this database
4 Q' H/ s* p5 U" I* [7 Z* z785100 CONCEPT_HDL CREFER Cross Referencer must not call Unix command on Windows platform
; C5 v" B# y) z8 g0 ^4 g785385 ALLEGRO_EDITOR MANUFACT Allegro Crashes when using Datum Dim with Shapes.
! F, Y: q. z: x3 v) f4 v
/ q C) Q& O" z" C5 fDATE: 05-28-2010 HOTFIX VERSION: 009
5 j" ]- c+ ^ D, F' J===================================================================================================================================
6 x! k& D+ o3 U! \) j$ UCCRID PRODUCT PRODUCTLEVEL2 TITLE
! P, M0 B9 i. r% b% m===================================================================================================================================
% y( I/ @% U7 N- z8 L8 Y; l& D758913 APD OTHER uncheck default check buttons through options/preferences0 h( b+ z; ~: z# q8 v8 L5 e
763566 PCB_LIBRARIAN PTF_EDITOR The ptf command in batch mode always returns "abort"# ^; b: {" Z6 e' K2 c+ ?5 [
763662 ALLEGRO_EDITOR INTERACTIV Place replicate update creates numerous DRC on win platform
* O( N* b) N6 w9 Z5 q, O771088 CONCEPT_HDL COMP_BROWSER QuickPick adds incorrect property value when ppt optionset file is used0 S( e# Q! v$ P- H) F
772285 MODEL_INTEGRIT GUI Model contains recursive calls fater port rename reorder funtion is performed on it.
6 R7 {' V/ O8 v774070 ALLEGRO_EDITOR DRC_CONSTR Allegro crash when sliding connections.* I/ _6 r4 [! \1 L( k a$ S. Q
774880 ALLEGRO_EDITOR INTERACTIV Place replicate stops with No available buffer identifiers.& b+ V0 m4 L; Y; e. B
775443 APD EDIT_ETCH The routing of DIff Pairs when transitioning from a region needs to be smoother.
) r' d; S! o1 q* }4 N776022 ALLEGRO_EDITOR INTERACTIV Allegro crashes when we use Ctrl+Click in Etch Edit mode for selecting a Cline Segment in Allegro PCB Design L: ?# r0 L5 f9 e0 b {. z& ? [
776151 ALLEGRO_EDITOR REPORTS Shape report incorrectly lists thermal connections for SMD,Via and Through all as Through.( J0 n! x- }+ P0 F
776190 ALLEGRO_EDITOR INTERACTIV place replicate crash; select polygon zoom points
5 \9 T/ h L, F) _7 M% w& z776284 PSPICE STABILITY 16.3 design crash while simulating the design
, {# t3 B2 J! V6 M- H. e777556 SPECCTRA CHECK interlayer clearance output drc even so layers are separated by a power layer
+ t$ `# D. Y+ L: p2 A5 z" u777689 ALLEGRO_EDITOR SHAPE Shape do not void if Curved Fillets are used- q6 M. O1 W/ _9 w! V/ _( y
777698 CIS RELATIONAL_DB CIS 16.3 ISR s007 - Relational feature doesn't work3 Y* C7 R" W, d. @3 E: y- C
778042 CAPTURE PRINT/PLOT/OUTPU Some text are not searchable in Capture generated pdf: h/ V0 X6 x4 W J+ h1 }
778350 ALLEGRO_EDITOR SHAPE Multiple Drill on pad gets round void instead of rectangular
! T* g" E6 {5 {: P778356 ALLEGRO_EDITOR SKILL Duplicate Vias with axlDBCreateModuleDef
" t* S7 C0 |1 U* z& Z778782 ALLEGRO_EDITOR OTHER Display-measure and axlAirGap incorrectly report no air gap for multiple drill pin |0 a$ s% y" p3 m! o# B
779146 ALLEGRO_EDITOR OTHER Moving component crashes Allegro9 a& d: l- |0 T
780213 ALLEGRO_EDITOR DATABASE Design saved in GXL when opened in XL gives misleading message.
6 [' ^, M0 ?3 w+ H% I' L9 {2 u, f780773 ALLEGRO_EDITOR SHAPE No DRC displayed when Place Bounds are edge to edge$ u2 J4 G F" `
/ z7 E, P3 @: Z) c& t/ ~ H6 ~DATE: 05-14-2010 HOTFIX VERSION: 008
f/ [1 D8 Y# p7 J9 H! b===================================================================================================================================' b: E! Q' ?0 t( v+ i
CCRID PRODUCT PRODUCTLEVEL2 TITLE. f7 k( Z L* h, g4 y x. `
===================================================================================================================================
; l: F$ O9 f5 v& p. `1 O1 H* _# J697699 CONCEPT_HDL HDLDIRECT SCM Verilog output contains the line “defparam <instance number>.SIZE
2 D* }' E! L/ u* }734169 ALLEGRO_EDITOR PLACEMENT Wildcard asterisk character giving "illegal char(s) in refdes entry." error in quickplace. I/ ^6 Z3 p, A1 d
738970 SIG_INTEGRITY GEOMETRY_EXTRACT power bus issue with SSN simulation when device is on bottom
7 A/ K: ?8 Z( t: ^" p. u# C744762 CONCEPT_HDL OTHER Connection dot sizes do not match on printout vs. screen( v2 d( j7 r' K$ R2 ]) ~
750371 MODEL_INTEGRIT GUI Model name in physical view cann't match the model in right workspace3 R& H4 T2 i7 W7 F" V" b
757024 CAPTURE STABILITY Capture crashes while exporting to EDIF4 k! p3 _- P8 {0 m4 \$ y! A7 f
759094 CONSTRAINT_MGR INTERACTIV One member of a diff pair will show Analysis Failed when analyzing the design." e' R8 W% Z& m5 l0 q
760178 ALLEGRO_EDITOR EXTRACT Crash Allegro when executing extracta command for big size design(size of .brd
2 Y0 \, G2 D/ k. N* I- I; K( h- P761391 SIG_EXPLORER OTHER Incorrect rise time
1 M! ?9 p u9 w2 ?" N) I- W3 R762402 ALLEGRO_EDITOR MANUFACT When photoplot(RS274X) of MM unit was loaded, shape was broken.
2 @% @! k- t4 J4 ]762783 SIG_EXPLORER INTERACTIV sigxp - coupled tline on stackup layer should show solved impedance
* ~( ~ s! e* _) @& ^763150 ALLEGRO_EDITOR OTHER Request - IPC356 output truncate the padstack size to fit into the columns 59-62 and 64-67
b }6 u/ |( e, f- s3 j763556 SIP_LAYOUT ASSY_RULE_CHECK Assembly Rules Checker is displaying an array of confusing DRC's on a Soldermask shape.
3 X2 l' g4 e/ ^8 P( H/ V764399 SPECCTRA ROUTE Manually routed trace in Allegro are ripped OFF after routing in SPECCTRA using Route > Route Editor.; r! B2 s3 Y% K9 A8 e
764475 SIG_EXPLORER INTERACTIV topologies from earlier versions cannot be opened in 16.2 on a machine
- M5 [+ W2 Q/ G4 k5 x- o765287 ALLEGRO_EDITOR PAD_EDITOR attempting to open padstack fails with - database has a non-recoverable corruption.$ o6 r8 k5 Q1 _2 u' n1 S; K7 f
766041 ALLEGRO_EDITOR OTHER Auto B/B via generator incorrectly defines some BB vias
$ M; [9 k B O- }8 y1 S% @3 F6 Y766153 ALLEGRO_EDITOR SKILL Allegro crashes when trying to extract padstack information! F5 V3 d! M; D( ]- w! S
766611 ALLEGRO_EDITOR EDIT_ETCH slide creates DRCs in ARK area, N# T6 e6 Y0 l9 R, y
767041 CONCEPT_HDL CORE The tap command failed because the specified tap body CTAP is invalid
. k/ K% N$ j R& F767146 FLOWS PROJMGR Project manager open last open .cpm in 15.7 version not in 16.3
& @" o- H" h! V: a8 D" b1 {& k- t767526 FLOWS PROJMGR Project Manager customization does not work
: o$ ?- r8 Y3 T0 |767671 APD DATABASE Crash creating cline with axlDBCreatePath() on this database.
$ R) ^2 E# G6 u% _* x3 U$ v767951 ALLEGRO_EDITOR DATABASE color net param file omits nets with bus brackets in the name! ~" u: G; K5 Y: r* k+ m
768168 CONCEPT_HDL CORE Fontsize on instances changes when doing backannotation
% p& I9 `7 L5 ^$ `/ B) t6 m# _768207 CAPTURE STABILITY Capture crash while editing properties0 b [$ X ?. m% U' q% A
768734 CAPTURE PROPERTY_EDITOR Properties of title block are not getting editted through spread sheet.
+ u E" O S6 v; K* t: d+ Y' v) ?! C768832 APD DRC_CONSTRAINTS Following Performance Advisor instructions results in much longer DRC check time.0 T4 z! ]$ A1 Q: ^$ I
768990 F2B PACKAGERXL RFSIP architect 16.3 85Y Schematic to SiP fails due to softinclude in cds.lib file this problem does not occur on 16.2
/ K! t1 i8 ~; m( P4 o769097 SIG_INTEGRITY GEOMETRY_EXTRACT Sip Digital SI-Bus Simulation function will shut down auomatically when it is running! ?! R+ @4 }2 G) X+ W: |) G1 C
769235 SPIF OTHER need to be able to remove mbs_spif* properties added by mbs2brd
$ K- W( B4 C1 e5 P I769326 CONSTRAINT_MGR DATABASE Length by Layer crashing a/ h/ Z1 F. l2 `4 V `0 F
769336 ALLEGRO_EDITOR TESTPREP testprep density - returns Unable to add the PROBE_DENSITY subclasses.
7 @2 f8 p) x1 Z1 H+ d( Y769458 ALLEGRO_EDITOR OTHER SMD Jumper has a problem about the connection point when using the Add Jumper
0 n* U3 z' D3 h2 E$ M, p769845 ALLEGRO_EDITOR EDIT_ETCH Diffpair routing out affected by line to line spacing rule.
0 H" p. P) v( e; S' b/ V2 Y769934 SIP_LAYOUT WIREBOND Duplicate Finger Name.
9 v5 e' f/ m: i% ]$ U7 p( m0 g- R$ v770006 ALLEGRO_EDITOR OTHER Ratsnest_schedule[Power_AND_Ground] can not show figure without move symbol.
. M) _4 E& R: K770125 ALLEGRO_EDITOR DATABASE PCB SI GXL Via Labels grayed out on formand labels not visible on the canvas# S% e7 d8 n! y" I) B
770212 ALLEGRO_EDITOR DRC_CONSTR Incorrect Etch Turn under SMD pad DRC error on this board
) Q" v2 R: q) X1 u1 L! k770230 ALLEGRO_EDITOR ARTWORK Artwork fails to suppress unconnected pads on pins with the net_short property.5 P ^; V. F8 J& q3 U
770233 ALLEGRO_EDITOR MANUFACT Fillets are not behaving as intended.
# X- m" B. w W3 ]/ ^% F8 J/ k770442 SCM PACKAGER Error during Export Physical - The subdesign block instances ares not updated with reuse properties
8 o! D' X) _/ P$ ~0 Q0 B* E" E- G770556 CONSTRAINT_MGR ANALYSIS PCB Editor's Constraint Manager not updating custom constraint cell.
1 v5 a9 C i) Y3 t" ^! t770861 ALLEGRO_EDITOR PADS_IN PADS translation fails with no error message! `( q5 N* q+ A" ]8 ]- P
770872 SIG_INTEGRITY OTHER Opening Orcad PCB Editor for this board takes Performance License as well4 W& D, l5 A3 n3 B& u0 W; Q
771117 ALLEGRO_EDITOR DRC_CONSTR Allegro PCB Editor crashes on Update DRC-16.3/hotfix006
3 ]4 e6 I% }0 C- t' {# g771181 ALLEGRO_EDITOR PLACEMENT Component deleted completely from board file after we Mirror and rotate them while moving them.
' K, W! t/ \+ j1 q# I/ X771256 ALLEGRO_EDITOR DRC_CONSTR Update DRC consumes system memory and crashes allegro after approx 30 minutes
/ x0 ^( K8 X A: b+ R$ N771423 ALLEGRO_EDITOR SHAPE Shapes - Update to Smooth - Low on available memory please exit the program.7 D7 F6 x7 J: n7 c( x
771456 ALLEGRO_EDITOR EDIT_ETCH Allegro 16.3 crashes when using arrow keys
# ^ c9 M4 B; U771719 PSPICE MODELEDITOR Can not generate a DEHDL symbol from Model Editor, because no Capture license.
/ P, q* p B" Q+ T" y. ~771765 ALLEGRO_EDITOR PADS_IN PADS translation fails to translate symbol. W) F, i3 y$ p
771766 ALLEGRO_EDITOR DRC_CONSTR Moving certain components takes a long time on this board database.
5 n2 [$ a; E6 }771815 SIP_LAYOUT IO_PLANNER SiP OA co-design flow does not allow a save to the .sip file after modifications in IOP
6 U. T, R% R2 a/ `) E, @: V773072 SIP_LAYOUT ASSY_RULE_CHECK wire to wire same profile
3 C! t( t7 [. c& b773126 CONSTRAINT_MGR UI_FORMS Constraint Manager "Value Filtering" for Topology Schedule is missing TEMPLATE and "UserDefined"
5 o- r) V" Z' A2 D( K773179 ALLEGRO_EDITOR PAD_EDITOR pad_designer crashed when attemting to delete internal name layer.( f5 D( a( X2 j- ^9 u8 v/ s( T" O. B
773229 ALLEGRO_EDITOR OTHER Netrev never end importing netlist generated from Capture CIS: [ }& @* _ j3 r1 h- l1 B, b
773329 ALLEGRO_EDITOR MANUFACT Allegro closes when performing a Linear dimensioning and then selecting the undo icon.' D& |3 F0 Z4 t: A7 ]9 c
773483 ALLEGRO_EDITOR MODULES place module problem: B% u+ B% ~: W3 F' {2 x
774036 ALLEGRO_EDITOR INTERACTIV Rats not shown after move->mirror command
0 o2 F \0 L( L# z9 i7 l- ^+ p774170 ALLEGRO_EDITOR DATABASE DBDOCTOR fixes Error but it reappears and Artwork fails
- ~) s+ J8 \. [+ j: E774602 SCM OTHER ASA crash while working with hierarchy L, X/ a0 z6 _# p! v
774643 CONCEPT_HDL CORE DEHDL crash on edit of attributes3 r3 R. W% d( W; c0 k
775201 ALLEGRO_EDITOR SKILL Color palette can only be changed one time using skill commands+ D- }; d# V3 D. D. e6 r# e! G/ |% [
775815 SIP_LAYOUT WIREBOND Unused wire profile once purged using wire profile editor are still available in CM and Color dialog7 q9 |: A7 W# S" C) \* o; }, n
775826 SIP_LAYOUT WIREBOND Cannot change the Wire Profiles on the wirebonds in this design1 G$ P# F p! J! d; \7 E& ]
775842 SIP_LAYOUT WIZARDS Die text in wizard is changing DIE location when origin set in DIE text file is other than 0, 0
^1 E y/ t8 T& p# Q- f2 u. W" e4 D0 l" g0 ^8 P4 h
DATE: 04-23-2010 HOTFIX VERSION: 007
/ J" C }1 [2 s6 [( ^# d+ k===================================================================================================================================# n" i! f( W! t& `) c% ?2 m1 v
CCRID PRODUCT PRODUCTLEVEL2 TITLE+ z& ], D" o7 M$ |" {0 g
===================================================================================================================================3 \* S+ S* R1 X3 R, `0 j, M( g
721859 ALLEGRO_EDITOR OTHER update shape to smooth creates tmp file on remote file server working dir why?6 c# R O' R1 K( M
740201 SPECCTRA_MENT_ IMPORT Wrong stackup order after translating from mbs2sp5 ?; D: W( i9 T3 _
744797 SIP_LAYOUT OTHER Cannot Copy a connector (IO) symbol in APD and SiP tools
9 Z( h* L; z$ i/ Y$ G% d, S% h747831 CIS CONFIGURATION There is a delay of 5 to 10 mins in opening SQL database in V16.2 and V16.3. It is fine in V16.0.
# V/ i# h% u' f7 v: z6 k747848 CIS CONFIGURATION Unable to configure CIS with Oracle database due to Capture crash.
E2 u' H7 c' M751372 CAPTURE OTHER Copy / Paste Issue in capture 16.3/ u g k. I0 s- x y% g7 \: g6 @3 X
757434 ALLEGRO_EDITOR MODULES Allegro hangs the board file after creating Placement Replicate circuit.
+ e1 V$ L# T9 f" Q9 ]* }$ E759906 CIS PART_MANAGER Property copy from one to several parts doesn't work% S8 i# }% ~* o
760154 PSPICE NETLISTER Model parameter (Tj) is not affecting Smoke Analysis result
/ L: U5 F* L' a3 H1 {761177 CIS OTHER Error Message - Memory exhausted
0 i, ^# V3 j- D& {2 ~5 _" S: B762602 CIS EXPLORE_DATABASE CIS doesn't open datasheet for parts if it is not stored at default Capture location.
+ v0 N" e0 q2 X% a3 p# P763677 APD EDIT_ETCH The "Via to Via Line Fattening" tool is inconsistent in which clines are changed.
. W1 x* o4 v; c1 W! h4 S& l* d4 d763715 CAPTURE NETLIST_OTHER A long pin name gets truncated upto 31 characters when the wirelist is created.1 A8 `# ?! M! U% I
763878 CONSTRAINT_MGR DATABASE Why Pinpairs disappear after closing Constraint Manager?
E1 O* Q6 f" J0 d( c1 L764020 CAPTURE NETLISTS Usernetl.dll has changed between 16.2 and 16.3, D$ v" a% o7 N
764101 APD EDIT_ETCH Perpendicular routing through a Region does not work when the region segment is drawn at an angle.
P0 U, X; O1 p. t. M764200 ALLEGRO_EDITOR DRC_CONSTR Via at smd fit drc on a via that is placed fully inside the padstack having custom pad5 y& J3 E: K/ t$ \; p
764903 PSPICE ENVIRONMENT 'Run in Resume Mode' does not work in SPB 16.3* j3 u. ]: n5 G' E" T7 x% K
765206 F2B PACKAGERXL Unable to feedback subsequent pin swaps from Allegro7 k, H& K( k+ V' Q2 _7 m
765319 APD DRC_CONSTRAINTS Identical Constraints in Performance Advisor question0 F. {9 V. D5 a, w% ^- U7 X
765541 SIP_LAYOUT SHAPE Set via oversize value to 3 in dynamic shape instance parameters will make overlap shape.
w4 \( ` k3 y9 f766147 APD EDIT_ETCH Resize/Respace Diff Pairs does not work on 45 and off angle' R' _9 k8 g' \" u0 s# X
766337 SIG_INTEGRITY GEOMETRY_EXTRACT Geometry of Via model Extracted from board file is not identical to Original Via geometry design
- [6 s# Z& c) l* w2 d/ D0 n3 \766443 ALLEGRO_EDITOR PADS_IN unable to translate PADS ascii to brd in 16.3
- {5 h% B) W- ^0 ?+ s766581 CIS CONFIGURATION In 16.3 capture.exe remains memory-resident after exit/ \( t. B1 {* H
767161 ALLEGRO_EDITOR SHAPE The behavior of Add Fillet command is different by Hotfix version.. J$ z2 f; M: l. K
767217 SIP_LAYOUT IMPORT_DATA The Die-Text In wizard and it is crashing on the "Finish" step.
; W2 o; w6 S* ^* K767598 SIP_LAYOUT WIREBOND Can't wirebond SIP designs as it just hangs.
! Q1 z3 C* v" {% D% c767832 ALLEGRO_EDITOR DRC_CONSTR Reducing Design Accuracy updates Physical Diffpair constraints wrongly
+ |" S: W3 w5 l4 i5 P6 F; z5 j768822 ALLEGRO_EDITOR SKILL axlSetParam return value is divided by 10 to the power of the design accuracy.* [+ v4 @# `9 A6 }1 C, I
769150 CIS PART_MANAGER Update All part Status on a group changes “Do Not Stuff” status to “Stuffed” in V61.3_ISR_5.9 D' ?5 G" G* k( h4 T
/ L9 h' v4 N- ~5 s/ i6 kDATE: 04-09-2010 HOTFIX VERSION: 006
: u3 ~8 B+ D* T2 y& S===================================================================================================================================+ B* [8 U9 n: ~, U' c5 @9 a4 [
CCRID PRODUCT PRODUCTLEVEL2 TITLE
h/ V7 t) G4 I===================================================================================================================================$ K- z6 B' p; l$ D7 I# W& L
745241 CONSTRAINT_MGR TECHFILE Importing a tcf file automatically enables On-Line DRC.
# s) |& `5 K7 ^" [" V6 g752587 ALLEGRO_EDITOR PLACEMENT Uppercase File name(XX.mdd) for Placement replicate update on Linux.
3 l- ?$ Q/ b% v2 _2 f( i$ W7 U753626 CONCEPT_HDL CORE newgenasym error while saving the hierarchical block symbol$ S- `) B" ^+ A0 z' ]
753894 CAPTURE OTHER Case sensitive version control S/W4 t; L1 f+ z& s; w
754487 RF_PCB OTHER Various asymmetrical clearance problems uncovered - calculation issues?
3 q1 v* f' K5 ^" |7 ~) L4 L% U758272 CONSTRAINT_MGR UI_FORMS Entering values on the Min/Max Propagation Delays worksheet hangs the application.
# x! M, O( ?/ c/ X758911 PSPICE PROBE Pspice crashes while exporting probe data using our sample project$ c$ e! G! m" N' @
759871 CAPTURE PROPERTY_EDITOR Save option in Right Mouse Click on property editor of nets doesn't saves all the changes.. @( z; |6 L+ u0 [ Z2 u+ b2 Q
759890 SPECCTRA ROUTE Specctra autorouter ignoring prerouted nets$ A0 C' o, |$ G3 h
760067 ALLEGRO_EDITOR SHAPE Dynamic Shape not getting filled on board with odd angle placement and routing
4 ]' c( ?/ K2 k' g- h760284 CONCEPT_HDL CORE Update Sheet Variables turns of the grid3 l3 P f6 g1 ~6 K$ c0 M
760480 MODEL_INTEGRIT OTHER Message open clipboard failed when trying to open the rename/reorder dialog in Model Integrity
2 b3 v3 ^: O( u/ \/ J/ W" S760667 ALLEGRO_EDITOR PADS_IN The pads_in.exe translate incorrect drill shape from PADS 2005 ascii database.4 {+ w+ b/ V. n0 e! q
760741 ALLEGRO_EDITOR MENTOR mbs2brd does not work in 16.3 but works in 16.2; E k: x) j7 f$ l" @. t, l/ [
760810 CONSTRAINT_MGR INTERACTIV Deleting Region Deletes NCCs
9 r0 P5 U, B4 X! {& [& ?3 R761114 PSPICE PROBE Refresh issue in Display > Cursor window
! f0 w4 d, Y: [761180 ALLEGRO_EDITOR DRC_CONSTR Via_at_smd not working for custom shaped padstacks. r$ A. k- V( b( E+ C3 x# U
761305 SPIF OTHER Allegro crash when seleting any of the Route - PCB Router - submenu items.( S; W* g( K+ Y8 W0 a
761376 ALLEGRO_EDITOR PAD_EDITOR Wizard_Template_Path is not considered for symbol template look-up ?- c- S: `, F# y
761416 ALLEGRO_EDITOR DATABASE Allegro crash on chaning the subclass for group of clines O3 z t- p. l/ q1 m
761492 ALLEGRO_EDITOR SKILL about axlTransformObject function u" j2 g6 E1 @7 s
761518 F2B PACKAGERXL about mismatch library path between cds.lib and actual
% _! ]# J+ ~/ r% M4 @. @0 u" Z+ |3 C761737 ALLEGRO_EDITOR OTHER Running Dbdoctor after executing Skill is giving symbol fit error for the .dra file
5 ~$ o& |* W0 L9 `1 d& p762155 ALLEGRO_EDITOR SYMBOL Updating a symbol changes the netname of the cline resulting in drcs.8 u* ?! r4 c; E3 x+ N( F6 K9 n
762181 ALLEGRO_EDITOR OTHER Allegro netrev crashes for long device name in PST* files
; `5 P' T0 q& q6 b, p* R8 D762316 ALLEGRO_EDITOR MANUFACT Allegro disappears on Adding dimensions for the symbol file8 l2 H4 G- }3 I) x
762792 ALLEGRO_EDITOR PADS_IN PADS_IN fails for SPB 16.3* b4 e! @, d7 X$ F+ \% d0 x
763108 ALLEGRO_EDITOR SHAPE Z-copy shape create an error like VOID boundary may not cross itself, T; H) ?8 s8 ]% }+ K: ?
763134 SIG_INTEGRITY SIMULATION Bit 7 of a simulation is out of sync with rest of bus. It should be the same for all bus values.
4 h' L8 f" G1 ?; }( c$ }763149 CIS GEN_BOM CIS BOM in V16.3 is not correct if database has Quantity field and its value is 0.
" H1 \- G" t' i# w8 i4 p4 V763296 ALLEGRO_EDITOR REFRESH The error was happened while doing the SUM6 Q* ?1 a6 c. \3 C! [
763303 ALLEGRO_EDITOR OTHER SMD Jumper has a problem while using the Add Jumper
& S) P. n: O G7 l8 x763315 ALLEGRO_EDITOR PADS_IN pads_in got error message WARNING ERROR(SPMHDB-205)
. A0 A$ V9 Y4 |, L/ m8 c' q2 X763354 ALLEGRO_EDITOR PADS_IN Auto suppress redundant shape while using pads_in translator
0 q- M% h, @- K( K763428 ALLEGRO_EDITOR PADS_IN enhance pads_in.exe translate spacing and physical rule into Allegro.
) C: |$ A; h" l/ O763446 ALLEGRO_EDITOR REPORTS missing fillet is reporting pad without drill
( A& Q! H* q2 d. W* \7 C; U763448 ALLEGRO_EDITOR DRC_CONSTR Performance advisor shows Cset as unused nets when it is assigned to Diff pairs or xnets.
" a! v% i1 i8 E2 n763586 ALLEGRO_EDITOR DATABASE Allegro rounds off the value after decimal in CM
/ V# Q; r8 J& Q _' |764077 CONCEPT_HDL CHECKPLUS The output predicate in the Graphical environment is not always returning the pin object for an output pin.; _1 G# t) Z& b6 J7 P& k
7 }# q2 b1 G+ JDATE: 03-26-2010 HOTFIX VERSION: 005/ g3 d2 I4 @; U( x7 d
===================================================================================================================================
) e3 I3 z7 h2 [. u. PCCRID PRODUCT PRODUCTLEVEL2 TITLE
' C* ~# r- t/ ?: \& n- J( Z6 s===================================================================================================================================
: d( x- @/ B6 D! M& A6 [599819 SIP_LAYOUT 3D_VIEWER display soldermask by default in the 3d viewer0 H w! n- J: @ a$ V
735992 CONCEPT_HDL CORE Create Test Schematic does not use the correct package type
- x& ]5 W$ N" i: f5 {, Y743787 SIG_EXPLORER OTHER 16.3 SigXP crash if sigxp.run created by previous version exist.
% q7 d# ] P/ R746320 CAPTURE NETLIST_ALLEGRO Remove Semi-colon from invalid pin-name check during netlisting
! u. O0 p* s7 W: G746444 ALLEGRO_EDITOR OTHER show element fails to display info on a via if it is in a module.
; N6 s2 T# i0 V3 c7 f) L, _* Y746726 SIG_INTEGRITY SIGWAVE Save As and Open Dialogs open in last saved directory
+ {( l2 D T, Q4 V5 c2 ]$ c0 L750080 CAPTURE NETLIST_ALLEGRO Improve error message ERROR(SPCODD-390)
3 s1 [0 E0 R8 E: ^& a+ N0 i& G7 w750606 SIP_LAYOUT ASSY_RULE_CHECK Wire to BF same profile check
* v1 }3 q( i( L9 j3 P- h& T751492 CAPTURE FPGA Option to swap the pin-numbers rather than their locations in the Schematic after back-annotation
; h6 e/ I; s4 m/ q753834 CIS LINK_DATABASE_PA unable to link multiple database part/ _6 H* h& V/ k* B' h7 C9 P
753990 F2B PACKAGERXL Delay in opening the subdesign tab in the Export Physical setup in SPB 16.3
" ?' R* |* Y {2 E. ~5 j754328 LAYOUT TRANSLATORS L2A gives error Subclass name TOP not valid Allegro subcls with s029 hotfix
8 E0 X$ N, C8 q+ b754434 CONSTRAINT_MGR OTHER allegro crashes when deleting matched group
, u! L: m" P( z y# m755111 ALLEGRO_EDITOR INTERACTIV "ALT_SYMBOLS_HARD TRUE" property does not work when I mirrored symbol using move command in 16.3.# w) M6 J7 o, J- P. C
756131 PSPICE SIMULATOR Capture crashes while re-running simulation" G) G# K4 Q( s+ F! i' N7 }
756148 PSPICE PROBE Zoom Area in Probe Window does not work for digital signal in SPB163
: P9 d& K$ w! ?2 w) z0 R* @$ N756169 SIG_EXPLORER OTHER Signal Explorer crashing due to sigsimcntl.dat
( K7 _$ M' T" X! t3 c/ e756176 PSPICE PROBE Trace color is wrongly interpreted in PSpice probe window.
d% n4 I$ o) S* z1 {756224 SIG_INTEGRITY SIMULATION Simulation aborts reporting that VIA models have changed$ N! z; V! a0 l+ y6 W
756281 ALLEGRO_EDITOR OTHER Why *.sav file cannot be recovered from PCB Editor utilities?
5 \+ s! T/ p0 A' R, Y0 X% B756673 SIP_LAYOUT ASSY_RULE_CHECK Running ADRC Metal to metal checks causes false X-D DRCs, cannot clear them and trying crashes the tool
) A" a7 L8 r) {& r/ N1 P756918 ALLEGRO_EDITOR OTHER Allegro angular dimensions working incorrect in 16.3
4 m$ ?: W, @! c7 i z9 C7 ~756932 ALLEGRO_EDITOR CREATE_SYM Create symbol fails with error duplicate pin number- s! ]8 q; I# R0 U8 d5 ~0 r
756976 ALLEGRO_EDITOR SKILL axlChangeWidth always return nil in Allegro version 16.3% o! I( @" V4 h% }) W8 h
757000 PSPICE NETLISTER Incorrect Hierarchical Format Netlist created
; [! g4 u. l% x% h2 f757406 APD OTHER Implement Segment over void features in APD L% k9 G( D& t" t" r
757624 SIG_EXPLORER OTHER Sigxp runtime error when simulation is run and exit without saving the topology
" R( T8 Q* X; y; n757820 ALLEGRO_EDITOR SHAPE Shape does not void to hole if there is no pad, a- r4 S! W/ K7 g, A' {, |4 M" M
758009 ALLEGRO_EDITOR OTHER Export > Library (MECH_SYM) adds a new subclass NCROUTE_PATH, data moved from one subclass to another.
( E% e" Q% z, p7 j1 D2 z1 q v5 D758022 CAPTURE DRC Capture crash while running DRC with “Run Physical Rules” checkbox./ L* {. Q e$ Z/ ~: O4 L$ E. e
758190 ALLEGRO_EDITOR PAD_EDITOR PCB Editor crashing on pin move in this design
% k* J7 [$ ?" ~6 C8 R4 T758374 F2B DESIGNVARI Problem with Mechanical part in Variant Editor- E4 S/ |, `2 ]: y% g
758471 SIG_INTEGRITY OTHER Differential impedance does not change on changing the etch effect values.) b6 b- b1 H# d- u% v/ M5 i
758490 CIS CRYSTAL_REPORTS Different crystal report output in 16.3 than from 16.2. Y, [1 q7 I6 q2 b
758498 CAPTURE NETLISTS PCB Editor netlister hangs$ s3 ~/ f8 ^, T, S
758584 APD SHAPE Shape not voiding all elements1 R& F) l& p" E8 R T( D5 I/ R
758886 ALLEGRO_EDITOR REPORTS Total number of nets is wrong into Testprep Report: N/ p" T" n; q
759146 ALLEGRO_EDITOR SKILL The title is not displayed in the form by the version.- D+ r/ o. q' _
759339 ALLEGRO_EDITOR ARTWORK artwork output fails by SPB16.x.) i2 o0 g5 ^3 U& d8 x& a5 r9 p! W9 S
759591 ALLEGRO_EDITOR SKILL axlSetParam fails and does not round the value as indicated by the warning message, M; }8 z; g/ _; f7 i
759816 CONSTRAINT_MGR OTHER Allegro Hangs when double click on a Bus in CM
( [9 o8 Q5 b" ]+ k+ B( R759947 APD OTHER Need an a way to convert Lines into Clines
$ |, J. G$ t- l K760353 ALLEGRO_EDITOR MANUFACT Allegro crashes and creates a .sav file on running the silkscreen command from Manufacture > Silkscreen
4 }5 {% F3 n: k/ r2 c760432 ALLEGRO_EDITOR PARTITION Unable to remove fixed property after partition import
5 V& `3 z% a! y; J* A3 i1 W760638 ALLEGRO_EDITOR PADS_IN pads_in translator can not handle " PINPAIRGROUP ".- K C9 N2 a1 A! |9 v$ b9 S
760734 ALLEGRO_EDITOR SHAPE Different therma contacts on rotated partsl
# ~+ {" d6 a2 }; i+ p' x761436 CAPTURE NETLIST_ALLEGRO SPCODD-53 Error when creating netlist with PACK_SHORT5 W) ^- o: f. q/ m O2 E
8 T' x; `2 e4 c7 J ~ R
DATE: 03-12-2010 HOTFIX VERSION: 004# q9 r9 I9 K% t$ D' }' i
===================================================================================================================================
' M( n( x7 q4 y* o) H! o* f( uCCRID PRODUCT PRODUCTLEVEL2 TITLE, {3 D# K7 D2 A! s% f3 `: m
===================================================================================================================================7 ]& k; J& O/ h/ K& b! p
689495 ALLEGRO_EDITOR DATABASE corrupt database
: m* ^% @3 h1 H* z, L# C725944 SIG_INTEGRITY GEOMETRY_EXTRACT xtalk make allegro freeze and never give hands8 v& D! s; R7 K% q$ o; m" J+ o1 y
732604 SIP_LAYOUT SHAPE Shape Issue - added shape will not clear around other elements.' |' X# P' ]+ ?: @+ B) e4 n
740106 PSPICE NETLISTER The "Enable PSpice AA Support for Legacy" option does not give the Desired Monte Carlo results4 r8 _5 O; ~* A# }5 y
744259 SCM UI Signal order reversed when a Vectored Signal name is renamed in reverse0 ]: m6 S! ?0 M( K0 ?) ]/ _/ T# u
745554 SIG_INTEGRITY GEOMETRY_EXTRACT Time to get Xtalk simulation result in 16.2 is lower than acceptable by comparing the time in 15.7* _$ E* I Y, I, |8 ]# b. G
745595 RF_PCB FE_IFF_IMPORT import iff RF_PCB give an empty block
" `6 t; S3 q8 p e' Y747133 CAPTURE STABILITY ERROR [DSM0006] Unable to save( A/ T5 p# ?0 n& g% ]: f A
747679 CAPTURE STABILITY Trying to Save the Design in 16.2 format gives DSM0006 Error and crashes Capture
' Q7 u( n9 G q750460 CIS FOOTPRINT_VIEW 3D footprint viewer doesn't shows the footprints% U9 d7 n1 |/ L0 p: X6 _
750777 SIG_INTEGRITY OTHER Trace impedance showing wrong3 ?/ Z. _# P2 [; r
751424 ALLEGRO_EDITOR DRC_CONSTR Unexpacted DRC for Shape to Route Keepout
* ?8 L8 ^% e$ W. k2 n751897 SIP_LAYOUT SPECCTRA_IF Radial Router crashing SiP tool
U' b& e) b8 [& C" P% s6 Y' D1 E$ a752029 SCM OTHER Cross probing not working between SCM and Allegro Editor in Linux Environment$ j' S1 e- e- N
752450 APD PADSTACK_EDITOR APD crashes when selecting a User Definable Mask Layers.
7 u" L: s3 Y6 g+ h& R; q9 t752581 PSPICE PROBE Pspice probe window crash+ h4 Z1 ^: j- |, o L$ F
752709 ALLEGRO_EDITOR PLOTTING Sheet content doesnot plots title block
. K- \1 n- e: p2 F" M! O- v752908 ALLEGRO_EDITOR INTERFACES Output from Export > DXF shows one instance of a via on the wrong layer
" K7 \+ t0 t' ?2 g. [6 L' N+ a; k" I# G753226 ALLEGRO_EDITOR OTHER File > Change Editor doesn't shows the default Product Options
! J& H4 g" M; Z8 ^753622 ALLEGRO_EDITOR GRAPHICS Enahnce capture image command to default the save as location to working dir
) `% y- Q, [( C8 C2 X753773 APD WIREBOND Requesting the option to set the diameter of the default WB_TACKPOINT power ring pad.
) {, M- ^7 m: Z7 ]! Y0 e& h) D753778 APD IMPORT_DATA Import NA2 displays the design momentarily and then crashes
5 t( r4 [5 c9 ^! ]6 k% |753866 SIG_INTEGRITY OTHER about Select by Polygon after move command$ ]3 Q0 @/ ^3 e% c( f9 {
753958 CAPTURE OTHER Capture V16.3 is extremely slow while edting schematics of design placed on network drive via VPN.! A6 I ~3 E5 M( [. e/ X k6 ^
754050 ALLEGRO_EDITOR UI_FORMS Why show element window disappears when scriptmode is set invisible
( q7 ? ~* x! A' m" G: M, S" M754143 SIP_LAYOUT OTHER SiP Package Design Integrity - running Extra Cline segments generates report without Layer number, a( k$ y& I& L
754327 ALLEGRO_EDITOR OTHER Rename Sub Class is not working as desired.0 r4 N* O4 j6 X1 C
754364 ALLEGRO_EDITOR PLACEMENT Crash when applying placement replication
6 @4 I' P& K6 f: c: }754462 ALLEGRO_EDITOR SHAPE Allegro circular dynamic shape fails to fill6 m$ T6 r; k$ k" Y' P
754819 ALLEGRO_EDITOR OTHER Create details shows wrong graphics for filled curves |0 E8 Y7 @9 R: ^2 b
755176 ALLEGRO_EDITOR PADS_IN Pads translation succeeds in v16.2 but fails in v16.3 on this ASCII file
3 y1 s$ t+ m' ?755256 ALLEGRO_EDITOR OTHER Attached script is crashing the designs in v16.3
8 }1 A5 D1 k5 U. q L$ Z! U& m755610 CONCEPT_HDL CREFER Cref hyper links does not work for signals where number "0" used to define the zone for page border
0 W4 P. I- R7 H) B; x' F% B755787 ALLEGRO_EDITOR EDIT_ETCH crash using resize_respace_dp command2 b4 E2 R# ?" r% V: M8 A
755881 ALLEGRO_EDITOR DATABASE Swap component crashes application; m4 L/ N& H' l/ p$ X! \1 S
756092 CAPTURE PROPERTY_EDITOR property editor flickers and loops on value edits
7 M: A5 Z. F5 O/ M4 u) Q" w0 H
/ F" o( N" s: v8 l! p. c; GDATE: 02-23-2010 HOTFIX VERSION: 003
0 R7 m5 B8 E* H4 j: N6 M1 N: {===================================================================================================================================3 C7 m6 W& d* T1 h% C
CCRID PRODUCT PRODUCTLEVEL2 TITLE
l% w0 ^/ p, |' o G9 s2 ^8 Z' X===================================================================================================================================4 @2 @/ o1 F7 B! j7 I' Q4 N" O9 V
263504 CONCEPT_HDL CHECKPLUS Checkplus fails to run if crefrpt exists in the design: o. X, U4 [7 f% Q% L
726836 ALLEGRO_EDITOR SKILL axlGeo2Str() and axlGeoEqual() return different results
$ Z- @3 z3 U3 [5 R7 _/ j4 b730820 SIP_LAYOUT PADSTACK_EDITOR Changing the Via diameter will cause the SiP tool to crash
; J9 U* r. m; M5 Z! }735193 CAPTURE FONTS Pin_names and Pin_numbers get convertred into darkened blocks in ‘Zoom to all’ view in V16.2.3 h" z! c9 |8 ~ n5 _% q
737307 SIG_INTEGRITY GEOMETRY_EXTRACT differential pair extraction to sigxp fails to extract coupled sparam via models
& U0 h+ A3 g$ @ s- A8 I) Z740936 ALLEGRO_EDITOR SYMBOL Confusing error message during Create Symbol- Q7 Q; d2 V) X; Q. V6 `0 I
744191 ALLEGRO_EDITOR EDIT_ETCH Arc routing enhancement! \$ @+ v; T3 n, R8 V
744497 ALLEGRO_EDITOR INTERACTIV PCB Editor Crashes with Data Customization Feature; c+ F" ~- i( M
746572 ALLEGRO_EDITOR DATABASE Reoccuring error in attribute pointer to attribute invalid on dra.* F- L& ?- ]# Y; r5 Z
746978 SIG_INTEGRITY SIGWAVE 2 licenses were used for SigXP and SigWave.
0 |' J7 p: U- B4 f6 y; j% ~747219 SIP_LAYOUT SHAPE Dynamic Filleting not working with odd angles" R7 Q" Q0 E1 Y$ \! g7 v" F; u
747593 ALLEGRO_EDITOR PADS_IN Some RULE_SETS cause the PADS translation to fail.
6 [+ f* s2 ?, F( P747746 ALLEGRO_EDITOR OTHER Request for more detail in downrev.log file$ O, O, S, Q9 }$ u$ b- j$ S
748033 GRE IFP_INTERACTIVE Enhancement in GRE where Show Element on Bundleshould show the total number of nets that are part of the bundle1 N" C1 S7 v" ]. P9 n
748333 ALLEGRO_EDITOR OTHER place by schematic page number not showing pages correctly
8 Q0 |& c u' Q4 e: d" {748375 ALLEGRO_EDITOR MANUFACT gloss - line smoothing causes crash6 A4 ^2 Y% t- @" P6 P
748818 ALLEGRO_EDITOR DRC_CONSTR Undesired DRCs shown in allegro 16.3 while moving component and the same are removed by update DRC' I& n& c2 E) r* V
748865 CONSTRAINT_MGR OTHER Allegro 16.3 slow to move component with CM open
9 u: p. l" _2 }) o/ g+ s749009 APD WIREBOND a part of function of the finger alinement doesn't work
9 H+ j2 t% ?& f) o* t749162 SIG_EXPLORER INTERACTIV Unable to proceed after RMB > Preference > Cancel4 z3 l2 j( y; b2 ^7 P) ]2 s" q
749307 ALLEGRO_EDITOR MENTOR mbs2brd fails with error VIF_Allegro_Write
2 q7 F( T. q% c* r6 W C- h749435 CIS DESIGN_VARIANT Cannot create variant part in 16.3
" f# b6 S' F2 Y749854 APD PADSTACK_EDITOR The value of user-defined mask layer is not retained in the design.
+ |2 D. L" Z0 A9 V749891 ALLEGRO_EDITOR PARTITION Unable to delete existing partitions
4 C6 q1 J M2 z! S749949 SIG_EXPLORER EXTRACTTOP A Topology extraction fails using APD and SiP series with the latest hotfix(SPB16.30.001).
1 k/ O$ ]# G' r4 r, M7 v750008 CAPTURE NETLIST_ALLEGRO Netlist different in SPB 16.3 and after installing SPB 16.3 hotfix 1 A% s0 H) t) M- g8 T5 w2 P5 r3 |
750591 ALLEGRO_EDITOR DATABASE Analyze diff pair object fails to display uncopled lenght values.
- [2 o& f C$ l% Y0 k750888 SPECCTRA ROUTE specctra is crashing while routing
2 I4 P7 I' r* k/ U4 |751204 F2B DESIGNVARI Design difference crashes while reading funcview
5 d. i3 F h6 J5 P8 v1 O1 K- n; h751398 ALLEGRO_EDITOR OTHER Allegro Crash when Edit is selected in Setup > Outline > Room outline: R9 P; ^4 U1 `: z+ i4 Q. ]- I
751578 ALLEGRO_EDITOR PADS_IN pads_in hangs while conversion3 _" I% n8 T( f5 s* t- i' R
c: E& N* y/ I8 SDATE: 02-09-2010 HOTFIX VERSION: 002. Q. O! Q$ m/ [0 f% a/ G' z
===================================================================================================================================' |: D, t; i0 @" f! }% u/ L
CCRID PRODUCT PRODUCTLEVEL2 TITLE, F3 |# ? a- i
===================================================================================================================================1 X% m9 Q S4 Y/ u/ \
527012 SIG_INTEGRITY IRDROP Severe Memory leak in IRDrop3 X+ K1 i, H" E f. K$ e
623678 PCB_LIBRARIAN CORE PDV freezes when changing grid
+ A$ Z$ v- Y4 Y5 k- P672592 ALLEGRO_EDITOR SHAPE Shape does not void correctly untill a clearance oversize value is added
' ]8 V' Q$ t7 y4 f1 P! Y. l( E688062 PCB_LIBRARIAN CORE PDV Strange characters appear when copying text into Bus Arrows ( Text symbols)( ~0 c- j6 w8 ~5 G, T8 J
710170 SIG_INTEGRITY IRDROP Run IR Drop even if all components on the net are not placed.
* Y$ Q# V8 N# r T. V710174 SIG_INTEGRITY IRDROP Audit function for IR Drop.$ Y6 P1 @0 M' ]* s
726833 PSPICE DEHDL Modify the methodology for migrating 15.7 and 16.2 users of ConceptPSpice
& ~: W) F, R' [ r+ y730717 SCM UI Unable to delete a zero connection signal in SLP which has a pull-up
0 s+ P0 V) Q7 X5 b9 M731017 ALLEGRO_EDITOR DRC_CONSTR DRC's show out of date when artwork is run
% G2 P( f7 ^6 [" I732145 CONCEPT_HDL OTHER Incorrectly generated VHDL netlist
% F1 a, t9 r& g/ ~" n+ V740123 ALLEGRO_EDITOR GRAPHICS Capture Image command fillin missing from jrl and script files% v: N) k. r e# b# ^
740278 ALLEGRO_EDITOR OTHER Jumper fucntion for Single Side PCB Design: C5 b% U/ }# |; ~. l
740656 ALLEGRO_EDITOR GRAPHICS Can we place custdatatips.cdt file on a site level for SPB16.3
1 B3 q" E, V4 n) L4 o% }: |741222 CONCEPT_HDL CORE Replace command (in Windows mode) causes crash
7 V7 o$ ~; r- t% b2 I# | w8 t742389 ALLEGRO_EDITOR EDIT_ETCH Change or add message when using Countour route% I) |6 b, \) J2 ~
743275 APD DATABASE With DRC enabled, this design seg faults in axldbid.c (solaris only). DRC update takes orders of magnitude longer on sun. g. y* w" ? c6 K( S
743623 F2B PACKAGERXL Pxl error when using pack_ignore on reuse blocks
" H" b! ?3 h$ X0 Q3 @- v744348 F2B BOM PART_NAME column getting word wrapped inspite of sufficient space in the HTML BOM report.0 U0 i: |" ]+ q1 i, w8 i/ |
745062 CONSTRAINT_MGR OTHER import techfile does not add new layers in cross section- h5 X/ k7 q0 U1 T2 [
745148 ALLEGRO_EDITOR GRAPHICS Allegro ptf driven HEIGHT value not pushed into 3D Viewer
, c5 b% S( u. s& I* m745301 ALLEGRO_EDITOR DATABASE Allegro 16.3 crsh on moving component
k( e! a3 D1 q( X2 r/ ~+ `) J745518 ALLEGRO_EDITOR DRC_CONSTR DRCs not shown when "Enable Antipads as Route keepout is checked in"2 }' X: K- j5 R( r
745745 SIP_LAYOUT WIZARDS Die Text In changing the pin names on duplicates* W8 q! \, G- x: F/ n6 N
745785 CONSTRAINT_MGR UI_FORMS Unnecessary window opens when the cell in PCSet By layer worksheet was clicked.
+ r' x8 y% W. b( _9 ?: K746002 CONCEPT_HDL CREFER Could not find pc.db in the root design$ p- Q! \7 _# [+ U2 G4 p8 C+ M- j. z
746010 CONSTRAINT_MGR SCHEM_FTB Updating the brd file using the "Import Changes Only" option overwrites the modified constraints in
" @; P9 t' V& @* K, m746080 CONSTRAINT_MGR OTHER Click Constraint Manager filter icons crash software6 x O# o4 @# ^. F5 C
746137 APD IMPORT_DATA Import > NA2 not transalating certain layers and padstack sizes$ Q3 {' I# K! D
746370 ALLEGRO_EDITOR GRAPHICS Setting infinite_cursor_bug_nt variable flips mouse movement on flip design( i! M; c( G. x
746519 CONCEPT_HDL CHECKPLUS CheckPlus the if statement is not seeing the True condition or the output predicate is not returning the True condition.; }0 b) @ R! M& O- z
746546 PCB_LIBRARIAN VERIFICATION con2con choosing incorrect PART_NAME in PTF File during verification
( B% t; d% F7 _1 j& R* ? V746865 CONCEPT_HDL CORE Tool generated pspice net names in core concept design cause short with copy all.1 S, D2 p5 }4 {( M
747636 SIP_RF OTHER RFSIP Layout RF Module Export chips & connectivity is not writing die attach method to chips file/ v8 h+ l) f F7 X A! ^3 R
q7 e; t. Z$ s. vDATE: 01-31-2010 HOTFIX VERSION: 0010 ?: |( u! o _
===================================================================================================================================/ o! B+ T) Q z" L) n3 v! Z
CCRID PRODUCT PRODUCTLEVEL2 TITLE
7 m: C: x0 O" E& O; p===================================================================================================================================
: v( I6 J' _, i2 Z' p' r491042 CONCEPT_HDL SECTION Prevent PackagerXL from changing visibility on SEC attribute* ]2 x. l2 p) _; c
496910 CAPTURE NETLIST_ALLEGRO Inconsistent netlist creation
" y' g% C" J$ w/ E0 k+ L! f9 V: f558783 PSPICE NETLISTER Why do Models with "awb*" prefix need wirte permissions to "*.ind" files?
# ~# K& U) i/ v5 _. r- h- i" k643241 CAPTURE SCHEMATIC_EDITOR OrCAD crashed while replacing cache
- |) N8 @# J% ]* H654292 ALLEGRO_EDITOR DATABASE Propagation Delay constraint behaves differently between 16.01 and 16.2+ ^# G' V: k4 ~- F0 I
662829 CONCEPT_HDL GLOBALCHANGE Global Update should honor property visibility settings in ppt_optionset; u7 I3 {/ {0 z" h* P
672718 SIP_LAYOUT EXPORT_DATA "Export>Symbol Spreadsheet" should export a .cvf not a .txt
% z0 @8 P, o6 H2 u T' S676233 CAPTURE NETLIST_ALLEGRO Cross probing stops working if design name has dots
2 |) ~ M5 K. m4 N9 t678739 CONCEPT_HDL CONSTRAINT_MGR Manually added targets in matchgroups lost when reopen CM) F3 D R2 N+ L4 }! m" z" s) o
690618 F2B BOM Write protected template.bom fails to write callouts' e4 \/ T- C5 @: o8 b+ [
700246 CIS LINK_DATABASE_PA Need option to update symbol always when linking part in CIS
$ {/ @0 ~3 B# ~; j) T* X7 l705393 CONCEPT_HDL CORE ConceptHDL crashes while switching to another hierarchy level under File > Plot Preview.4 _" g4 J9 k. ?
708634 ALLEGRO_EDITOR SHAPE Shapes getting incorrectly displayed in 16.2: E5 b0 H% D7 N. Z
708950 CONCEPT_HDL CORE Tool crashes while trying to change the text on the schematic using a text editor./ ?) m5 z6 j0 a; o
709823 ALLEGRO_EDITOR OTHER Arcs not converted properly when upgrading symbols% |5 d, m7 ~ W6 s
713964 F2B PACKAGERXL Net property Probe_Number is getting changed during the packaging run2 J0 A' W( s/ A( s
718119 F2B BOM Exclude the callout file name from the template.bom file- j# @3 n& X- u: Q
718496 SIG_INTEGRITY SIGWAVE Frequency at smith chart.
7 `! m+ r2 n2 M4 E9 Z721422 CONCEPT_HDL CHECKPLUS Checkplus fails if "\\" character is used in the parameter list
/ y5 ?7 X/ g+ J, p0 V721788 SCM OTHER SCM unresponsive while closing out a Block without Saving$ Q2 M" P) G' H5 I
721801 CONCEPT_HDL CORE Save As crashes DE HDL if an existing page is selected in the design1 i3 [4 `/ D% q$ e2 [+ g, C
722653 F2B PACKAGERXL Packaging does not complete2 ^# Z/ I) y8 T' b. L( f- O6 }
725285 CONCEPT_HDL CORE nconcepthdl does not work same as concepthdl for same script.
: f7 {6 l! q0 J) j; g725719 CONCEPT_HDL CORE wire pettern of Publish PDF
% A! e) s6 b) \727062 CONCEPT_HDL CREFER Custom properties not visible for TOC symbol in schref_1 view% e5 x1 g% F/ P: I+ p
727194 CAPTURE CORRUPT_DESIGN Random Capture crash7 M4 A5 _7 ?% G: F6 H9 D
727704 SCM PACKAGER ASA to PCB getting out of sync/ L u8 d9 l9 w+ u/ e0 \& L1 W
728066 CAPTURE NETLIST_ALLEGRO Allegro PCB Edtior net cannot be generated if PACK_SHORT is used
$ Y+ J( [- l8 z% r% ?# A729214 CONCEPT_HDL CORE SHOW_PNN_SIGNAME directive used with Windows Mode gives crash% a- l1 T4 B+ [! G7 a
730295 SIG_INTEGRITY OTHER Filled rectangle shapes not extracted properly" v J2 T, z4 V: D5 |- Z4 o( k
731183 CIS QUERY_DATABASE CIS Query fails with ODBC Error for query (Price contains 29)
$ {! c5 T1 e+ e732073 SIP_LAYOUT DXF_IF DXF_OUT generate an incorrect shape
# _# Z% o8 J1 U4 V" k# H5 n9 H- s732138 CONCEPT_HDL CORE Cannot change SI model assignments5 V3 V9 g: L; i4 I; X
732216 ADW DBEDITOR dbeditor crashes doing copy-as-new into lib folder that has partially completed chips.prt file+ y1 U. y; c) j" p* Z& V
732249 SIG_INTEGRITY SIMULATION Probe sim with custom stimulus cause segmentation fault. Linux only.* B3 ], l E5 Z8 z/ s( [
732847 ALLEGRO_EDITOR DRC_CONSTR Manual Void uses Shape to Pin constraint to void Holes
! r! ~3 _* g6 L* r733261 FLOWS PROJMGR Project manager does not work with the Restricted User in client server environment
: k0 L6 m! ]0 ?+ x1 t733773 CONCEPT_HDL OTHER Syntax issues in DEHDL. P& N& k( H( U0 H" k
734260 APD COLOR Why subclasses still remain visible even after global visibility is turned off.7 R6 w# s, \" A, B! {
734419 CONCEPT_HDL CORE Concept crashes in windows mode when netname is deleted on schematics generated by ASA0 z% q9 m, i, P' n7 U5 d! A* F
734555 CONSTRAINT_MGR SCHEM_FTB Import Logic does not overwrite the Constraints9 X6 v9 h# g u
735290 CONCEPT_HDL OTHER Concept's PDF Publisher has issues.- R" X2 M0 H2 y1 G
735892 CONCEPT_HDL CORE "Component Modify" changes visiblilty of Key properties* _# `8 d0 U+ N# b1 u
735977 ALLEGRO_EDITOR MENTOR Mentor to Allegro translation fails without any error message# O+ Y4 t- L1 j% G- _2 u8 @0 c
736071 CONCEPT_HDL CORE Property visibility is not retained on the schematic instance when we modify the component on sch.
1 E# j; Q7 P; M, c7 ?736165 SIP_LAYOUT SCHEMATIC_FTB about error message of "schematic to layout"
" N5 @1 i' q; r8 b9 E: }736167 CONCEPT_HDL CORE HDL crashes when I select BGA symbol in Component Browser0 ? t( G: a+ T. M+ M( G; U# S( j" {
736911 ALLEGRO_EDITOR SHAPE No DRC displayed when Place Bounds are edge to edge
1 M* }& z9 x7 `0 S* b738035 ALLEGRO_EDITOR OTHER Measure function has different result between 15.7 and 16.2 version.: o: D" t' s6 @. Q6 Y5 Y6 i
738129 CONSTRAINT_MGR UI_FORMS Need Diffpair Constraints option in Analysis Modes Electrical Options with Performance license9 u: p% S: t4 t H, `& W
738276 ALLEGRO_EDITOR PLACEMENT No feedback in console window when placing unfound components in Allgero 16.3
- Q6 |) T2 b% N' z- ^* }2 Z3 {738366 ALLEGRO_EDITOR GRAPHICS 3d viewer not showing some connectors with mutliple place bounds correctly$ u! V) M A( e; [4 h2 h7 q
738454 SIG_INTEGRITY FIELD_SOLVERS EMS2D extracts incorrect CPW to Trace spacing5 U9 o1 E; C# Z& i3 `3 _0 l
738578 ALLEGRO_EDITOR OTHER scriptmode +w doesnot work on Linux! s6 n4 E8 V2 c
738869 ALLEGRO_EDITOR OTHER Error msg when cds.lib contains missing SOFTINCLUDE: E/ B; P# u5 |6 p9 D( @
739116 EMI SIMULATION At EMI simulation on SigXP an extra Sigwave form is launched.' q7 ~8 |1 _' B3 |5 P$ P* R
739225 ALLEGRO_EDITOR GRAPHICS Ability to lock the 'Hide Pallette' option
: O# e8 l* {* J; l* V' [- _* c739599 ALLEGRO_EDITOR DRC_CONSTR drc_errchk indic
3 T6 r7 v) ^- Z. n& ]739628 ALLEGRO_EDITOR SYMBOL Opening a symbol file is crashing allegro.
5 G- {0 b1 M+ t7 ?' D739653 ALLEGRO_EDITOR SHAPE Shape created in 15.X .dra changes geometry when uprev'd to 16.X
# k9 G! {& Q5 o! S) k739661 ALLEGRO_EDITOR OTHER Export netlist creates incorrect via_list syntax.
$ P3 L) S8 L: M* ^0 S( K739872 ALLEGRO_EDITOR SKILL Crash while performing axlExtractToFile in 16.3, T6 D( M, Y+ {6 b6 f3 i. C
739934 SIG_INTEGRITY OTHER specctraquest crash on changing signal model+ l# R# f' j! i. S- J* h% t; Z" Y- \
739937 MODEL_INTEGRIT PARSE zero valued estimated parasitics in ibis models! W2 u1 K/ [9 v9 p. V
739942 ALLEGRO_EDITOR SHAPE zcopy xhatch shape creates oversize copy
5 K" I, S. n% }; g5 I/ a3 c+ u- j740133 ALLEGRO_EDITOR DRC_CONSTR Same net DRC Update from Analysis Modes runs forever.
: Z& f: n& A w1 W740281 ALLEGRO_EDITOR OTHER Jumper components where were placed in PCB disappeared
4 z; D- T' {; q+ ^, M( \* ~- G( t: R740309 SIP_LAYOUT DIE_EDITOR Moving a die pad in DIE EDITOR on G69A_U1 causes the die pads to rotate 90 degrees from the design.
1 Z4 Q, ~" [1 g- Y5 H8 Y740399 ALLEGRO_EDITOR COLOR Cannot automatically load custom color palette in 16.2
5 P- j( M5 f" z; \' _741210 ALLEGRO_EDITOR DATABASE Edit >Move; spin creates 'connect record not found' message; p, u* s4 A' f: V
741307 ALLEGRO_EDITOR PADS_IN Shapes on some layers is not getting translated from PADS into Allegro0 I l/ w, m9 c9 V2 V9 { ^
741313 ALLEGRO_EDITOR DRC_CONSTR Add connect slow in 16.3
( P" F6 j2 t2 ~2 ^% [6 U- T- a741778 ALLEGRO_EDITOR COLOR Color pallete in 16.3 is not expanding when maximize dialog) S3 \: Z, ^, ]+ ^. f
741910 ALLEGRO_EDITOR PADS_IN unable to translate PADS ascii to brd, e" _! _7 t' a" M# o( r, h
741939 ALLEGRO_EDITOR PADS_IN PADS to Allegro Translation fails or hangs.
& }4 y' L5 D/ J+ {741980 ALLEGRO_EDITOR PARTITION Import of parition does not import etch or vias.! A; m! i7 z, Y
742676 ALLEGRO_EDITOR SKILL Tpoint cannot be moved by using skill.9 b; S/ w4 E! Q6 R* m/ S
743161 ALLEGRO_EDITOR SCHEM_FTB Netrev crashing when importing netlist into board file." h. N8 W' o! x0 E4 s: Z
743235 ALLEGRO_EDITOR PLACEMENT Allegro crashes when unmatching comp in placement replicate.
8 p$ m- D# |; X2 W743243 CONSTRAINT_MGR TECHFILE Closing CM destroys tcf values when they are set to locked using fObjectNOTReadOnly7 ^1 u, @8 g s3 l/ K m
743301 SIP_LAYOUT DIE_EDITOR Edit die command creates two extra die pads. k5 H- m( h: o# p" _0 Z( U; d+ W
743316 CONSTRAINT_MGR DATABASE With Allegro 16.3 Constraint manager takes to long to update
4 a+ s( N! w8 a1 A! ]# v743553 CONSTRAINT_MGR OTHER Net disappears if we cancel the line width edits in CM
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发表于 2012-1-11 21:45
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