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Cadence SPB OrCAD 16.60.016 Hotfix | 853 mb! e" {0 z6 P; B
DATE: 09-27-2013 HOTFIX VERSION: 016
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! w& U! R6 P5 p===================================================================================================================================
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: a- p5 t+ Y0 A; T* `5 r0 }8 R( ZCCRID PRODUCT PRODUCTLEVEL2 TITLE
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===================================================================================================================================+ `5 p3 P1 r& Y5 k% B! d
- W" R' c" ~5 \1 C f# ~548538 CAPTURE NETLIST_ALLEGRO Enhancement:Include mechanical parts in Allegro netlist
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1076579 CAPTURE GENERAL Display value only if value exists
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1083904 FSP GUI Need Filter in Change FPGA dialog to select desire FPGA from the long list.6 ]4 X5 j$ L; c5 k; Q! J
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1089313 ALLEGRO_EDITOR INTERFACES Allegro Export PDF requires similar setup options as DE-HDL Export PDF for layer visibility
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1095728 ALLEGRO_EDITOR EDIT_ETCH Slide to grab adjacent elements when extend selection is enabled
9 K2 L, M9 D4 r) m: e3 Z- Q- C ~$ O2 w! Q8 g/ g1 S8 y
1102698 SIG_INTEGRITY ASSIGN_TOPOLOGY ECset will map on single ended nets but fails when the two nets are define as a diff pair.( E8 [& j8 E5 r7 K1 \
0 o* F& _, H9 E4 |1 U- |2 V1104071 SIG_INTEGRITY REPORTS Shape Parasitic value changes for bottom shape for changes in top shape
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1117731 FSP POWER_MAPPING Ability to sort in Power Regulator forms
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3 H. S( v) g: o! c1 F1121539 FSP CONFIG_SETTINGS Cannot configure special FPGA pins (temperature diodes)
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' z" D0 r7 ~' O* F& Q* ]1122721 FSP MODEL_EDITOR Partial copy-paste overwrites the complete cell in XML Editor
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5 o+ b8 x6 p; Y% |. W/ `* R" X) I1 @! y1123238 FSP TERMINATIONS Report functionality for terminations defined in the complete design.- j5 a" d v: g) u
# U% Z F+ Y v. B1 F2 O6 j- z1123364 FSP GUI Clicking on column header should sort the column.
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. A2 Y3 m. n. p( [- L7 O1123403 FSP EXTERNAL_PORTS Improper checkbox selection for 緿o Not Connect?or 縀xternal Port?column: _$ |6 ^; ~4 }
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1125611 CONCEPT_HDL OTHER display unconnected pin in schematic pdf.( I9 h/ L# t: {
! _% o1 I9 q7 Z1129871 ALLEGRO_EDITOR INTERACTIV Wire Profile Editor can't read mcmmat.dat in working directory.. J: Z4 x. `0 R
3 `) w3 e7 U1 {1133688 ALLEGRO_EDITOR GRAPHICS Enhancement request to enable 3D Viewer to show STEP model from .dra file.7 m2 a7 O$ P! J# w
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1141747 ALLEGRO_EDITOR GRAPHICS 3D view dooesnot displays height if step_unsupported_prototype variable set
7 D7 F2 b* B' {! d4 _0 u. y! i5 j" M' O* E
1142215 SIG_INTEGRITY SIMULATION PULSE_PARAM set on DiffPair wasn't used for designlink simulation.3 m, K+ v, l' R- c, i2 w
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1142798 ALLEGRO_EDITOR INTERFACES Step file output is incorrect in step viewer when composed of arcs and line.' N: U7 P8 ]; @ p: e' x$ F
- U1 f& w* ~; {1142894 FSP GUI Ability to RMB on a header and select `Hide Column?
; C7 X( n3 S% R8 Q4 P) i: m1142940 FSP EXTERNAL_PORTS Issue with checking/unchecking "Do not connect" and "External port" cells. J" D8 B6 C, a+ J( K* O
: `4 E! q4 q3 `' v& b1142949 CONCEPT_HDL SKILL Usage of "Preferences > License Settings?in FSP
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2 z$ j: `- Z W5 H7 S1 n9 ?- U1143091 SIP_LAYOUT SYMB_EDIT_APPMOD symed: When AddPins is used to add pins to a co-design die, those pins are not output as bumps in the die abstract/ r* @0 G. l8 l
. a9 R" c3 A( C% i1144371 CONCEPT_HDL COMP_BROWSER Component Browser search results are inaccurate1 `- J/ F. W# S. g+ m$ @
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1145033 ALLEGRO_EDITOR PLACEMENT When aligning components with options in Placement mode displays no busy indicator+ ~) R- T: |( i8 N
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1145286 CONCEPT_HDL CORE Directive required for switching off the console4 ] e$ a) c3 E/ @
+ p% L9 J# p, I) ?; _( w1145800 ALLEGRO_EDITOR GRAPHICS Spurious odd lines are shown in shapes and text that are not part of the design with opengl.
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1147899 ALLEGRO_EDITOR SHAPE Autovoid two overlapping shapes that share the same net4 y; Y: _% K" [% ?6 R
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1149996 ALLEGRO_EDITOR EDIT_ETCH Routing does not follow the ratsnest 'pin to pin'.
K* I) ^) H: J3 [
# e% B9 O+ Z N' H4 \7 p1150847 ALLEGRO_EDITOR INTERFACE_DESIGN Rename of DiffPair was not retained.( `! I& U8 v! {( z5 z- z5 x" d9 T
% q8 b! {, p: ]4 K9 N1152577 ALLEGRO_EDITOR DATABASE slide removes cline seg- X4 c7 q- m" Y- w7 N9 @4 I
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1152751 CONCEPT_HDL CORE Option to double-click and copy the Netname
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, }1 ]! v9 C4 y1 A/ a1153220 ALLEGRO_EDITOR INTERFACES ENH: option to supress header/footer during PDF Export8 T, ]/ Z. t$ ~4 E
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1153625 ALLEGRO_EDITOR INTERFACES If Symbol has place bound bottom, the step model shows incorrect placement.1 e9 p4 A' ?3 ?
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1153813 CONCEPT_HDL CORE Spaces should not be allowed in the signal name entry form1 K! n8 U* J8 G+ P% \' |
3 i s1 A$ P" R7 ^; ?2 n' B6 N1153857 CONCEPT_HDL CORE Changing different power symbol should maintain the schematic level properties.5 ?. e6 w( o. j$ U3 g
) a- G+ U6 l4 k+ R1155161 CONCEPT_HDL CORE Add Signal name: Suggestion box overlaps with the typed signal name that is typed
7 {- @% ]' I) i6 k; e- f3 \
& @6 [. D& H) c5 X9 ?# Y1155922 CONCEPT_HDL OTHER How can I use the batch mode for PDF Publisher and print a variant overlay?
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$ U7 N5 x" n5 c: S3 N% @1156858 ALLEGRO_EDITOR PADS_IN PADS Translator: Missing drill on square PTH padstack F2 Q0 T& T0 Z
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1157362 APD 3D_VIEWER Need a way to color multiple nets in 3D viewer from APD/SiP.
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/ F$ x+ K5 L2 h1158130 CONSTRAINT_MGR ANALYSIS Constraint Manager do not display the Cumulative Result in Reflection Simulation
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1158210 ALLEGRO_EDITOR SHAPE SIP Layout happens crash while users move the shape with route keep-out/ M, X, ?) g, Q# [( v; d
+ c6 z# r/ z! W5 h; H1158452 SIG_INTEGRITY GEOMETRY_EXTRACT CPW differential traces are not extracted as coupled when they are routed at an angle
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1158827 ALLEGRO_EDITOR EDIT_ETCH Slide a via in pad automatically add cline back to via to pin.
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& k2 I5 t l$ B( R: S9 F+ g! l: n: _1158871 PCB_LIBRARIAN IMPORT_CSV PIN TEXT is not automatically added when importing the .csv file# P9 {4 F' X& Q3 ^; p, B( X
U X0 m; Z, p/ U1159738 ALLEGRO_EDITOR INTERACTIV Selecting the Cancel button in the Text Edit command does not cancel the text." v" t" h, S% e/ g
- q/ y" Y4 o1 `; H1159878 SIG_EXPLORER OTHER Ecset mapping dont follow topology template
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1159971 ALLEGRO_EDITOR MANUFACT Allegro PDF Publisher requires ability to control film record sequence when generating the combined PDF file9 a; U; v8 D; X; ^( K
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1160017 SIP_LAYOUT DIE_ABSTRACT_IF Add text to clarify shrink operation1 t2 K8 P% E4 n) c/ L
1 r. c# a; V6 |# g3 y( D1160507 APD EDIT_ETCH Script not playing back what was recorded when sliding lines2 G7 ]+ v# K/ \- v
' d! b8 C8 }0 q: l- t1161261 ADW TDO-SHAREPOINT Schema for TDO-SP fails on Japanese OS: ? }( V- H0 Q* `
6 c2 l) u7 `# z, A( y( \5 Z" ^. T1161538 CONCEPT_HDL CORE Espice model value edited in DE HDL & then netlisting done, but it doesnt changes the earlier assigned model in Allegro
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2 T: Y2 p% S% q1161636 ALLEGRO_EDITOR DRAFTING need new function for PDFout : hatching shape
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1161777 ALLEGRO_EDITOR OTHER default line width for PDF output0 ^, x) [! G" ?- |. I, E3 ^
* R2 E" `& x8 t, l1 d3 F6 i1162383 CONCEPT_HDL CHECKPLUS Checkplus not using $CDS_SITE/custom_help and $CDS_SITE/custom_rules_include directories.
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1162562 CAPTURE STABILITY Capture crash on second attempt of pspice netlist creation in 16.6
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5 Y% u! K6 U7 K# ?) S0 f, G1 f4 m1162629 FSP PROCESS "Load Process Option" under Run does not work properly3 P: K, O: v- q/ [& P9 v
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1162686 CONCEPT_HDL CORE Changing NET_SPACING_TYPE to display both shows up with $NET_SPACING_TYPE6 [. z8 I, l6 d5 l0 L2 [2 f
7 t3 x5 E: H' m) `8 ]
1163149 ALLEGRO_EDITOR DATABASE Autosilk creates Illegal arc to corrupt database
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7 g; ]8 A$ r* D. X2 u1163439 ALLEGRO_EDITOR COLOR Duplicate Views Listed in Visibility Tab.
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: _5 H* t* v; g1163521 CONCEPT_HDL COMP_BROWSER System Architect crahes on replace- p3 Q2 I0 r; _" \+ b M g2 P* P
2 r% Q9 M3 ^% ^9 o# Q9 q1163709 CONCEPT_HDL CONSTRAINT_MGR Loosing Diffpairs when reimport block or restore from definitioin* N$ o, _" A4 n( O' j% f4 G
7 ^! F7 E _( T. j# q: t3 z1163902 APD EXPORT_DATA Q- In APD > File - Export - Board Level Component, check otion of delay reports is not working, is it ?
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# U4 q* V3 }+ T I. J1164337 CONCEPT_HDL CORE Cannot delete attribute filter value in PDF > General > Attribute Filter list0 [ t" o8 Z& y* c0 r1 s
0 Y: g0 m/ ~% x( S7 i% t1164365 ALLEGRO_EDITOR INTERACTIV Symbol not selected for Move because Symbol Pin number selected in options tab not available on symbol
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- e/ `! t9 Z! P3 s5 J1164769 APD VIA_STRUCTURE The replace via structure command does not accept a single canvas pick.
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1165026 ASI_SI GUI EMS3D exist in Via Model Setup of SI base.1 h2 m6 v- k& y, j
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1165561 CAPTURE DRC File > Check and Save clears waived DRCs, L- L# {2 ^5 g' O+ Z' v/ E8 \* y6 Z9 \/ \
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1165631 CAPTURE STABILITY Capture crash in the hierarchy tab of Project Manager window
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9 A: s9 j$ A( L ~( d: \( Q' V5 A1165836 SIG_INTEGRITY GEOMETRY_EXTRACT Some nets has no result at Bus Simulation and Comprehensive simulation.(update): t1 x2 `4 h5 K! U( M
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1165911 FSP PROCESS Editing group name in protocol causes incorrect Process option checked; ^5 x* I2 b" F' y
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1166026 ALLEGRO_EDITOR DATABASE Running DB Doctor removes net name from vias$ \6 |( W2 b6 a2 x3 u3 s
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1166034 SIP_LAYOUT OTHER SiP - Cline Change Width command enhanced to have selection by polygon not just rectangle
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" \ B0 \7 F7 J, r$ O1166074 GRE CORE GRE crashes during planning phases
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1166319 ALLEGRO_EDITOR PLACEMENT Swap not succeed- x0 J! q: t4 U+ Y2 T0 R% H; M7 w
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1166484 SIP_LAYOUT WIREBOND Bondfinger "Align With Wire" problem during move- a7 Z) z* X* y7 |1 x2 P
' X$ n6 _# x$ w( A7 ~' A: b: u. ^1166530 ALLEGRO_EDITOR INTERACTIV Bug: Mirror in Placement Edit resets the options tab for Edit > Move! H; ^& p* S' E# K h; e. ~
5 y5 G) Q; t2 [ o" q6 e2 u8 O1 [& z y1166819 CONCEPT_HDL CORE Cadence DEHDL Text Size Issue
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1167847 CAPTURE PROPERTY_EDITOR Implementation name length greater than 31 character causes capture crash
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# k9 a% b( I$ o3 X3 U1167887 F2B OTHER Improve message on symbol to schematic generation$ o8 Y$ ?6 T6 T* B) v: F4 P
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1168369 F2B DESIGNVARI Variant don縯 appear in increasing order while Annotate.) |% q9 l- P. R1 K* c: h
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1168629 APD OTHER Do we have Skill command which is equivilant to Change Characteristics operation of a Wire Bond in APD
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& t$ z7 a) C3 s3 |1168678 ALLEGRO_EDITOR NC Drill Figure will be changed wrong layer when some subclass was deleted in SPB165S045.
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1168798 ALLEGRO_EDITOR INTERACTIV Enh - Allow user the ability to set the visibiity layer of refdes while moving the symbol rather than fixing it to silk
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1168830 ALLEGRO_EDITOR DRC_CONSTR missing DRC-marker for package to package check2 {9 q! m3 [# z
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1168864 ALLEGRO_EDITOR CREATE_SYM Saving the dra after Shape Expand/Contract throws warning 'Sector Table is not empty2 W4 O0 W4 A9 Z
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1169213 PSPICE SIMULATOR Parametric sweep is giving incorrect reuslts: N. A0 \, ^9 {9 m# M& W2 I1 e3 [
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1169436 FSP FPGA_SUPPORT Add support for Cyclone V CSX and CST parts
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1170108 ALLEGRO_EDITOR INTERACTIV Enhancement to preserve Rat T location for Topology assigned schedule
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7 ^" n3 ~# D F+ j! L8 O) o E( E1170313 SIP_LAYOUT LOGIC scm adding additional pin names and unassigned property to codesign die chips file* Y4 x( T! p/ h5 J1 Z7 X
" D" c$ Q4 }* G; Z9 C& B/ k1171136 CONCEPT_HDL CORE Page Number should also be displayed in Import Design Window./ H& m' n3 J: U+ p
5 ~4 i4 C2 N" w1171747 ALLEGRO_EDITOR PLACEMENT Allegro crashes when doing a gate swap between components6 v1 N9 H3 p# f* I, h- j! B
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1172183 ALLEGRO_EDITOR INTERACTIV Alignment modules fails on equal spacing% V7 u9 f& x7 F% G4 \" r g
! F% f# o7 A1 v' E1173183 ALLEGRO_EDITOR DRC_CONSTR Undesired Same net DRC for overlapping Pin and Via% g1 S! o) z& J a$ k5 V
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1174067 ALLEGRO_EDITOR DRC_CONSTR Soldermask to shape drc does not show if the layer is a PLANE.3 \. H7 Y$ G( I: j, C5 J) S
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1174338 ALLEGRO_EDITOR PLACEMENT preview has rotated pads, ]; X& E }( B3 j' {
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1175307 CONSTRAINT_MGR ANALYSIS CMGR fails to report RPD DRC for accuracy 4 - mm
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1175537 ALLEGRO_EDITOR REPORTS net loop report crashes Allegro. Design specific: t, S1 _. p; n
0 P" Q6 m0 j k. ]+ e8 \8 l1176126 ALLEGRO_EDITOR INTERFACES 3D viewer doesnot change models units dynamically d" |: f" |! R' L6 f+ E
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1176281 CONCEPT_HDL CORE Option to Auto-hide excluded modules
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- B; t& r/ H; I! I P7 }4 @1 Q8 e- h5 W. H1176413 ALLEGRO_EDITOR MANUFACT Q - testprep parameter settings is not retained, what could be the cause..
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. x3 _9 E% x7 m+ x) b6 t* t1176791 ALLEGRO_EDITOR GRAPHICS Spurious odd lines are shown in shapes and text that are not part of the design with opengl; w1 R& A* P( v- t) |% w
3 O! \. _+ S# ^5 d* w1178052 ALLEGRO_EDITOR SHAPE SIP crashes during shape degassing. h) m! M6 q& a! b" J
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1178158 ALLEGRO_EDITOR INTERFACES Export step file creates step file of same height
5 N5 o r% e* ~
' ^ E5 N% v- X2 ]* [( \1178201 ALLEGRO_EDITOR GRAPHICS Large oval pads rendered as oblong hexagons in the 3D viewer/ m8 G$ U5 R/ Y+ I9 b0 V
: c$ Y! n" r8 K9 P0 o1178671 ALLEGRO_EDITOR GRAPHICS 3D Viewer in package symbol editor not displaying correct place bound shapes.
. F1 |6 q, P1 K0 I6 J+ R/ ~* L, I. a# b! n* g. Z7 Y
1178725 ALLEGRO_EDITOR OTHER With fillets present, rat lines do not point to the closest endpoint.4 u) e- a) \# i4 A8 [ m4 R
2 I2 ^1 v/ p) ~. g1178972 CONSTRAINT_MGR ANALYSIS The Cross-Section's parameters was not applied immediately after importing a DCF on the Constraint Manager.
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1179093 ALLEGRO_EDITOR SHAPE Dynamic Shape for GROUND net on TOP Layer is corrupted and is not voiding correctly in certain areas." B ~2 d+ v. L) d0 D
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1179109 ALLEGRO_EDITOR OTHER DXF importing makes figure shift in 16.5&16.6 version it is ok in 16.3 version% ~! Y6 U, }1 e1 I0 ?& x- l1 p
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1179571 ALLEGRO_EDITOR ARTWORK Artwork crash and artwork log report Aparture missing
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$ p# n; W9 u2 r1179636 SPECCTRA ROUTE Route Automatic will not start if NET_SHORT are attached to a mec-pin5 Z$ e1 }4 f2 D2 L) F! G/ m; r
" c9 a& C7 [" g" n2 q1179659 SIP_LAYOUT DIE_EDITOR die edit on co-design die losing c4 bumps6 |1 H% ^; ]+ g: W H5 o
7 n2 g* n4 C7 b( T
1180306 ALLEGRO_EDITOR ARTWORK When trying to create Artwork the tool crashes with no error messages just a little X box8 c0 ]$ k! c; z( p
- ]2 o2 D1 w( o4 g7 j" t- u1180573 ALLEGRO_EDITOR ARTWORK If one layer has warning, all artwork films are "created with warning".
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1180960 SIP_LAYOUT PLACEMENT swap function is not swapping logical paths in sip layout!
8 F+ Q1 D2 t" O* j+ T. t, {8 K! r% L# W% y% W
1182534 ALLEGRO_EDITOR SKILL axlLayerPrioritySet() not working with v166 s013 and up
( m4 p# ^" K' X w9 i% W2 P; N5 F3 k( P* x- K$ @
1182560 ALLEGRO_EDITOR PLOTTING Creating plot 2nd time casues Allegro to crash7 ?) x1 {, k( _ s
% [4 z6 j) a# e" k' f
1182616 ALLEGRO_EDITOR PLACEMENT Application crashes when attempting to place a high pin count BGA
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4 ?+ b8 I Q, v& H: f1183752 CONCEPT_HDL CORE Unable to modify location properties within a read-only hierarchical block
2 v! e# c3 K# z
. c! @# ^3 o2 N' e9 h$ X8 m- `1183774 SIP_LAYOUT DIE_EDITOR Die Refresh hangs* S& D- Z: c I5 N$ X
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1184178 CONCEPT_HDL CONSTRAINT_MGR Ecset xnet members lost from electrical class when restore from definition of subblocks$ Q. l/ U; P2 ^( s) n& M- |9 Z
. H {" p9 y' s- M1 r1184787 ALLEGRO_EDITOR EDIT_ETCH Allegro SPB166 s 015 crashes during normal add connect function.7 c/ }2 W. N4 Q% b$ t) j" v: V) t; g
. q- T6 k* c4 F
# c5 L9 e6 N/ J' i/ g3 _Cadence SPB OrCAD 16.60.016 Hotfix
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发表于 2013-10-5 20:59
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