EDA365电子工程师网

标题: VHDL 8位数码管扫描显示电路(原创) [打印本页]

作者: zgq800712 时间: 2008-12-1 15:47
标题: VHDL 8位数码管扫描显示电路(原创)
module _7segscan(clk,dataA,dataB,dataC,dataD,segd,sel);
input [7:0]dataA;
input [7:0]dataB;
input [7:0]dataC;
input [7:0]dataD;
input clk;
output [7:0]segd;
output [3:0]sel;
reg [7:0]segd;
reg [3:0]sel;
reg [1:0]i;
[email=always@(posedge]always@(posedge[/email] clk)
begin
i<=i+1;
case(i)
  0:begin segd=dataA;sel=8;end
  1:begin segd=dataB;sel=4;end
  2:begin segd=dataC;sel=2;end
  3:begin segd=dataD;sel=1;end
  default:begin segd=8'bx;sel=0;end
endcase
end
endmodule

这个是Verilog 的，VHDL的没有；；；
刚学VHDL，很多概念；分析方法多不知道；
有时候把问题想的很复杂，让自己陷入困境；更难写了
VHDL的8位数码管扫描显示电路有头绪了，但还是写不出来；没有输入端口直接显示会了；
但是有输入。老是把它想成锁存，每位多要带锁存器硬件电路；
   写软件的时候老是想着硬件电路，怎么样也想不出办法

今天早上在写。。。

zyunfei 威望 +10 谢谢版主，不过上面的不是原创内容；今天下午用VHDL写了个8位数码管扫描电路；编译通过了。不过有不少waring；

一个人孤军作战一个字累！！！更更何况我是新手；新手也寂寞啊
Warning: Timing Analysis does not support the analysis of latches as synchronous elements for the currently selected device family

Warning: Found pins functioning as undefined clocks and/or memory enables Info: Assuming node "CLK" is an undefined clock

不去掉仿真设置下的的CHECK OUTPUTS仿真的时候会出现如下错误：请高手指点一二：
Error: Simulation results from F:/VHDL/LED_SCAN/db/LED_SCAN.sim.cvwf (0 ps to 1.0 us) do not match expected results from vector source file F:/VHDL/LED_SCAN/LED_SCAN.vwf

由于不会做仿真最后没有仿真，序列信号多不会赋值，晕死了；大家会就教教我把!!!

数码管是共阴的，位码大家自己看下是不是对应起来了！！
此程序不带译码功能，直通输出；

如果你使用的是7064（64个宏），那 Error: Can't fit 67 registers in device ;哈哈，资源不够

下面是完全自己写的源码，没有在目标板上试验过。复制代码的朋友要注意了！！！

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;

ENTITY LED_SCAN IS
PORT(
SEG7IN:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
SEL:IN STD_LOGIC_VECTOR(2 DOWNTO 0);
CLK:IN STD_LOGIC;
SEG7OUT:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
   SCAN:OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
  );
END LED_SCAN;
ARCHITECTURE BEHAV OF LED_SCAN IS
SIGNAL cnt8:INTEGER RANGE 0 TO 7;
SIGNAL TEMP0,TEMP1,TEMP2,TEMP3,TEMP4,TEMP5,TEMP6,TEMP7:STD_LOGIC_VECTOR(7 DOWNTO 0):="00000000";
BEGIN
PROCESS(CLK)
BEGIN
IF (CLK'EVENT AND CLK='1') THEN
cnt8<=cnt8+1;
END IF;
END PROCESS;

PROCESS(CLK)
BEGIN
IF (CLK'EVENT AND CLK='1') THEN
CASE SEL IS
WHEN "000"=>TEMP0<=SEG7IN;
WHEN "001"=>TEMP1<=SEG7IN;
WHEN "010"=>TEMP2<=SEG7IN;
WHEN "011"=>TEMP3<=SEG7IN;
WHEN "100"=>TEMP4<=SEG7IN;
WHEN "101"=>TEMP5<=SEG7IN;
WHEN "110"=>TEMP6<=SEG7IN;
WHEN "111"=>TEMP7<=SEG7IN;
WHEN OTHERS=>NULL;
END CASE;
END IF;
END PROCESS;
process(cnt8,TEMP0,TEMP1,TEMP2,TEMP3,TEMP4,TEMP5,TEMP6,TEMP7)
BEGIN
CASE cnt8 IS
WHEN 0=>SCAN<="01111111";SEG7OUT<=TEMP0;
WHEN 1=>SCAN<="10111111";SEG7OUT<=TEMP1;
WHEN 2=>SCAN<="11011111";SEG7OUT<=TEMP2;
   WHEN 3=>SCAN<="11101111";SEG7OUT<=TEMP3;
   WHEN 4=>SCAN<="11110111";SEG7OUT<=TEMP4;
   WHEN 5=>SCAN<="11111011";SEG7OUT<=TEMP5;
   WHEN 6=>SCAN<="11111101";SEG7OUT<=TEMP6;
   WHEN 7=>SCAN<="11111110";SEG7OUT<=TEMP7;
   WHEN OTHERS=>NULL;
END CASE;
end process;
END;

现在又发现没有带一个写入使能；所以就加WR信号,当WR为1的时候允许写入,当7位写完后置0,此后不管 SEG7IN  ,SEL  为什么多不会进行写入;
这个东西断断续续搞了我一下午,  哎,,很久没有这么投入了的做一件事情了!!!
现附上源代码:
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;

ENTITY LED_SCAN IS
PORT(
SEG7IN:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
SEL:IN STD_LOGIC_VECTOR(2 DOWNTO 0);
CLK,WR:IN STD_LOGIC;
SEG7OUT:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
   SCAN:OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
  );
END LED_SCAN;
ARCHITECTURE BEHAV OF LED_SCAN IS
SIGNAL cnt8:INTEGER RANGE 0 TO 7:=0;
SIGNAL TEMP0,TEMP1,TEMP2,TEMP3,TEMP4,TEMP5,TEMP6,TEMP7:STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN
PROCESS(CLK)
BEGIN
IF (CLK'EVENT AND CLK='1') THEN
IF WR='1' THEN
CASE SEL IS
WHEN "000"=>TEMP0<=SEG7IN;
WHEN "001"=>TEMP1<=SEG7IN;
WHEN "010"=>TEMP2<=SEG7IN;
WHEN "011"=>TEMP3<=SEG7IN;
WHEN "100"=>TEMP4<=SEG7IN;
WHEN "101"=>TEMP5<=SEG7IN;
WHEN "110"=>TEMP6<=SEG7IN;
WHEN "111"=>TEMP7<=SEG7IN;
WHEN OTHERS=>NULL;
END CASE;
END IF;
END IF;
END PROCESS;
PROCESS(CLK)
BEGIN
IF (CLK'EVENT AND CLK='1') THEN
cnt8<=cnt8+1;
END IF;
END PROCESS;
process(cnt8)
BEGIN
CASE cnt8 IS
WHEN 0=>SCAN<="01111111";SEG7OUT<=TEMP0;
WHEN 1=>SCAN<="10111111";SEG7OUT<=TEMP1;
WHEN 2=>SCAN<="11011111";SEG7OUT<=TEMP2;
   WHEN 3=>SCAN<="11101111";SEG7OUT<=TEMP3;
   WHEN 4=>SCAN<="11110111";SEG7OUT<=TEMP4;
   WHEN 5=>SCAN<="11111011";SEG7OUT<=TEMP5;
   WHEN 6=>SCAN<="11111101";SEG7OUT<=TEMP6;
   WHEN 7=>SCAN<="11111110";SEG7OUT<=TEMP7;
   WHEN OTHERS=>NULL;
END CASE;
end process;
END;

下面有仿真图

附上一张RTL

[ 本帖最后由 zgq800712 于 2008-12-3 20:23 编辑 ]

RTL.GIF (139.95 KB, 下载次数: 48)

SIM.GIF (28.91 KB, 下载次数: 36)

防真图

作者: zyunfei 时间: 2008-12-3 14:26
给你顶下，虽然我有的还看不懂哈哈

以后请多多指教啊！

作者: zyunfei 时间: 2008-12-3 14:26
你不是已经学会Verilog 了吗？为什么还要用VHDL啊？！

作者: 长杉长杉 时间: 2010-1-28 18:03
太长了

作者: sutee7907 时间: 2010-1-29 15:05
library IEEE;--共阳极显示76543210
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY seg7 IS
   PORT (
   clk : IN std_logic;
   rst : IN std_logic;
   dataout : OUT std_logic_vector(7 DOWNTO 0); --各段数据输出
   en : OUT std_logic_vector(7 DOWNTO 0)); --COM使能输出
END seg7;

ARCHITECTURE arch OF seg7 IS

signal cnt_scan : std_logic_vector(15 downto 0 );
signal data4 : std_logic_vector(3 downto 0);
signal dataout_xhdl1 : std_logic_vector(7 downto 0);
signal en_xhdl : std_logic_vector(7 downto 0);
begin
  dataout<=dataout_xhdl1;
  en<=en_xhdl;
process(clk,rst)
begin
   if(rst='0')then
  cnt_scan<="0000000000000000";
  elsif(clk'event and clk='1')then

   cnt_scan<=cnt_scan+1;
   end if;
end process;

process(cnt_scan(15 downto 13))
begin
case cnt_scan(15 downto 13) is
   when"000"=> en_xhdl<="11111110";
   when"001"=> en_xhdl<="11111101";
   when"010"=> en_xhdl<="11111011";
   when"011"=> en_xhdl<="11110111";
   when"100"=> en_xhdl<="11101111";
   when"101"=> en_xhdl<="11011111";
   when"110"=> en_xhdl<="10111111";
   when"111"=> en_xhdl<="01111111";
   when others=> en_xhdl<="11111110";
  end case;

end process;

process(en_xhdl)
begin
case en_xhdl is
   when "11111110"=> data4<="0000";
   when "11111101"=> data4<="0001";
   when "11111011"=> data4<="0010";
   when "11110111"=> data4<="0011";
   when "11101111"=> data4<="0100";
   when "11011111"=> data4<="0101";
   when "10111111"=> data4<="0110";
   when "01111111"=> data4<="0111";
   when others => data4<="1000";
  end case;
end process;

process(data4)
begin
  case data4 is
   WHEN "0000" =>
   dataout_xhdl1 <= "11000000";
   WHEN "0001" =>
   dataout_xhdl1 <= "11111001";
   WHEN "0010" =>
   dataout_xhdl1 <= "10100100";
   WHEN "0011" =>
   dataout_xhdl1 <= "10110000";
   WHEN "0100" =>
   dataout_xhdl1 <= "10011001";
   WHEN "0101" =>
   dataout_xhdl1 <= "10010010";
   WHEN "0110" =>
   dataout_xhdl1 <= "10000010";
   WHEN "0111" =>
   dataout_xhdl1 <= "11111000";
   WHEN OTHERS =>
   dataout_xhdl1 <= "00000011";

   END CASE;
   END PROCESS;

end arch;

作者: wangp 时间: 2010-6-16 19:44
为什么显示expected an integer value?

欢迎光临 EDA365电子工程师网 (https://bbs.elecnest.cn/)