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求救—谁能帮忙改一改

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发表于 2009-10-31 17:10 | 只看该作者 回帖奖励 |倒序浏览 |阅读模式

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library ieee;5 D" W5 D+ j, ]
use ieee.std_logic_1164.all;2 R$ l' d' [; _/ L) a. O& y4 [( H
use ieee.std_logic_arith.all;
1 k" n3 V$ {: [9 Ruse ieee.std_logic_unsigned.all;/ p" o. q' ?* `7 B; b8 y
entity hour is
+ {, {8 Y8 ~# j* O: z port(clk_h,clk_t,tp_h,res_h:in std_logic;1 {1 O: T2 R# X5 r9 M4 f
  hset:in std_logic;0 P/ h2 ]* f8 c  ?
  sig_h:in std_logic_vector(2 downto 0);" F( r1 R' \' ^& i% @
  din_h1ut std_logic_vector(3 downto 0);
! A! t# P" W4 Y3 z3 _  din_h0ut std_logic_vector(3 downto 0);
- {$ l+ k0 U7 n8 n  pmut std_logic;
0 C' @/ F- f3 ?5 _$ g) X8 Z3 n  cp_h:out std_logic);
$ N1 p1 z" {; N+ J/ m. t' O7 I% ]  + q7 W) R3 f" d6 l/ s
end hour;* _4 Y& g' }3 L( s. t2 d  `! T$ _
architecture behav of hour is
+ X, n# `7 x9 M8 x) Zsignal clk:std_logic;
; c" j9 E* M' `' X9 @8 hbegin
+ K/ @/ G3 l/ R0 \* U    process(clk_h,clk_t,tp_h,sig_h,res_h,hset)' L: w* L# [# j+ ?
     variable cq1,cq2,cq3,cq4:std_logic_vector(3 downto 0);# D2 I2 I: `5 p! T& F
     variable co1:std_logic;# v' B5 l- r5 y' {# h7 F
     variable co2: std_logic_vector(7 downto 0) ;
6 m$ x, k1 l# N( |- l3 o  o5 O3 R% m   begin : J& e/ D% {  E/ U$ g, K
    if sig_h="001"and tp_h='1' then clk<=clk_t;
7 w) u) c7 L) J) _# c8 l/ r) y% V   else clk<=clk_h;
# W  p8 v9 P4 s$ w. Q9 w, b% \   end if;
3 c* e, j" {/ [) Y7 M) f    if res_h='1' then cq1:="0000";cq2:="0000";cq3:="0000";cq4:="0000";co2:= (OTHERS =>'0');( [" [1 H, o9 G; Q7 v8 y. G+ d: p
       elsif  clk'event and clk='0' then cq1:=cq1+1; cq3:=cq3+1;8 V: P4 E# Z% w6 ^% j" h2 J
      if cq1="1010" then cq2:=cq2+1;cq1:="0000";
# u+ ~- i/ u" |8 r! M' B% d            end if;
6 M5 [" }/ Z- }) D. h) l            if  cq2="0010" and cq1="0100" then$ X) P( G0 E1 [$ s1 J- w0 D/ s  F
    cq1:="0000";cq2:="0000";5 w- H4 H8 x! ?! J, g3 l0 l
    co1:='1';! ]5 c* D+ p5 `3 w
   else co1:='0';7 b" d# x2 ^7 v
      end if;
  o3 a, Y2 p; y, N+ U      if cq3="1010" then
" _  s2 m2 Q1 C+ }/ i      cq4:=cq4+1;
7 }" {% J1 X  U7 Q% Y      cq3:="0000";
, g# k1 {) Z3 ?, m7 `    end if;
* N7 w7 w" Y  |( N: |6 y2 W% b# `   if cq4="0001" and cq3="0010" then
* b' t9 d+ n1 m& f3 x* E. W( M8 R         cq3:="0000";cq4:="0000";co2:=co2+1;
# `8 G' F9 o$ \/ Z& S, |      end if;
- O& z3 \! o5 ?7 o4 ], u3 m    end if;# f9 t; f5 A- k8 l
  if hset='1' then   
: H1 K  Y* I" U' F8 K* _          din_h1<=cq2;din_h0<=cq1;cp_h<=co1;
0 B5 p! @$ r! t3 L0 c* |- ?         else
8 N) T0 k# a& [1 ^) q           if co2(0)='1' then
1 B5 V+ ~. m9 v0 O+ b  R- l             if cq3="0000" and cq4="0000" then cq3:="0010";cq4:="0001";pm<='0';
1 S. Y8 Z/ O: @) l( v9 g; T             end if;0 f0 v2 O2 s/ Y. t; c
             pm<='1';
8 r, o& T2 s7 B  h9 ?            else pm<='0';: C, ~( c  Q5 G$ V
            end if;
* O- l! G5 J2 t, }, W            if co2(0)='0' and cq3="0000" and cq4="0000" then cp_h<='1';
0 v( m) v# w' f9 v2 l& A              else cp_h<='0';
" p6 c) {( |( i             end if;
8 M1 {" T9 A. X+ x' W* `9 p4 p- O           din_h1<=cq4;din_h0<=cq3;  & [% o, B& D$ H& J: i2 v! W, a
        end if;  --12/24转换4 D0 m/ Y- D9 e; O4 A4 a. {5 R
  . o. [$ Z( ?: d& J
     end process;7 q# \" l- D3 X, {0 o4 U9 S
end behav;
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 楼主| 发表于 2009-10-31 17:10 | 只看该作者
报错:3 P; T8 V: b( j$ B6 w2 O' L
Info: *******************************************************************
9 b, P! E. {5 `0 pInfo: Running Quartus II Analysis & Synthesis; r- i% @% J3 P2 R$ Z1 t
        Info: Version 9.0 Build 132 02/25/2009 SJ Full Version
. v: c4 j. t* i# O8 x) Z: a) t) Y        Info: Processing started: Sat Oct 31 17:04:02 2009
) j7 h9 a4 l6 DInfo: Command: quartus_map --read_settings_files=on --write_settings_files=off hour -c hour0 J  s/ J# A( {0 ~* r! S- u& m7 W
Info: Found 2 design units, including 1 entities, in source file hour.vhd
, g* u% |; }0 u( J        Info: Found design unit 1: hour-behav
. Q+ A+ z+ j& B: l6 S. w9 _" G- _        Info: Found entity 1: hour
" ~0 N6 h" }6 `5 zInfo: Elaborating entity "hour" for the top level hierarchy
# c! A* D2 B4 j1 E) bWarning (10492): VHDL Process Statement warning at hour.vhd(29): signal "clk" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
* u& R( g5 F9 ^" `7 O+ BWarning (10631): VHDL Process Statement warning at hour.vhd(20): inferring latch(es) for signal or variable "pm", which holds its previous value in one or more paths through the process
9 z+ N. x$ \% n: a& kInfo (10041): Inferred latch for "pm" at hour.vhd(20)
- q8 j% w- y7 a/ w* A0 y( jError (10821): HDL error at hour.vhd(48): can't infer register for "cq4[0]" because its behavior does not match any supported register model* @6 N: S$ N* B
Error (10821): HDL error at hour.vhd(48): can't infer register for "cq4[1]" because its behavior does not match any supported register model& p+ l; P( H" P3 T- q
Error (10821): HDL error at hour.vhd(48): can't infer register for "cq4[2]" because its behavior does not match any supported register model
( L9 [! P" x, `4 rError (10821): HDL error at hour.vhd(48): can't infer register for "cq4[3]" because its behavior does not match any supported register model% P, f- ~+ V& p4 e6 `
Error (10821): HDL error at hour.vhd(48): can't infer register for "cq3[0]" because its behavior does not match any supported register model; k2 \% ^/ s( W/ x  O& B
Error (10821): HDL error at hour.vhd(48): can't infer register for "cq3[1]" because its behavior does not match any supported register model
1 w( Y" c3 R. z( i- CError (10821): HDL error at hour.vhd(48): can't infer register for "cq3[2]" because its behavior does not match any supported register model
6 b& F% ?! N6 oError (10821): HDL error at hour.vhd(48): can't infer register for "cq3[3]" because its behavior does not match any supported register model: q8 }$ _# X0 z2 S" }0 \
Error: Can't elaborate top-level user hierarchy7 {% ?3 x' O$ _! ?5 s5 M5 i
Error: Quartus II Analysis & Synthesis was unsuccessful. 9 errors, 2 warnings
$ T8 Q+ p- W; f) f) g2 f- j6 M        Error: Peak virtual memory: 184 megabytes7 w, ]3 h! _4 K" u' }* ^2 B& N
        Error: Processing ended: Sat Oct 31 17:04:04 2009
' V7 {; w- Y9 u$ L; c        Error: Elapsed time: 00:00:02
0 [; V3 b7 }- O2 Y1 w        Error: Total CPU time (on all processors): 00:00:010 U: i; Y8 I: m' n) W6 Q% m
Error: Quartus II Full Compilation was unsuccessful. 11 errors, 2 warnings
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