求救—谁能帮忙改一改

zhong0985 · 发表于 2009-10-31 17:10

EDA365欢迎您！

您需要登录才可以下载或查看，没有帐号？注册

x

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity hour is
port(clk_h,clk_t,tp_h,res_h:in std_logic;
  hset:in std_logic;
  sig_h:in std_logic_vector(2 downto 0);
  din_h1

ut std_logic_vector(3 downto 0);
din_h0

ut std_logic_vector(3 downto 0);
pm

ut std_logic;
  cp_h:out std_logic);

end hour;
architecture behav of hour is
signal clk:std_logic;
begin
process(clk_h,clk_t,tp_h,sig_h,res_h,hset)
   variable cq1,cq2,cq3,cq4:std_logic_vector(3 downto 0);
   variable co1:std_logic;
   variable co2: std_logic_vector(7 downto 0) ;
begin
if sig_h="001"and tp_h='1' then clk<=clk_t;
else clk<=clk_h;
end if;
if res_h='1' then cq1:="0000";cq2:="0000";cq3:="0000";cq4:="0000";co2:= (OTHERS =>'0');
   elsif  clk'event and clk='0' then cq1:=cq1+1; cq3:=cq3+1;
   if cq1="1010" then cq2:=cq2+1;cq1:="0000";
         end if;
         if  cq2="0010" and cq1="0100" then
cq1:="0000";cq2:="0000";
co1:='1';
else co1:='0';
   end if;
   if cq3="1010" then
   cq4:=cq4+1;
   cq3:="0000";
end if;
if cq4="0001" and cq3="0010" then
      cq3:="0000";cq4:="0000";co2:=co2+1;
   end if;
end if;
  if hset='1' then
      din_h1<=cq2;din_h0<=cq1;cp_h<=co1;
      else
         if co2(0)='1' then
         if cq3="0000" and cq4="0000" then cq3:="0010";cq4:="0001";pm<='0';
         end if;
         pm<='1';
         else pm<='0';
         end if;
         if co2(0)='0' and cq3="0000" and cq4="0000" then cp_h<='1';
            else cp_h<='0';
         end if;
         din_h1<=cq4;din_h0<=cq3;
      end if;  --12/24转换

   end process;
end behav;

zhong0985 · 发表于 2009-10-31 17:10

报错：
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 9.0 Build 132 02/25/2009 SJ Full Version
Info: Processing started: Sat Oct 31 17:04:02 2009
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off hour -c hour
Info: Found 2 design units, including 1 entities, in source file hour.vhd
Info: Found design unit 1: hour-behav
Info: Found entity 1: hour
Info: Elaborating entity "hour" for the top level hierarchy
Warning (10492): VHDL Process Statement warning at hour.vhd(29): signal "clk" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10631): VHDL Process Statement warning at hour.vhd(20): inferring latch(es) for signal or variable "pm", which holds its previous value in one or more paths through the process
Info (10041): Inferred latch for "pm" at hour.vhd(20)
Error (10821): HDL error at hour.vhd(48): can't infer register for "cq4[0]" because its behavior does not match any supported register model
Error (10821): HDL error at hour.vhd(48): can't infer register for "cq4[1]" because its behavior does not match any supported register model
Error (10821): HDL error at hour.vhd(48): can't infer register for "cq4[2]" because its behavior does not match any supported register model
Error (10821): HDL error at hour.vhd(48): can't infer register for "cq4[3]" because its behavior does not match any supported register model
Error (10821): HDL error at hour.vhd(48): can't infer register for "cq3[0]" because its behavior does not match any supported register model
Error (10821): HDL error at hour.vhd(48): can't infer register for "cq3[1]" because its behavior does not match any supported register model
Error (10821): HDL error at hour.vhd(48): can't infer register for "cq3[2]" because its behavior does not match any supported register model
Error (10821): HDL error at hour.vhd(48): can't infer register for "cq3[3]" because its behavior does not match any supported register model
Error: Can't elaborate top-level user hierarchy
Error: Quartus II Analysis & Synthesis was unsuccessful. 9 errors, 2 warnings
Error: Peak virtual memory: 184 megabytes
Error: Processing ended: Sat Oct 31 17:04:04 2009
Error: Elapsed time: 00:00:02
Error: Total CPU time (on all processors): 00:00:01
Error: Quartus II Full Compilation was unsuccessful. 11 errors, 2 warnings

		自动登录	找回密码
密码			注册

求救—谁能帮忙改一改

EDA365欢迎您！

推荐内容 /1