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DATE: 05-28-2016 HOTFIX VERSION: 071* N, q: i& a7 X3 Z+ d
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5 f" q; n/ w9 l' p' s3 @ d: U. |1 q1452838 CONCEPT_HDL CORE Apparent discrepancy between Bus names and other nets
$ J6 G1 ^( [' o2 ]! e1469146 ADW LRM ERROR(SPCODD-5): Pin '1<1>' on the following primitive instance cannot be packaged in package
5 j+ D# d6 ~& R4 `3 ^$ I1499515 ADW COMPONENT_BROWSE The Search Criteria property value is automatically being set in the ADW Component Browser
/ P. l* B3 ^- [& G# @4 F1524947 SIG_INTEGRITY SIGNOISE SI Base, PCB SI: Custom Stimulus is not recognized correctly
! G% t- t2 _) f1532162 CONCEPT_HDL CORE The Rename Signal command does not update split symbols.) }4 I$ b1 q" x6 h& g/ m+ {' t
1543997 CONSTRAINT_MGR OTHER Import Logic is overwriting the constraints in attached design.
7 o0 F0 I/ m' V A1544675 ALLEGRO_EDITOR OTHER Export libraries corrupts symbols if paths do not include the current directory (.)
4 J( O/ E* S# C `2 G1549097 CONSTRAINT_MGR XNET_DIFFPAIR Need to warn users creating differential pair(s) in the Physical Tab with nets that have voltage properties set4 P5 O6 E; I) U& T0 G# ~: q& ?
1551934 ALLEGRO_EDITOR SKILL axlBackDrill command is not analyzing new layer set when application mode is set to 'None'& `5 x/ W( J0 n6 j3 J
1554919 ADW LRM LRM does not find PTF data for cell 'res' in the reference library
2 a# V' Z9 i; Z4 o) u4 s' m3 X1555009 CONCEPT_HDL INTERFACE_DESIGN Not possible to rename NG3 b" n. `4 t; y; u9 H. V& \6 G
1557542 ALLEGRO_EDITOR OTHER DXF export creates strange result for donut-shaped polygon
# F$ D5 Q/ z9 P% f1 p4 d1559136 ALLEGRO_EDITOR EDIT_ETCH Cannot connect floating clines to vias with nets, N1 p l B4 v+ J7 N$ ]
1560301 CONCEPT_HDL CORE DE-HDL hangs when Edit menu commands are called on Linux if xclip is open; w5 s a, u Z$ x4 c
1560804 ALLEGRO_EDITOR OTHER Film records order gets reversed when using File - Import - Parameters after File - Export - Parameters
0 S9 z* @* }$ I C4 c1564036 CONCEPT_HDL CORE User-defined custom variables are not getting populated in the TOC" R$ ^3 ~3 F" a+ Q+ S2 f1 h
1564545 CONCEPT_HDL OTHER Signal model property deleted from an instance is not deleted from the instance pins
& L' D6 t: C w" n F' |: K1564552 CONCEPT_HDL CORE Find Net should zoom to the nets on schematic canvas6 T# I0 b9 r$ o$ N2 [8 c
1566119 CONCEPT_HDL CORE Right-clicking the schematic to add a component does not show all the schematic symbol versions- O2 L$ Y1 ^: L4 ]6 Z7 J. L' z- D
1566848 ALLEGRO_EDITOR ARTWORK Board Outline artwork is incomplete
5 m, {/ Q/ s" q* N1 b) @0 O1567290 ALLEGRO_EDITOR MANUFACT Import Artwork fails to import a shape.8 m/ [, W4 h, _* p2 {' G J
1567587 ALLEGRO_EDITOR MANUFACT Extended tool name in header of drill file is not correct' m6 e0 W+ n& A$ a r' F+ o$ l: J% {
1569056 CONCEPT_HDL CORE Opening New Cascaded Window Causes Graphics Artifacts on Old Window
2 i/ J t9 [3 Y4 w7 s8 j1569087 ALLEGRO_EDITOR DRC_CONSTR Running DRC Update gives the message 'Figure outside of drawing extents. Cannot continue.'/ Q$ [4 B- \& O0 @
1569147 CONCEPT_HDL CORE Signal Name AutoComplete Drop Down List Not Correctly Displayed
& ~3 V) g, X4 D- ?: J1 ]8 c: I1569924 CONCEPT_HDL CHECKPLUS ERROR (body_to_physical_check) - Pin name(s) not found in package : PEX_REFCLK0_N* PEX_REFCLK1_N*.... K3 d$ m# b& q% V4 ^- E+ e/ [
1570419 CONSTRAINT_MGR CONCEPT_HDL How do I add a customized worksheet custom property weblink in Constraint Manager0 L% z* M+ ~9 z: U
1570624 APD ARTWORK Artwork file has missing voids on a layer and is causing a short
, j" p, c7 j2 V q( M3 I7 j, J1570678 F2B DESIGNVARI Variant Editor error when adding an RSTATE property
! [* e3 W' X2 |1 ~: H L1571113 CONSTRAINT_MGR DATABASE Reports generated from cmDiffUtility show the differences in mm units only# D0 i3 `9 r' W& ~5 v$ W
1572593 ALLEGRO_EDITOR ARTWORK ARTWORK: 'Draw holes only' option does not match display0 k/ X2 g) M0 G' P
1573205 CONCEPT_HDL CORE dsreportgen is unable to resolve the physical net names (PHYSNET)+ F. N6 P" @* Q" I; g0 f! J7 D3 l
1573970 CONCEPT_HDL ARCHIVER archcore fails to archive the <project CPM>.arch file7 s4 ]0 _) _! u
1574381 CONCEPT_HDL OTHER Packager crashes with some advanced settings4 G6 W% {% o: {9 X T, t
1576100 ALLEGRO_EDITOR SYMBOL Update symbol crashes, creates '.sav' file, but shows update was successful in 'refresh.log'
% h- p. K! S2 p1 I, r/ W4 n1580103 ALLEGRO_EDITOR DATABASE dbstat of 16.6 does not recognize 17.X files) j% W7 o! n& l0 n" K$ m
# e4 c+ l2 v3 EDATE: 04-22-2016 HOTFIX VERSION: 069
, B, Y3 z. M5 Q===================================================================================================================================
4 F* |- }0 L0 Q. K% V* ^/ }CCRID PRODUCT PRODUCTLEVEL2 TITLE
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$ n& o$ m& [8 t% K; I1272355 F2B DESIGNVARI Property changes on replaced component shows incorrect result in BOM output
% @0 T L W' z3 g1483136 ADW COMPONENT_BROWSE About searching the parenthesis or comma in Component Browser of ADW Mode
, J. _2 h+ [7 j" ~. ?1488909 ALLEGRO_EDITOR DRC_CONSTR Test Via causes net scheduling verification to fail1 X$ w8 |0 T3 W; n. S
1498389 SIP_LAYOUT DIE_GENERATOR Provide the ability in the 'die in' command to specify flip chip as a DIE symbol
& X9 y: P* p) F2 D2 \1506672 ALLEGRO_EDITOR INTERACTIV Replicate Place - Shapes are missing/ _) V# c! Z- d9 w
1523532 F2B PACKAGERXL Adding subdesign names in the "Use subdesign” or “Force subdesign" sections hangs for more than a minute* F1 v; U- `/ E, @
1525783 CONCEPT_HDL CORE \BASE scope does not work for SYNONYMed global signals" |3 Z# U" _8 X' h9 h1 l9 c
1529846 ALLEGRO_EDITOR SHAPE Some shapes are not generated in the artwork5 E+ Q0 M$ s* Q+ D
1537499 CONCEPT_HDL CORE Adding the same version (already placed) with the same split block name should not be allowed3 ^# Q D. B# q. T: i
1542334 CONCEPT_HDL CREFER creferhdl leaving lock files in sch_1 folder
6 A# T8 h2 G" q1543410 ADW LRM LRM shows confusing pat status. It reports that update is needed but clicking update doesn't work
l# W' R n& T# F. B# o1546141 ALLEGRO_EDITOR SHAPE Shapes missing from Artwork1 L0 l# O6 @! y5 y8 l
1546877 CONCEPT_HDL CORE Align Left on Wires Fails With Incorrect Error Message
/ ^% z* i: b6 ]& O1548953 CONCEPT_HDL CORE Genview generates a symbol with strange graphics - lines going to a single point
* y$ _) D1 O% W2 Q1548978 ALLEGRO_EDITOR MANUFACT Shape not voiding clines/ O0 y) x& u& ]/ j# S
1550941 PCB_LIBRARIAN PTF_EDITOR PDV Part Table Editor new column sorting causing problems( D# m% M: [& t7 y _
1553950 ALLEGRO_EDITOR SKILL Executing axlUIControl('pixel2UserUnits) crashes Allegro- T# [4 i4 B$ K/ p& U0 K5 }0 t, p9 W/ K
1554333 CONCEPT_HDL CORE Changed connectivity error when aligning ports attached to netgroups
4 y5 |8 t& E! N2 v1555092 SIP_LAYOUT DEGASSING Degass offset is not working with hexagons
% n& S+ L+ ]* Z( A1556261 ALLEGRO_EDITOR DATABASE Running DBDoctor on board file gives an error"Illegal database pointer encountered, Exiting DBDOCTOR." and crashes w0 W& K' z1 T2 c7 z; Z
1557716 APD OTHER Stream out fails with request to terminate detected - Program aborted
& {8 g$ g, b- V; H1559951 SIP_LAYOUT SYMB_EDIT_APPMOD Wrong bump locations after Symbol Editor -> Refresh co-design die
* i7 p+ g- D; @8 y( f3 n! ?1560197 CONCEPT_HDL CORE bomhdl adds extra charcters to subdesign_suffix when generating hierarchical BOM/ j3 F# J0 i# U# a
1562537 ALLEGRO_EDITOR MENTOR Mentor BS to Allegro 16.6 results in Fatal Error: R" F. R4 A; ^. f' }, x
1564203 ALLEGRO_EDITOR ARTWORK ARTWORK : Can't generate negative film.
! w g# ?; D$ y4 ~& ?0 b+ H- R8 u
9 @. g; [$ F+ F; z8 C' B; ^DATE: 03-23-2016 HOTFIX VERSION: 068) L+ ~- r: [4 P' V
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CCRID PRODUCT PRODUCTLEVEL2 TITLE, S% z1 l" Q& {' A# c# L" L6 ~
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1522411 FLOWS PROJMGR License selection should persist on invoking Layout from Project Manager
5 [) Y7 p7 w3 \1544614 ALLEGRO_EDITOR SKILL Associative dimension data reaches the 'psm' file despite deleting the layer on which it was set in the 'dra' file
( Y9 D3 x+ T: U) a1545909 ALLEGRO_EDITOR UI_FORMS Show 'microvia' checkbox in 'Blind/Buried Vias' form only with the 'Allegro_PCB_Mini' license W' Q7 B# }/ y! @# N" R- @
1546842 ALLEGRO_EDITOR OTHER Unsupported characters: Not being reported by 'netrev' and causing nets to short5 T, w8 h% ?8 S# O9 B; U$ A9 V
1547224 CONCEPT_HDL CORE Lock the 'PATH' property once it is assigned by system) F3 G9 W2 S3 F$ L% f9 J3 {. ^2 H3 Y
1547584 SIP_LAYOUT OTHER SiP - Design Variant - delete embedded layer if not selected.
2 y. C1 {& N; K) k- I8 n" L p1548116 CONCEPT_HDL CORE Some versions of Technology Independent Library do not appear when adding a symbol
1 O3 H1 N$ j' s% x& K. p: @1548151 ALLEGRO_EDITOR INTERFACES Exporting a step file gives a component rotation mismatch in the *.stp file
6 e' y2 T; h7 q) {% ^( f5 w4 P; W1548421 F2B BOM Parts with same 'BOM_IGNORE' set do not behave the same way in the BOM report
8 h J% w" n7 U9 y; C1549105 APD OTHER 'Stream out' fails with message: 'Request to terminate detected. Program aborted'
( _, M- d0 |: L1549662 ALLEGRO_EDITOR OTHER Import parameters fails if your parampath does not have .' J; j! _" p& n% |
1549836 CONCEPT_HDL CORE Tools -> Customize -> Keys -> Reset does not actually reset keyboard shortcuts
: J5 x' }9 O& }0 A1550052 ALLEGRO_EDITOR PLACEMENT PCB Editor crashes when copying symbols
: v! L _5 o2 {0 L. D/ e( l. Q6 w1 a9 \9 c6 h( ]
DATE: 03-11-2016 HOTFIX VERSION: 067; L* e7 Y1 q: J2 h; U
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CCRID PRODUCT PRODUCTLEVEL2 TITLE
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1482953 ALLEGRO_EDITOR DATABASE Part change disassociates parts from Group
f( J; @$ F# q, a/ v+ Z3 T, U1484075 ALLEGRO_EDITOR PADS_IN 'pads_in' imports ASSEMBLY_TOP and PLACE_BOUND_TOP outlines that are defined as shapes as lines
! g3 V5 x! z# \# I. @* m' c1 @1519155 ALLEGRO_EDITOR OTHER IPC-2581-B Negative Plane Error
% E, F- D- P& w9 g1528075 CONCEPT_HDL OTHER Auto Generate: DML model assignment fails with error 'There is PHYS_DES_PREFIX property in PTF file.'
! i6 q4 t9 S- r1528398 ALLEGRO_EDITOR SCHEM_FTB Problem with pin number format used in NC property! a; ?6 x. }7 M( G/ D5 y: ]+ t
1529178 SIG_EXPLORER OTHER Values not transferred correctly for PinPairs when created ECSET from a net
9 S! M& ] A" O/ o3 L3 @5 p1529720 CONCEPT_HDL COPY_PROJECT Running ADW copy project does not update the 'master.tag' file
& j' u# \- }1 T2 a5 m( H0 e, }1530707 CONCEPT_HDL CORE Request to recover a 16.6 design after DE-HDL crashes% ~+ R& \% t( @/ E
1532124 CONSTRAINT_MGR SCM 'File - Export - Technology file' in Constraint Manager crashes SCM if .tcf file is missing6 I. h6 a* G! J; i/ |# f, W, m
1532788 CONSTRAINT_MGR OTHER Pin pair is hidden when Highlight Filter is ON in Constraint Manager
0 r+ ]. O5 V6 z) B9 i# G1536912 CONCEPT_HDL CORE Customizing keys in DE-HDL - Disallow mapping a command to alphanumeric characters
" I, `. a" R' g y" _1537055 CONCEPT_HDL CHECKPLUS Rules Checker - POWER_PINS value not obtained when schematic instance has the POWER_PINS and POWER_GROUP properties( ^ V1 u6 q7 ?3 ~8 |6 ?3 e; l
1537278 SIG_EXPLORER SIMULATION SigXplorer (Allegro Sigrity SI) crashes when simulation is viewed in SystemSI Waveform Viewer ]5 h$ M% t# I" j# A# R
1537339 CONCEPT_HDL INTERFACE_DESIGN No warning is flagged when moving a Net Group over a net1 P" F$ h" A- g! G& C& ~
1537521 FLOWS PROJMGR Do not allow project creation if there are spaces in directory or file names on the Linux platform6 S1 b. ~9 W. n6 O
1539227 CONCEPT_HDL CORE Renaming a page from the hierarchy browser crashes the schematic editor.
; O ~3 K, M7 m0 u$ X1541532 SCM SCHGEN Generate Schematics crashes with 'Out of Memory' error
, @! Y5 O& o/ M. [6 K. a( w1541589 ALLEGRO_EDITOR INTERFACES STEP model incorrectly shown in 3D viewer. Shows pins as angled./ P. @: ^& n' h9 [. ~! L# Y
1541680 CONCEPT_HDL DOC A dot (.) or period in design name created 2 separate design folders in worklib
3 [% I) }$ W5 x1541687 ALLEGRO_EDITOR PADS_IN PADS closed polygons are imported as lines5 |! g$ e3 k/ K8 b
1542722 ALLEGRO_EDITOR INTERFACES IDX export: RefDes and PART_NUMBER missing for mechanical symbols; a. B. e+ r" M! U3 `3 G( {
1542817 ALLEGRO_EDITOR DATABASE Import Netlist not getting completed on specific board2 A$ m6 |2 T3 D5 N; T$ w1 Y
1544060 SCM SCHGEN Generate Schematics causes Allegro System Architect to crash3 H1 q; D" d: b5 g; G3 e
1544633 APD STREAM_IF The 'stream out' command causes Allegro Package Designer to crash
, A& K& G2 w! J/ @5 V1544698 ALLEGRO_EDITOR PLACEMENT 'place replicate' does not add clines and vias to fanouts if fanouts are marked
- Q0 l6 Y/ ~8 D# I$ O/ N# L* e% L! J1544859 APD PARTITION Timing vision menu is missing in APD/SIP partitions./ O) t4 j \0 n! Z, a& I3 w3 |
1545136 ALLEGRO_EDITOR PLACEMENT All fanouts are marked as part of one symbol instead of the symbols they attached with
* w+ S$ O' k9 F6 H1 r" K1545370 APD OTHER Pads in .mdd file getting placed on different layers as compared to the design3 A) E% S# g$ D6 q: w/ A5 l, F
" A1 @' V- O3 Y6 f( |+ b; Z
DATE: 02-26-2016 HOTFIX VERSION: 066
- ?% D7 F' g$ o" Z5 @: v===================================================================================================================================
P# F3 {# v k$ Y# Z) Q# VCCRID PRODUCT PRODUCTLEVEL2 TITLE
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! u8 |: R# a5 b* G- @8 B1523426 ALLEGRO_EDITOR DRC_CONSTR Dynamic shape not adjusted based on keepout; DRC generated5 y. T# K9 J# C$ u
1526729 SPIF OTHER Exporting a dsn file causes PCB Editor to crash - in the interactive and batch modes
; P6 k7 ]- I3 c" I1529209 CONCEPT_HDL CORE When adding a component symbol version, the More option does not show all the versions
7 w( L7 E2 H2 e/ ]1 o1530888 ALLEGRO_EDITOR INTERFACES IPC2581 does not generate production files and fails with a segmentation fault message& l+ r @: N% s. _
1532865 CONCEPT_HDL CHECKPLUS Provide the ability for Rules Checker to report a GND symbol from the standard, and not our local library, in .mkr: Y0 B7 S0 I" `2 o5 `- @; c, F
1536273 CONSTRAINT_MGR CONCEPT_HDL Model-defined differential pair is removed, and Constraint Manager Design Differences does not report an issue
. N& {0 |( f" p [/ c3 L1538343 APD OTHER Inconsistent behavior when running Reports > Design Summary Report in Allegro Package Designer3 f% \ z3 H/ ?9 V( I+ F# p U
1539077 ALLEGRO_EDITOR SYMBOL PCB Editor crashes when choosing Layout > Renumber Pins- ^1 o7 j" S/ @1 j" n' `
1539997 ALLEGRO_EDITOR SKILL PCB Editor crashes when the axlStringRemoveSpaces() command is run* l3 X$ w; X, ~* o
1541445 APD DIE_EDITOR There are two Recent Designs submenus in the APD Symbol Editor; one should be removed
7 B5 k" u( w! R/ _
' ^- s- s( F& p$ R, _+ [DATE: 02-12-2016 HOTFIX VERSION: 065
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7 ]1 K N* t( V5 b1511947 ADW DSN_MIGRATION Command line arguments of the 'designmigration' command are not working
2 I3 K* c/ _5 a1517388 ALLEGRO_EDITOR SHAPE DRC error reported as PCB Editor fails to read the void for a via
, y9 {7 J9 [+ E# ~/ } P1521661 ALLEGRO_EDITOR PLACEMENT 'place replicate create': Automatically select etch objects connected to symbols, but not to objects outside the circuit& o8 |9 M+ V2 C4 g* T
1522831 APD OTHER axlSpreadsheetSetColumnProp with 'AUTO_WIDTH' propName does not autofit the contents.
) {3 Z9 Z |: F# d5 c6 s1524773 SIG_INTEGRITY SIMULATION Running PCB SI Probe and SigXplorer simulations show different number and shapes of waveforms
+ k5 X( d0 b7 D4 b1524875 F2B PACKAGERXL Packaging using csnetlister fails, while manual packaging of individual blocks works fine
7 T( v( q/ m* Q- K: j4 N4 @7 [1527785 SIP_LAYOUT WIREBOND SiP Layout stops responding when adding a wire to an existing finger8 o) [5 k2 s+ G E0 l
1528479 ADW LRM LRM crashes when opened on a lower-level block in a hierarchical design
7 o- @2 B, U: x2 o% U0 S- m1531425 CONCEPT_HDL CORE DE-HDL crashing while trying to add a NetGroup
0 X' c% z+ G. d0 k8 G1 g1532722 ALLEGRO_EDITOR NC Backdrill NCDrill files not getting created with PA3100 license.% [% Y' N& v' s
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DATE: 01-29-2016 HOTFIX VERSION: 064
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CCRID PRODUCT PRODUCTLEVEL2 TITLE
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1510387 FSP EXTERNAL_PORTS Break in extending a net as a deep connection when it is targeted to multiple FPGAs connected in a daisy chain" ~1 Y+ d, B$ Q& e) h" I9 ~
1514132 ALLEGRO_EDITOR INTERFACES Element position changes after importing DXF- F2 F8 H! F( t7 ]- q
1514285 ALLEGRO_EDITOR TECHFILE Importing .tcf file from Constraint Manager does not import user-defined properties.
# c9 v$ x$ T1 T9 u1515580 ALLEGRO_EDITOR EDIT_ETCH Sliding routed differential pair signals results in odd angles if the 'Dynamic Fillets' option is selected/ k1 L2 x" k$ S0 o; w2 _
1519040 ALLEGRO_EDITOR DATABASE Match groups are lost when a board created in SCM is saved in Allegro PCB Designer.
2 A* \- a( T- {( k1519910 CONCEPT_HDL INTERFACE_DESIGN Hotfix 62: Information on manually-remapped port groups is not saved, but reset to default5 f8 G! l# A% |. W1 ?! V" O" \& o9 @
1519943 ALLEGRO_EDITOR DATABASE When user units are changed from 4 to 2, the design seems to disappear from the canvas
* `& R+ h% y2 n; P& J0 v1519946 CONCEPT_HDL CORE Renaming a net leads to loss of constraints associated with the net
5 y, s4 f/ f. F% x( d1 O1519987 ALLEGRO_EDITOR SCHEM_FTB In Hotfix 61, constraints are lost on importing a netlist/ E4 Z" D. o: m7 n' c5 V/ m: f
1520727 CONCEPT_HDL CORE In Project Manager, the 'Design Sync - Export Physical' command does not automatically update the schematic$ D! P- p: F% w/ }2 e% t) p
1521174 SIP_LAYOUT DIE_STACK_EDITOR Padstack shapes not converted correctly to die-stack layer using Die-stack Editor
& ]. A. q% d. b1522227 SIP_LAYOUT IC_IO_EDITING SiP Layout stops responding when trying to add a co-design die (.xda file)
6 v2 ~# v- D* n6 K9 X- g7 [# X6 Y1522900 ORBITIO ALLEGRO_SIP_IF Padstack shape distortion after translation to OrbitIO from SiP design
0 f& _/ H/ P+ M2 N5 e( e3 a1523237 ALLEGRO_EDITOR SKILL SKILL function axlDBGetExtents() causing PCB Editor to crash
. K! u( _$ ^; H" d- A# s1524641 ALLEGRO_EDITOR DATABASE PCB Editor stops responding when updating outdated dynamic shapes9 g0 L2 S1 D& |/ n, Z+ n
1525432 CONSTRAINT_MGR OTHER User-defined property not being transferred from DE-HDL to PCB Editor
- m; r" ~1 X+ n4 J1 F- {6 ~* `' {1525948 F2B PACKAGERXL Reference designators assigned by the Packager tool are not correct
' D2 T; P% E# ]6 m4 I' _$ Z. c1527321 ALLEGRO_EDITOR SCHEM_FTB Unable to create netlist with the 'Open Board in OrCAD PCB Editor' option in Hotfix 63. H; } e; m( v6 M
1528254 CONSTRAINT_MGR CONCEPT_HDL Import Logic with the 'Overwrite current constraints' option is deleting some attributes( K. A4 e1 Q! p/ H0 @8 Y# C- k$ q
, d- E E$ w- k5 H5 p7 w" [DATE: 01-15-2016 HOTFIX VERSION: 063# g/ K' ]8 t0 n8 L
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1472414 ALLEGRO_EDITOR SCHEM_FTB netrev changes pin-shape spacing rule in constraint region
( x( e1 v. ^# E( f- j% ^, h( O1494194 CONCEPT_HDL CORE Random display of the 'PHYS_NET_NAME' property in hierarchical designs& E' i K0 [8 B/ ~
1500190 ALLEGRO_EDITOR EDIT_ETCH Snake Router Creates Line-to-Line DRCs z( u; w0 t% L' T2 {: v$ |" N/ W
1501093 SIP_LAYOUT OTHER Package design variant shows wirebonds connected to a die which is not part of the variant
+ J$ _ X% F/ |' L, W& W; K1509184 ALLEGRO_EDITOR DATABASE BB vias in mirror have terminal pads suppressed by artwork
, r9 R0 z1 A* f! Z7 K, c- {1511397 SIP_LAYOUT TECHFILE Tech file exported from release 16.5 cannot be reused in SiP Layout in 16.5 or 16.6
* b1 p5 I3 k# a# p, }0 U/ U1511744 ALLEGRO_EDITOR OTHER Allegro PCB Editor removes property from component instance
/ f3 y+ K1 M: y2 a: h1511761 SIG_INTEGRITY OTHER Allegro PCB Editor crashes on running the cns_show command.# `: D+ \# e- G$ L
1511787 ALLEGRO_EDITOR INTERFACES IPC-2581 not exporting overlapping shapes correctly. V7 d0 W( I# p2 {- D5 }( N
1512071 ALLEGRO_EDITOR OTHER The color of 'SHAPE PROBLEMS' subclass is reflected in the color of 'NCLEGEND-1-4' subclass when executing PDF out' i' M# w. Q1 P4 h1 m& `
1513085 CONCEPT_HDL CORE NC pins combine with NC_1 and routed as one net in Allegro PCB Editor1 y( Y& F- e: ?2 e Y
1514469 CONCEPT_HDL CORE Unable to get rid of an underscore from the PHYS_NET_NAME property& h' a/ z3 h$ B7 m* |$ {" Q
1515318 PCB_LIBRARIAN IMPORT_EXPORT Import Pin Table: 'CTRL + C' and 'CTRL + V' not working correctly
+ H: R0 U' s9 e |. J1516093 ALLEGRO_EDITOR PADS_IN Pads library translator does not translate slot orientation
( @) X. |1 x9 ?$ P# q$ I1517351 CONCEPT_HDL CORE Genview does not update an existing split symbol8 j5 ?; ]9 b" W7 \/ i
1518032 CONCEPT_HDL SECTION How to get rid of error 'SPCOCN-2009 - Symbol has the SEC property but the required SEC_TYPE property is missing.'3 @+ C; [8 ]* o. x: n5 t* I9 D& L
1518724 PCB_LIBRARIAN PTF_EDITOR PTF Editor is not saving changes/ x; y. i' O5 O# v% o8 o& ]. ^
1519518 CONCEPT_HDL OTHER Genview does not generate split symbols
1 ]8 ]& w+ z* K0 b1519623 CONCEPT_HDL CORE Differential pair added to a NetClass does not display 'NET_PHYSICAL_TYPE' on the canvas( f4 N }2 {1 x8 }4 D! `
1520207 CONCEPT_HDL CORE Genview crashes after renaming ports
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* P# Q* [; h. ^DATE: 12-11-2015 HOTFIX VERSION: 062
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* T6 ]6 ~0 b1 p+ X, D, yCCRID PRODUCT PRODUCTLEVEL2 TITLE# H" j' I; k3 d$ X8 g, C
===================================================================================================================================: s5 [5 K6 A6 s! e9 ^. z
1012606 ALLEGRO_EDITOR REPORTS Natural sort option for Report output7 S( h" h$ v* F, Y" y
1408218 ALLEGRO_EDITOR MANUFACT Specifying the Offset value results in unexpected value of the NC Route coordinates in the .rou file
& O4 U# y1 E3 g+ I1440509 ALLEGRO_EDITOR PLOTTING Ratsnest do not follow the refdes position when plotting the BOTTOM layer with the 'Mirror' option v: n, i5 D- L- T: G
1444144 ALLEGRO_EDITOR DRC_CONSTR The 'add taper' command generates line to line spacing DRC
E2 \: `! }1 j1471275 SCM UI Allegro System Architect (SCM) - Allow sorting on the pin number field in the Matrix view
- o, H0 i+ I w0 t1474764 ALLEGRO_EDITOR PLACEMENT In SPB166 Hotfix 56, the place replicate create command does not produce desired results if the fanout is marked
. G# M/ m& l1 h0 c$ I1474894 ALLEGRO_EDITOR PLACEMENT Place replicate fails to include vias when the module is applied to other circuits. m7 ?6 V) @, `: v
1485931 ALLEGRO_EDITOR INTERFACES Errors generated when importing IDF in an existing board file
) P, V+ H) a: q9 ]' o& R J* E1487603 SIP_LAYOUT WIREBOND SiP Layout XL - Add multibondwire option to non-standard wirebonding1 p0 U. G, r9 g
1490311 SCM OTHER Block Packaging reports duplication when it should not, X% U8 S4 a) N0 x: U
1491272 ALLEGRO_EDITOR EXTRACT Incorrect information exported to DXF if the value of SeparateSlotHoleLegend is set to 'yes', y; d9 ^- e7 s3 h+ J: G% b2 S
1491521 F2B PACKAGERXL Packager reports error (SPCODD-269) when there are duplicate subdesign suffixes - need a clearer message$ a) _- [0 K. x4 `
1492013 CONCEPT_HDL CORE Stale PNN properties not cleared from schematic on packaging design (backannotation)9 i. _5 O4 b' J, `
1492703 CONCEPT_HDL OTHER 'Global Property Display' not working for symbol edit8 S/ h( f: w; |) k
1495296 SIG_EXPLORER OTHER The T-point sequence in SigXplorer is different from the layout
* J% D l) _9 W$ `1495789 ALLEGRO_MFG_OP CORE DFM checker checks for laser vias ( LVDC, LVDP, LVDT )0 F: i8 F6 f% B& Z( c6 @& [) `- f
1496286 ALLEGRO_EDITOR PLOTTING Export PDF is not exporting hidden, phantom, and dotted line types( N( F5 o" I* l' n1 R0 \
1499051 ALLEGRO_EDITOR PLOTTING PDF Publisher reports error for a donut shape model in the layout - 'Shape symbol cannot have a void in a shape'- S6 S* l+ r9 m& o* a, G+ C
1499380 SIP_LAYOUT DEGASSING Oblong shape degassing voids are not created correctly
?7 w6 C8 p2 Z4 I/ R6 ^! P1499538 ALLEGRO_EDITOR PAD_EDITOR Pad_designer does not allow layer name change from Begin_layer to diepad1_top; dbdoctor does not fix this
7 Q& U2 @7 q) {9 {7 _1500422 ALLEGRO_EDITOR SKILL SKILL function, axlTriggerSet, results in PCB Editor crashing at launch
# n. C$ q9 l3 F% I2 M" |- p1500659 FLOWS PROJMGR Need the ability to ensure that the standard library is not added to the project libraries list by default
$ X1 k- E% a! E, I$ c& W6 L1500725 F2B PACKAGERXL Unable to clear pstprop.dat file conflicts
, L/ w, ? O& c* b( E1 r, o1501139 ALLEGRO_EDITOR PADS_IN Pads_in creates pastemask for Through Hole padstacks
: x# i2 y1 _$ w: R1501165 F2B DESIGNVARI TDO does not manage overlay files and variant_roz1040660_1.ba cannot be created unless variant_merged.dat is checked out6 h9 w. x* g4 y+ g& q( P( Y
1501774 ALLEGRO_EDITOR OTHER PDF Publisher: If text is attached to an object, the object is also printed in the PDF
3 l7 T: s: S/ y' m0 G7 b1501898 F2B DESIGNVARI Variant custom variables are visible in the schematic border but are not there in the Variant Details form* g3 H- k$ P+ e& h' [' P
1501974 F2B PACKAGERXL 'Feedback has found Illegal pin swap(s)' error although the pin was already swapped and fed back (B2F) to DE-HDL
6 Y4 }5 y$ M* i J! V, P1502782 ALLEGRO_EDITOR SCHEM_FTB Allegro System Architect (SCM) - Export Physical stops unexpectedly without any errors or warnings% s) B0 o; g M) R
1503551 APD STREAM_IF In SPB166 Hotfix 60, error reported if a self-intersecting polygon outline exists at a specific location
) y5 w8 J6 n R1 e) f$ D" E: J1504093 ASI_SI GUI View Topology and Waveform buttons overlap when Signal Analysis window is resized, C5 W a3 ?# o) g9 f5 @) B
1504767 CONSTRAINT_MGR SCHEM_FTB Constraint Manager generates errors if the 'sNoF2BFlow' property is added to the Constraint Manager Dictionary
' D; D1 J" ^& T. \1 s% z1505497 SIP_LAYOUT LOGIC Assign net fails to fully connect propagated items
! q7 J" F2 Y! g @( A1506110 ALLEGRO_EDITOR DRC_CONSTR No DRC shown when a text on etch layer is overlapped on mechanical pin
8 Y& ^* a; s: v5 c2 l6 j$ a9 @5 I1506654 CONCEPT_HDL INTERFACE_DESIGN Netgroups broken when moving
: p; y3 t2 Q$ {1 ?1506983 ALLEGRO_EDITOR SKILL axlBackDrill SKILL command crashes PCB Editor after backdrill analysis is run when App mode is set to None
8 Y' w8 h' e' b8 _
. m4 x, c) X/ E) E6 W+ rDATE: 11-20-2015 HOTFIX VERSION: 061
! l/ x4 o8 d- b( [4 e, |===================================================================================================================================- `8 f* g/ a8 `1 G4 E
CCRID PRODUCT PRODUCTLEVEL2 TITLE# Y2 d6 u( d5 N
===================================================================================================================================
8 k5 Y0 z- R% \+ O) A( o8 {5 Z1 E, t; o1306441 APD OTHER The Minimum Shape Area option in Layer Compare uses an unspecified value" u+ u0 D3 ] M j3 S
1342644 ADW COMPONENT_BROWSE Need directive or method for Component Browser to load a search criteria file upon init, B6 E# e4 b5 E# t7 l
1413248 CONCEPT_HDL CORE Import from another TDO project makes the block read-only
% [! C* B. e* v( e1417429 ALLEGRO_EDITOR INTERACTIV Pick box only accepts 1 set of values. You need to close the box and reopen it to draw a rectangle; b w- k8 |; h7 C7 Q: X* N; `
1417442 ALLEGRO_EDITOR INTERACTIV Spin via stack and only part of the stack spins; G- e! t/ i1 F4 k0 [2 h/ T; H3 M
1451977 CONCEPT_HDL PDF Origin of PDF mediabox not starting at (0,0) when PDF page_height and page_width are set
8 V6 _# p! j9 Y5 T/ m1453527 ALLEGRO_EDITOR EDIT_ETCH Contour route hugs the outer edge of the route keepin7 R! N* x i" s8 @% V
1464948 PCB_LIBRARIAN VERIFICATION The errors/warnings do not match between the various tools! i1 Y) i( E3 f. U
1467826 CONCEPT_HDL PDF PublishPDF from Console Window creates a long PDF filename+ h }0 k3 x: b) o- m! i& H
1478639 CAPTURE OTHER Capture Browse Nets window does not display all nets0 X! |; M& U- H
1479177 SIP_LAYOUT OTHER Pin pair constraints do not appear to be supported in Sip Layout XL
+ ~' M& Z2 H, Z7 }1479227 CONCEPT_HDL CHECKPLUS Custom DE-HDL Rules Checker rule flagging invalid voltage in hierarchy
3 f' w. h. j4 v2 D: R: f1479454 CONCEPT_HDL OTHER DE-HDL issue: locked DIFF_PAIR property is editable/ J E8 w: K! [7 \" F5 I
1480293 CAPTURE PROJECT_MANAGER Capture hangs when searching for all nets ^% b8 \; z) w3 H- v/ D6 O
1483894 CONCEPT_HDL CORE Import Design hangs when pull-down arrow is clicked twice0 c5 M# ~1 N" v, W, ]4 d
1484781 CONCEPT_HDL CORE Three different Hierarchical Viewer issues
5 r" D. L3 T, L: Y% o6 T( R1485059 PCB_LIBRARIAN CORE Part Developer pin attributes are randomly marked as read-only
4 Y2 K' h" h, w5 q1485960 CONCEPT_HDL CHECKPLUS Custom DE-HDL Rules Checker rule is crashing the project% u- Y/ j- F' A8 L3 Y' c _4 E8 M
1486086 ALLEGRO_EDITOR ARTWORK Cannot generate artwork.
2 l4 T$ t) g% ~1486834 CONSTRAINT_MGR OTHER Restore the Status column in cmDiffUtility
7 s1 k7 H2 ]1 w8 U* Q+ ~9 _/ F/ F1487085 CONCEPT_HDL CONSTRAINT_MGR Import Physical with the Constraints only option reports problems2 m, C" U- T* ?6 W7 M
1487197 ALLEGRO_EDITOR DRC_CONSTR Drill to Via DRCs are not being reported0 q7 r5 H' d1 A) y5 N% t+ b' ~
1487265 CONCEPT_HDL CORE Replace command in Windows mode shows incorrect behavior" B5 C4 T7 N( e
1487733 CONSTRAINT_MGR OTHER Running Export Physical - It takes over two hours to update the PCB Editor board
7 P$ h9 G( E a2 g% p G1 ~$ L1488758 CONCEPT_HDL CONSTRAINT_MGR CM_VALIDATION_ON_SAVE should be a hard stop on Constraint Manager6 L' i5 Q$ ?! y6 u/ ?5 O
1490299 SCM OTHER ASA does not update revision properly0 ~9 X* x- @* z8 F7 |9 M% v) n
1490744 ALLEGRO_EDITOR SKILL axlChangeLine2Cline changes line to cline and places it on the TOP layer: j+ i' C0 B1 a) C `
1490924 F2B PACKAGERXL Save Design/Export Physical is resetting Via constraints( u. L- L! v: g6 X: m2 T
1491351 ALLEGRO_EDITOR OTHER Create Detail for bond fingers on a custom layer not working" l& A/ i; d& e, j
1492595 ALLEGRO_EDITOR MANUFACT Dimension character substitution help is wrong2 l8 `: }" e( O" _
1492777 ORBITIO ALLEGRO_SIP_IF OrbitIO import of customer mcm results in crash
9 O; ]- ^1 @. o/ j' Y1492901 CONCEPT_HDL CORE Cannot instantiate a multi-sections symbol (> 10 versions) in Design Entry HDL
) W1 _3 G) y% K2 T3 s7 J1495621 ALLEGRO_EDITOR INTERFACES Oval pins are placed with wrong orientation in IPC2581
- v+ x3 z( }7 S1497597 ALLEGRO_EDITOR DATABASE Show Element on pin shows wrong drill size
8 B$ L; z& ?5 v# c: r/ s5 }- V1497956 CONCEPT_HDL CORE ADW Library Flow test schematic generation crashes DE-HDL while saving the design when using customer adw_conf_root0 k" u& E# s' h3 M. f& t
1498234 ALLEGRO_EDITOR ARTWORK PCB Editor fails to create artwork and no error is listed in the log file& y l8 D' |! @3 [- r9 M4 W( ~2 y, w% M
1499363 CONCEPT_HDL CORE Custom attributes under variant management stopped working in Hotfix60 |
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发表于 2016-6-29 12:21
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发表于 2016-8-17 13:05
