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DATE: 05-28-2016 HOTFIX VERSION: 071
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1452838 CONCEPT_HDL CORE Apparent discrepancy between Bus names and other nets
# Q8 W9 \6 h* p! C! F2 }) ?1469146 ADW LRM ERROR(SPCODD-5): Pin '1<1>' on the following primitive instance cannot be packaged in package9 Y$ d* X! D4 m, m% ]) r% ~2 l' B% s8 ~
1499515 ADW COMPONENT_BROWSE The Search Criteria property value is automatically being set in the ADW Component Browser
4 \" t; F% o1 q" V x1524947 SIG_INTEGRITY SIGNOISE SI Base, PCB SI: Custom Stimulus is not recognized correctly
4 N# l3 w% O' Z8 ]1532162 CONCEPT_HDL CORE The Rename Signal command does not update split symbols.. ^7 a8 ]- \5 B& ~ u; T" C! {
1543997 CONSTRAINT_MGR OTHER Import Logic is overwriting the constraints in attached design.
8 D5 ^; M0 [3 y1544675 ALLEGRO_EDITOR OTHER Export libraries corrupts symbols if paths do not include the current directory (.)
4 x: o. M' [5 H: k$ @0 |+ K4 ^1549097 CONSTRAINT_MGR XNET_DIFFPAIR Need to warn users creating differential pair(s) in the Physical Tab with nets that have voltage properties set
4 } W( r H1 O( u1551934 ALLEGRO_EDITOR SKILL axlBackDrill command is not analyzing new layer set when application mode is set to 'None'
9 S$ M @) B, q, K& r+ x1554919 ADW LRM LRM does not find PTF data for cell 'res' in the reference library0 r3 \9 p, N* l6 o
1555009 CONCEPT_HDL INTERFACE_DESIGN Not possible to rename NG1 h1 T$ a M8 Z* `4 k. h
1557542 ALLEGRO_EDITOR OTHER DXF export creates strange result for donut-shaped polygon
8 u2 i6 w9 M' K1 I% v1559136 ALLEGRO_EDITOR EDIT_ETCH Cannot connect floating clines to vias with nets) O% d- S, ], X7 Z
1560301 CONCEPT_HDL CORE DE-HDL hangs when Edit menu commands are called on Linux if xclip is open% t! b- T, ^# ^5 [9 R: R% r
1560804 ALLEGRO_EDITOR OTHER Film records order gets reversed when using File - Import - Parameters after File - Export - Parameters% l( l6 |5 L" R. G; H+ O
1564036 CONCEPT_HDL CORE User-defined custom variables are not getting populated in the TOC
$ w' u2 j8 R" Q* I7 _; A1564545 CONCEPT_HDL OTHER Signal model property deleted from an instance is not deleted from the instance pins" k$ {* U1 W3 {' c3 n; S
1564552 CONCEPT_HDL CORE Find Net should zoom to the nets on schematic canvas8 l& i+ \* Z1 A8 I: D/ l
1566119 CONCEPT_HDL CORE Right-clicking the schematic to add a component does not show all the schematic symbol versions1 Q* R8 L3 n' e: Z6 O& [: F! k" r/ i
1566848 ALLEGRO_EDITOR ARTWORK Board Outline artwork is incomplete/ D" ] [/ b' A* w) B
1567290 ALLEGRO_EDITOR MANUFACT Import Artwork fails to import a shape.
; l# m6 e% y# `/ I) c4 B1567587 ALLEGRO_EDITOR MANUFACT Extended tool name in header of drill file is not correct, N; ~3 ?2 D- K/ _7 e6 d
1569056 CONCEPT_HDL CORE Opening New Cascaded Window Causes Graphics Artifacts on Old Window
; H& [1 p# K+ n1 }. q1569087 ALLEGRO_EDITOR DRC_CONSTR Running DRC Update gives the message 'Figure outside of drawing extents. Cannot continue.'* y$ E! n5 l% X5 Y9 A
1569147 CONCEPT_HDL CORE Signal Name AutoComplete Drop Down List Not Correctly Displayed
5 B. X5 I- ^( q* h" _1569924 CONCEPT_HDL CHECKPLUS ERROR (body_to_physical_check) - Pin name(s) not found in package : PEX_REFCLK0_N* PEX_REFCLK1_N*...
% |# g |8 }+ d4 q1570419 CONSTRAINT_MGR CONCEPT_HDL How do I add a customized worksheet custom property weblink in Constraint Manager: Z4 Q9 e2 B2 ^2 e l
1570624 APD ARTWORK Artwork file has missing voids on a layer and is causing a short- w h5 R3 G! c% `2 o; |" E
1570678 F2B DESIGNVARI Variant Editor error when adding an RSTATE property/ ?+ b2 v; @+ X% n) ^! \. R5 v
1571113 CONSTRAINT_MGR DATABASE Reports generated from cmDiffUtility show the differences in mm units only
) k+ f& R" f( r. w4 `- i/ o8 _1572593 ALLEGRO_EDITOR ARTWORK ARTWORK: 'Draw holes only' option does not match display! t/ i; U5 O* W- [- X0 `
1573205 CONCEPT_HDL CORE dsreportgen is unable to resolve the physical net names (PHYSNET). F4 N/ v' r) s8 W* `
1573970 CONCEPT_HDL ARCHIVER archcore fails to archive the <project CPM>.arch file
# g, @7 P8 c. s% H2 @1574381 CONCEPT_HDL OTHER Packager crashes with some advanced settings
7 M5 X6 g8 D5 l7 c# I1576100 ALLEGRO_EDITOR SYMBOL Update symbol crashes, creates '.sav' file, but shows update was successful in 'refresh.log'
. |, ^+ t; G- k) P# A1580103 ALLEGRO_EDITOR DATABASE dbstat of 16.6 does not recognize 17.X files( I* ~3 f% W% X! o
! }. `# ^; M8 b1 I
DATE: 04-22-2016 HOTFIX VERSION: 069
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CCRID PRODUCT PRODUCTLEVEL2 TITLE
# @7 O% m, i t. n# N===================================================================================================================================
3 v! o0 q/ B0 p9 G1272355 F2B DESIGNVARI Property changes on replaced component shows incorrect result in BOM output
) b/ j5 w1 `$ M/ e! r1483136 ADW COMPONENT_BROWSE About searching the parenthesis or comma in Component Browser of ADW Mode, @ j" j! m5 y4 S5 ]3 G
1488909 ALLEGRO_EDITOR DRC_CONSTR Test Via causes net scheduling verification to fail
/ w. n4 A7 C2 q0 g- c1498389 SIP_LAYOUT DIE_GENERATOR Provide the ability in the 'die in' command to specify flip chip as a DIE symbol+ b6 C! X* i9 ?) E
1506672 ALLEGRO_EDITOR INTERACTIV Replicate Place - Shapes are missing
9 K& Y ] L" a$ a, Y# G: K9 T1523532 F2B PACKAGERXL Adding subdesign names in the "Use subdesign” or “Force subdesign" sections hangs for more than a minute3 l" H* D! p; }& w' A* J
1525783 CONCEPT_HDL CORE \BASE scope does not work for SYNONYMed global signals! m* n$ s. M* z; N+ F
1529846 ALLEGRO_EDITOR SHAPE Some shapes are not generated in the artwork
7 B R* B! g. j9 Z! G% `1537499 CONCEPT_HDL CORE Adding the same version (already placed) with the same split block name should not be allowed
4 x. B( J; q$ k6 @' \1542334 CONCEPT_HDL CREFER creferhdl leaving lock files in sch_1 folder
! ~7 I/ C$ G/ B' C1543410 ADW LRM LRM shows confusing pat status. It reports that update is needed but clicking update doesn't work+ }5 f9 W# K/ w* m$ {6 K# T5 q! f
1546141 ALLEGRO_EDITOR SHAPE Shapes missing from Artwork' E. Z9 l( O9 c8 b6 a- R0 l4 Y+ d
1546877 CONCEPT_HDL CORE Align Left on Wires Fails With Incorrect Error Message1 R T$ X/ Z# a* ^4 G0 A
1548953 CONCEPT_HDL CORE Genview generates a symbol with strange graphics - lines going to a single point
1 \( t! ?7 s$ Q N2 g! Z: e1548978 ALLEGRO_EDITOR MANUFACT Shape not voiding clines
/ d$ y9 U Z. ]1 v1550941 PCB_LIBRARIAN PTF_EDITOR PDV Part Table Editor new column sorting causing problems
_6 e* f' Q" e1553950 ALLEGRO_EDITOR SKILL Executing axlUIControl('pixel2UserUnits) crashes Allegro
( ]5 M H! X, @1554333 CONCEPT_HDL CORE Changed connectivity error when aligning ports attached to netgroups
% S4 u T. z0 y1 V' r1555092 SIP_LAYOUT DEGASSING Degass offset is not working with hexagons
) @: g I( Y8 u1556261 ALLEGRO_EDITOR DATABASE Running DBDoctor on board file gives an error"Illegal database pointer encountered, Exiting DBDOCTOR." and crashes# s# \' _% k3 J
1557716 APD OTHER Stream out fails with request to terminate detected - Program aborted. d; Y o. Y- Q. O+ _: Q7 G, V
1559951 SIP_LAYOUT SYMB_EDIT_APPMOD Wrong bump locations after Symbol Editor -> Refresh co-design die; Q2 w' {6 u) s/ T. i3 { x
1560197 CONCEPT_HDL CORE bomhdl adds extra charcters to subdesign_suffix when generating hierarchical BOM3 ^' j5 u) a; P' x2 r; n
1562537 ALLEGRO_EDITOR MENTOR Mentor BS to Allegro 16.6 results in Fatal Error' ^; S1 c7 O* [. ` d
1564203 ALLEGRO_EDITOR ARTWORK ARTWORK : Can't generate negative film.
~+ l+ W ]1 M! X. k: E
$ N! E! {, C# ~2 X; ]9 pDATE: 03-23-2016 HOTFIX VERSION: 068
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1522411 FLOWS PROJMGR License selection should persist on invoking Layout from Project Manager
% {% e9 z2 p8 s1544614 ALLEGRO_EDITOR SKILL Associative dimension data reaches the 'psm' file despite deleting the layer on which it was set in the 'dra' file
3 \* K3 I8 d0 W, Z/ d) i1545909 ALLEGRO_EDITOR UI_FORMS Show 'microvia' checkbox in 'Blind/Buried Vias' form only with the 'Allegro_PCB_Mini' license
% T4 t3 v C: M7 M( x* `* W8 r1546842 ALLEGRO_EDITOR OTHER Unsupported characters: Not being reported by 'netrev' and causing nets to short
4 @2 `/ s; D% `# O) A# E- v1547224 CONCEPT_HDL CORE Lock the 'PATH' property once it is assigned by system0 I: G6 m0 @% u. r! @
1547584 SIP_LAYOUT OTHER SiP - Design Variant - delete embedded layer if not selected.% ?2 W7 l' m U* n' A* J8 M
1548116 CONCEPT_HDL CORE Some versions of Technology Independent Library do not appear when adding a symbol" A$ U1 g G8 i! m
1548151 ALLEGRO_EDITOR INTERFACES Exporting a step file gives a component rotation mismatch in the *.stp file
' Y5 j4 |7 J! p* G# `: I1548421 F2B BOM Parts with same 'BOM_IGNORE' set do not behave the same way in the BOM report& s1 U; y( M1 [1 r7 A
1549105 APD OTHER 'Stream out' fails with message: 'Request to terminate detected. Program aborted'
8 G# {( _. `% W; x5 L! c# f, [6 i1549662 ALLEGRO_EDITOR OTHER Import parameters fails if your parampath does not have .
& c5 v) P; @6 Z) o& X l1549836 CONCEPT_HDL CORE Tools -> Customize -> Keys -> Reset does not actually reset keyboard shortcuts
. t: m! |! k" Z4 D E1550052 ALLEGRO_EDITOR PLACEMENT PCB Editor crashes when copying symbols- p! e2 b3 k$ n* T/ }
& U% A: Z7 y4 w* [
DATE: 03-11-2016 HOTFIX VERSION: 067
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# }+ k7 N: e7 E, g( I% l" J1482953 ALLEGRO_EDITOR DATABASE Part change disassociates parts from Group
* p g8 A t& C K# A, }* z! A2 l+ B5 F8 D1484075 ALLEGRO_EDITOR PADS_IN 'pads_in' imports ASSEMBLY_TOP and PLACE_BOUND_TOP outlines that are defined as shapes as lines% e, k3 X1 ~3 D
1519155 ALLEGRO_EDITOR OTHER IPC-2581-B Negative Plane Error
, @4 I7 I2 h& B1528075 CONCEPT_HDL OTHER Auto Generate: DML model assignment fails with error 'There is PHYS_DES_PREFIX property in PTF file.'
- a! }$ k7 n. j9 z0 k3 W1528398 ALLEGRO_EDITOR SCHEM_FTB Problem with pin number format used in NC property8 `( d9 l6 ]0 ?; E$ b6 A
1529178 SIG_EXPLORER OTHER Values not transferred correctly for PinPairs when created ECSET from a net
# H4 H3 |7 w' L0 G0 [- q ?( j: T1529720 CONCEPT_HDL COPY_PROJECT Running ADW copy project does not update the 'master.tag' file
3 b. u& U6 y& s# s1530707 CONCEPT_HDL CORE Request to recover a 16.6 design after DE-HDL crashes: u! d3 M n& ]. Y5 J% O
1532124 CONSTRAINT_MGR SCM 'File - Export - Technology file' in Constraint Manager crashes SCM if .tcf file is missing/ \( W: d' B6 N4 q4 P4 k+ Z
1532788 CONSTRAINT_MGR OTHER Pin pair is hidden when Highlight Filter is ON in Constraint Manager
' B& T$ ~6 _3 h/ y1536912 CONCEPT_HDL CORE Customizing keys in DE-HDL - Disallow mapping a command to alphanumeric characters
, g+ G; X. C* Z3 y1537055 CONCEPT_HDL CHECKPLUS Rules Checker - POWER_PINS value not obtained when schematic instance has the POWER_PINS and POWER_GROUP properties! U2 P: U; {1 }) g
1537278 SIG_EXPLORER SIMULATION SigXplorer (Allegro Sigrity SI) crashes when simulation is viewed in SystemSI Waveform Viewer2 y4 B( @! [- B9 J
1537339 CONCEPT_HDL INTERFACE_DESIGN No warning is flagged when moving a Net Group over a net
; ^9 n& J: k% u- O. C1537521 FLOWS PROJMGR Do not allow project creation if there are spaces in directory or file names on the Linux platform
' e. U2 U2 R# S1539227 CONCEPT_HDL CORE Renaming a page from the hierarchy browser crashes the schematic editor.
& x7 `' S$ E! r. b5 e; u/ e1541532 SCM SCHGEN Generate Schematics crashes with 'Out of Memory' error1 N5 _% c9 i% I5 Z
1541589 ALLEGRO_EDITOR INTERFACES STEP model incorrectly shown in 3D viewer. Shows pins as angled.
2 x+ D- G4 E$ u1541680 CONCEPT_HDL DOC A dot (.) or period in design name created 2 separate design folders in worklib7 O& R1 b9 r& V0 ^' t
1541687 ALLEGRO_EDITOR PADS_IN PADS closed polygons are imported as lines
8 F" ]/ w7 B4 V$ \6 K5 }1542722 ALLEGRO_EDITOR INTERFACES IDX export: RefDes and PART_NUMBER missing for mechanical symbols8 e! Y% Y" P: V. B3 {9 k8 R" U( F
1542817 ALLEGRO_EDITOR DATABASE Import Netlist not getting completed on specific board
% B# C2 H# |8 z1544060 SCM SCHGEN Generate Schematics causes Allegro System Architect to crash
% ~' r7 N! c# }% l7 l5 j& [0 v. ^+ q1544633 APD STREAM_IF The 'stream out' command causes Allegro Package Designer to crash
f0 ]- m6 I; f P% _/ t1544698 ALLEGRO_EDITOR PLACEMENT 'place replicate' does not add clines and vias to fanouts if fanouts are marked* I4 ]8 ~# e; f7 U, }5 k0 ]
1544859 APD PARTITION Timing vision menu is missing in APD/SIP partitions.
% U1 q, U. _5 z6 ^6 r0 f0 v3 \1545136 ALLEGRO_EDITOR PLACEMENT All fanouts are marked as part of one symbol instead of the symbols they attached with
3 B, h6 ] P. f& z3 S: i+ d. i1545370 APD OTHER Pads in .mdd file getting placed on different layers as compared to the design0 ~$ l9 I4 D+ e$ F
& _5 Y$ Q9 Y2 n( R, h$ [( T EDATE: 02-26-2016 HOTFIX VERSION: 066; ], |& [# B2 a# U! [3 Y
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CCRID PRODUCT PRODUCTLEVEL2 TITLE
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! M/ w3 ?$ G4 S( i4 f1523426 ALLEGRO_EDITOR DRC_CONSTR Dynamic shape not adjusted based on keepout; DRC generated
) o( }; d: U' K1526729 SPIF OTHER Exporting a dsn file causes PCB Editor to crash - in the interactive and batch modes
- u+ D9 L1 n# m, c5 \6 z( \1529209 CONCEPT_HDL CORE When adding a component symbol version, the More option does not show all the versions
- W0 k% H5 C. ?& O: T9 R" V ?$ Z1530888 ALLEGRO_EDITOR INTERFACES IPC2581 does not generate production files and fails with a segmentation fault message
$ S/ ^- [2 r/ k e0 H0 |; ]5 Z4 ~1532865 CONCEPT_HDL CHECKPLUS Provide the ability for Rules Checker to report a GND symbol from the standard, and not our local library, in .mkr
, ~) }' [9 E5 B* @5 B& O1536273 CONSTRAINT_MGR CONCEPT_HDL Model-defined differential pair is removed, and Constraint Manager Design Differences does not report an issue
* G' T7 d" ~ v' Y0 p$ T9 ?1538343 APD OTHER Inconsistent behavior when running Reports > Design Summary Report in Allegro Package Designer
+ p9 m$ H9 Y. J; X1539077 ALLEGRO_EDITOR SYMBOL PCB Editor crashes when choosing Layout > Renumber Pins7 ~, j" l1 h6 H; x
1539997 ALLEGRO_EDITOR SKILL PCB Editor crashes when the axlStringRemoveSpaces() command is run) y; b' ~2 D% G% j: g
1541445 APD DIE_EDITOR There are two Recent Designs submenus in the APD Symbol Editor; one should be removed2 X$ I$ D) J7 w4 b: a7 U
6 q+ T: a; b3 C5 r0 q
DATE: 02-12-2016 HOTFIX VERSION: 065* L S& |8 P6 t9 y4 `+ W: e2 U
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: C" j `- f' E4 h7 ?1 N% n( D* v1 LCCRID PRODUCT PRODUCTLEVEL2 TITLE
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, H" Q) C& @; N/ g* L6 D5 ^% l0 ~1511947 ADW DSN_MIGRATION Command line arguments of the 'designmigration' command are not working
/ Y- L# q' p3 Z. r( f# R* N3 J2 }1517388 ALLEGRO_EDITOR SHAPE DRC error reported as PCB Editor fails to read the void for a via
! F' ?3 T* l8 V) y! N: N1521661 ALLEGRO_EDITOR PLACEMENT 'place replicate create': Automatically select etch objects connected to symbols, but not to objects outside the circuit
' p n' d* _+ s+ J) c* K. _4 }1522831 APD OTHER axlSpreadsheetSetColumnProp with 'AUTO_WIDTH' propName does not autofit the contents.. u" \8 f3 m, A- ]. c; Y0 D
1524773 SIG_INTEGRITY SIMULATION Running PCB SI Probe and SigXplorer simulations show different number and shapes of waveforms, Y1 H3 M" R: f" ^, F2 I5 r& Z
1524875 F2B PACKAGERXL Packaging using csnetlister fails, while manual packaging of individual blocks works fine o v/ \* \% \6 ~/ {
1527785 SIP_LAYOUT WIREBOND SiP Layout stops responding when adding a wire to an existing finger
: l, g* a: O5 }! B6 K1528479 ADW LRM LRM crashes when opened on a lower-level block in a hierarchical design: y, {$ Z& |1 ~0 [# L: j
1531425 CONCEPT_HDL CORE DE-HDL crashing while trying to add a NetGroup
' i" d. N+ }! v1 _ j8 v& p+ T1532722 ALLEGRO_EDITOR NC Backdrill NCDrill files not getting created with PA3100 license.2 \7 Q& d+ f& A7 V4 A) [
! G# k* L) N% D& A' ~7 gDATE: 01-29-2016 HOTFIX VERSION: 064! h/ S6 v) B* F6 S+ w+ L' H; u
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' o: A4 l- T p- c7 d' {4 C# u; t1510387 FSP EXTERNAL_PORTS Break in extending a net as a deep connection when it is targeted to multiple FPGAs connected in a daisy chain
, R2 s) J2 W6 a1 L' q @+ q5 I1514132 ALLEGRO_EDITOR INTERFACES Element position changes after importing DXF
8 S% @* Z4 t8 M& B) M1514285 ALLEGRO_EDITOR TECHFILE Importing .tcf file from Constraint Manager does not import user-defined properties.2 P. Q; a6 q6 v# m. z4 t3 Q
1515580 ALLEGRO_EDITOR EDIT_ETCH Sliding routed differential pair signals results in odd angles if the 'Dynamic Fillets' option is selected
0 B1 H f$ J" e" b; {4 c1519040 ALLEGRO_EDITOR DATABASE Match groups are lost when a board created in SCM is saved in Allegro PCB Designer.' |4 j3 j8 Z$ M
1519910 CONCEPT_HDL INTERFACE_DESIGN Hotfix 62: Information on manually-remapped port groups is not saved, but reset to default* t2 \2 V9 Y0 L c J
1519943 ALLEGRO_EDITOR DATABASE When user units are changed from 4 to 2, the design seems to disappear from the canvas7 O* `- T8 z+ [3 {
1519946 CONCEPT_HDL CORE Renaming a net leads to loss of constraints associated with the net
4 B1 k( h+ c( \9 [, X: Y1519987 ALLEGRO_EDITOR SCHEM_FTB In Hotfix 61, constraints are lost on importing a netlist
6 r0 \3 a; Q4 U6 [. t1520727 CONCEPT_HDL CORE In Project Manager, the 'Design Sync - Export Physical' command does not automatically update the schematic2 O+ }! j$ j) d+ Q
1521174 SIP_LAYOUT DIE_STACK_EDITOR Padstack shapes not converted correctly to die-stack layer using Die-stack Editor
# W* k5 l8 ^6 E' g5 m0 `; H$ h9 ?/ h1522227 SIP_LAYOUT IC_IO_EDITING SiP Layout stops responding when trying to add a co-design die (.xda file)! _/ k' ?; W6 c; G7 \7 x
1522900 ORBITIO ALLEGRO_SIP_IF Padstack shape distortion after translation to OrbitIO from SiP design; V& e) @+ _/ g8 t% P0 o, [' r
1523237 ALLEGRO_EDITOR SKILL SKILL function axlDBGetExtents() causing PCB Editor to crash& o+ r4 H6 Z$ ~5 V l5 ]6 R
1524641 ALLEGRO_EDITOR DATABASE PCB Editor stops responding when updating outdated dynamic shapes
/ d6 y) t+ a2 z# I1525432 CONSTRAINT_MGR OTHER User-defined property not being transferred from DE-HDL to PCB Editor3 R" v& M! v% G; v, A! A i* k
1525948 F2B PACKAGERXL Reference designators assigned by the Packager tool are not correct
' W/ e2 t/ t+ X/ Q1527321 ALLEGRO_EDITOR SCHEM_FTB Unable to create netlist with the 'Open Board in OrCAD PCB Editor' option in Hotfix 63
1 q+ u% B) B' S: |" t1528254 CONSTRAINT_MGR CONCEPT_HDL Import Logic with the 'Overwrite current constraints' option is deleting some attributes6 t0 W8 ]* | b5 w* f
5 A. D9 g8 @* F# V) K
DATE: 01-15-2016 HOTFIX VERSION: 063' u8 H. H* l8 r6 {9 d1 [4 l! H
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1472414 ALLEGRO_EDITOR SCHEM_FTB netrev changes pin-shape spacing rule in constraint region5 N- Z$ r5 l3 T
1494194 CONCEPT_HDL CORE Random display of the 'PHYS_NET_NAME' property in hierarchical designs) P& u. s. z* }9 P) v: T( x! l9 W
1500190 ALLEGRO_EDITOR EDIT_ETCH Snake Router Creates Line-to-Line DRCs
# _3 u$ x t) L. P1501093 SIP_LAYOUT OTHER Package design variant shows wirebonds connected to a die which is not part of the variant
6 V' _- g& Z$ [! f- m* c/ ]" I1509184 ALLEGRO_EDITOR DATABASE BB vias in mirror have terminal pads suppressed by artwork1 c4 o; u, n# X0 Y7 K) @' D7 t% C
1511397 SIP_LAYOUT TECHFILE Tech file exported from release 16.5 cannot be reused in SiP Layout in 16.5 or 16.6
! }" }" F8 h" ]4 p1 h! D1511744 ALLEGRO_EDITOR OTHER Allegro PCB Editor removes property from component instance; o4 \4 L$ }4 T8 N7 l0 I
1511761 SIG_INTEGRITY OTHER Allegro PCB Editor crashes on running the cns_show command.
4 r5 L! o7 ?8 R( O3 D5 f1511787 ALLEGRO_EDITOR INTERFACES IPC-2581 not exporting overlapping shapes correctly.* o/ s- w$ m2 ^( X
1512071 ALLEGRO_EDITOR OTHER The color of 'SHAPE PROBLEMS' subclass is reflected in the color of 'NCLEGEND-1-4' subclass when executing PDF out
0 s$ A q( u( G5 @1513085 CONCEPT_HDL CORE NC pins combine with NC_1 and routed as one net in Allegro PCB Editor* _: S! G- A! X8 a7 ^
1514469 CONCEPT_HDL CORE Unable to get rid of an underscore from the PHYS_NET_NAME property
; p( q, C; P4 N9 p% |5 ~$ g1515318 PCB_LIBRARIAN IMPORT_EXPORT Import Pin Table: 'CTRL + C' and 'CTRL + V' not working correctly( `- S) |* c+ @/ j# s5 \0 l
1516093 ALLEGRO_EDITOR PADS_IN Pads library translator does not translate slot orientation: q$ m: C: }" s" e2 }
1517351 CONCEPT_HDL CORE Genview does not update an existing split symbol# }# ^+ O9 w2 _1 ?
1518032 CONCEPT_HDL SECTION How to get rid of error 'SPCOCN-2009 - Symbol has the SEC property but the required SEC_TYPE property is missing.'2 ], r2 X4 L: {! B! D& v
1518724 PCB_LIBRARIAN PTF_EDITOR PTF Editor is not saving changes
. r# y1 R) R- a6 G1519518 CONCEPT_HDL OTHER Genview does not generate split symbols6 P+ n( m1 p# e, `
1519623 CONCEPT_HDL CORE Differential pair added to a NetClass does not display 'NET_PHYSICAL_TYPE' on the canvas/ V5 I2 M" x! }5 [! ~% K) T% m
1520207 CONCEPT_HDL CORE Genview crashes after renaming ports2 }2 m- z ?5 F# r# o+ Z
& p; k; ?8 B9 e- C$ Z* T( i
DATE: 12-11-2015 HOTFIX VERSION: 0626 a6 N9 I( P- N% k) p
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1012606 ALLEGRO_EDITOR REPORTS Natural sort option for Report output2 @9 z$ e+ ^1 [
1408218 ALLEGRO_EDITOR MANUFACT Specifying the Offset value results in unexpected value of the NC Route coordinates in the .rou file
; l- s: c& T1 e7 `/ F1440509 ALLEGRO_EDITOR PLOTTING Ratsnest do not follow the refdes position when plotting the BOTTOM layer with the 'Mirror' option1 O! T0 L2 X, `8 S- K3 t8 {! @
1444144 ALLEGRO_EDITOR DRC_CONSTR The 'add taper' command generates line to line spacing DRC1 J1 j# y* t& v' v3 d
1471275 SCM UI Allegro System Architect (SCM) - Allow sorting on the pin number field in the Matrix view
1 C5 j3 k1 T1 u; _9 Y1474764 ALLEGRO_EDITOR PLACEMENT In SPB166 Hotfix 56, the place replicate create command does not produce desired results if the fanout is marked
: P8 S* t; ?- x& L) l$ i) G1474894 ALLEGRO_EDITOR PLACEMENT Place replicate fails to include vias when the module is applied to other circuits.
/ v* z$ t2 H6 Q# m8 B1485931 ALLEGRO_EDITOR INTERFACES Errors generated when importing IDF in an existing board file
8 d# a: d6 M0 n0 \1 E2 j: L1487603 SIP_LAYOUT WIREBOND SiP Layout XL - Add multibondwire option to non-standard wirebonding3 n8 x4 R: }* z) s3 b+ Z
1490311 SCM OTHER Block Packaging reports duplication when it should not
8 p$ S {: ^# l$ X# I+ l8 ]1491272 ALLEGRO_EDITOR EXTRACT Incorrect information exported to DXF if the value of SeparateSlotHoleLegend is set to 'yes'$ D2 Q j m# ~ ?$ p
1491521 F2B PACKAGERXL Packager reports error (SPCODD-269) when there are duplicate subdesign suffixes - need a clearer message
% N) \6 |( ] U) t+ \1492013 CONCEPT_HDL CORE Stale PNN properties not cleared from schematic on packaging design (backannotation)
! c6 e+ S$ U% D: F- @1492703 CONCEPT_HDL OTHER 'Global Property Display' not working for symbol edit
& h1 U# K' f0 a8 Q- z" [1495296 SIG_EXPLORER OTHER The T-point sequence in SigXplorer is different from the layout
" C* ~* p! u& R- I# D0 B1495789 ALLEGRO_MFG_OP CORE DFM checker checks for laser vias ( LVDC, LVDP, LVDT )
' a* `# ]( L! p M2 R- r) ~1496286 ALLEGRO_EDITOR PLOTTING Export PDF is not exporting hidden, phantom, and dotted line types
, K$ F: ~. _4 e0 g9 d) w2 M' g8 R1499051 ALLEGRO_EDITOR PLOTTING PDF Publisher reports error for a donut shape model in the layout - 'Shape symbol cannot have a void in a shape'# P( `3 S' t. V- D
1499380 SIP_LAYOUT DEGASSING Oblong shape degassing voids are not created correctly
: ^* k+ k( U7 U$ U0 [1499538 ALLEGRO_EDITOR PAD_EDITOR Pad_designer does not allow layer name change from Begin_layer to diepad1_top; dbdoctor does not fix this/ _5 G# b* |/ h* b1 k" R. ]1 Y
1500422 ALLEGRO_EDITOR SKILL SKILL function, axlTriggerSet, results in PCB Editor crashing at launch
, }% {% r. x, h4 D5 @# s" ~- U2 p1500659 FLOWS PROJMGR Need the ability to ensure that the standard library is not added to the project libraries list by default$ M; ?: S3 y6 W. t
1500725 F2B PACKAGERXL Unable to clear pstprop.dat file conflicts
: f6 U# Q5 s1 u8 _8 F* \5 ]1501139 ALLEGRO_EDITOR PADS_IN Pads_in creates pastemask for Through Hole padstacks
) W( S @$ G# I& A1501165 F2B DESIGNVARI TDO does not manage overlay files and variant_roz1040660_1.ba cannot be created unless variant_merged.dat is checked out
; f+ J0 s! q; a# L4 O2 ]1501774 ALLEGRO_EDITOR OTHER PDF Publisher: If text is attached to an object, the object is also printed in the PDF6 T+ u( I8 w+ N0 }4 O$ N
1501898 F2B DESIGNVARI Variant custom variables are visible in the schematic border but are not there in the Variant Details form1 X" t- z4 D* G
1501974 F2B PACKAGERXL 'Feedback has found Illegal pin swap(s)' error although the pin was already swapped and fed back (B2F) to DE-HDL% X! Z4 y" j7 C
1502782 ALLEGRO_EDITOR SCHEM_FTB Allegro System Architect (SCM) - Export Physical stops unexpectedly without any errors or warnings
, i. c9 O. [# |. F; I1503551 APD STREAM_IF In SPB166 Hotfix 60, error reported if a self-intersecting polygon outline exists at a specific location
2 j- |! l1 K0 V9 n$ C1504093 ASI_SI GUI View Topology and Waveform buttons overlap when Signal Analysis window is resized. a( z! x6 S& d) x% Z+ u
1504767 CONSTRAINT_MGR SCHEM_FTB Constraint Manager generates errors if the 'sNoF2BFlow' property is added to the Constraint Manager Dictionary
! m: V, H# A5 s4 Q. Z ]4 S1505497 SIP_LAYOUT LOGIC Assign net fails to fully connect propagated items
5 D T7 ^4 Q. J0 l1506110 ALLEGRO_EDITOR DRC_CONSTR No DRC shown when a text on etch layer is overlapped on mechanical pin
- a8 p o( S+ |$ X9 v1506654 CONCEPT_HDL INTERFACE_DESIGN Netgroups broken when moving
+ Y3 g( P* |, j5 d1506983 ALLEGRO_EDITOR SKILL axlBackDrill SKILL command crashes PCB Editor after backdrill analysis is run when App mode is set to None2 d" G- D* K7 @; a8 s g0 _! e
# @' n* o# b$ F R3 D9 W8 Z: R: B; c
DATE: 11-20-2015 HOTFIX VERSION: 061
; k# m) k C6 i3 X* p: L===================================================================================================================================
' D. m! {4 J: J. b0 g7 nCCRID PRODUCT PRODUCTLEVEL2 TITLE
C. ~6 y& e) i5 H+ [8 j% Q===================================================================================================================================. A) u) B; `3 f; q/ V. ?9 }: h z
1306441 APD OTHER The Minimum Shape Area option in Layer Compare uses an unspecified value2 X# c; I7 |. M. J7 o _
1342644 ADW COMPONENT_BROWSE Need directive or method for Component Browser to load a search criteria file upon init P+ S/ k( W0 l! J' {4 q
1413248 CONCEPT_HDL CORE Import from another TDO project makes the block read-only
: S1 K' ^6 W- s1417429 ALLEGRO_EDITOR INTERACTIV Pick box only accepts 1 set of values. You need to close the box and reopen it to draw a rectangle4 z# ]( ?6 `8 g, a
1417442 ALLEGRO_EDITOR INTERACTIV Spin via stack and only part of the stack spins
* R I0 T5 Q; g6 e* X ?; ^% ]1451977 CONCEPT_HDL PDF Origin of PDF mediabox not starting at (0,0) when PDF page_height and page_width are set
- b/ r4 w2 x0 h' E" c1 _6 N) I2 `2 F1453527 ALLEGRO_EDITOR EDIT_ETCH Contour route hugs the outer edge of the route keepin
' u; X' U3 d) n$ r' t, j( _( _1464948 PCB_LIBRARIAN VERIFICATION The errors/warnings do not match between the various tools
* h9 f$ \; u% I6 _: F6 y+ Z: w1467826 CONCEPT_HDL PDF PublishPDF from Console Window creates a long PDF filename
) {' p- L0 K5 v6 O1478639 CAPTURE OTHER Capture Browse Nets window does not display all nets* a! x' d: @! I' ?1 ?
1479177 SIP_LAYOUT OTHER Pin pair constraints do not appear to be supported in Sip Layout XL
/ h. l( Q( n" L- ?- S; B: \! G1479227 CONCEPT_HDL CHECKPLUS Custom DE-HDL Rules Checker rule flagging invalid voltage in hierarchy
% C% ] w8 u, {9 B( o; z8 K1479454 CONCEPT_HDL OTHER DE-HDL issue: locked DIFF_PAIR property is editable! r0 S0 c; ]8 F2 R
1480293 CAPTURE PROJECT_MANAGER Capture hangs when searching for all nets8 \: c, @9 }# H9 e- \) J0 u0 R
1483894 CONCEPT_HDL CORE Import Design hangs when pull-down arrow is clicked twice
% j* u/ R3 J# a0 i' m1484781 CONCEPT_HDL CORE Three different Hierarchical Viewer issues: d; T: T7 A/ A
1485059 PCB_LIBRARIAN CORE Part Developer pin attributes are randomly marked as read-only
6 y# N) V2 {8 r$ ^1 t+ c1485960 CONCEPT_HDL CHECKPLUS Custom DE-HDL Rules Checker rule is crashing the project
P$ K. ]4 G% P0 @% c1486086 ALLEGRO_EDITOR ARTWORK Cannot generate artwork.$ D9 H" P; r( [! Z1 {3 x
1486834 CONSTRAINT_MGR OTHER Restore the Status column in cmDiffUtility
. h/ }% P$ z: N# m; |1 r5 N1487085 CONCEPT_HDL CONSTRAINT_MGR Import Physical with the Constraints only option reports problems
" W5 n5 T7 W- A% ?; Y( y# S1487197 ALLEGRO_EDITOR DRC_CONSTR Drill to Via DRCs are not being reported
8 `5 s# [0 [2 g1 v% x2 b1487265 CONCEPT_HDL CORE Replace command in Windows mode shows incorrect behavior
7 J3 @, ^* y# X u* `9 |% s1487733 CONSTRAINT_MGR OTHER Running Export Physical - It takes over two hours to update the PCB Editor board5 g3 H1 }" x7 |8 I* O: ^
1488758 CONCEPT_HDL CONSTRAINT_MGR CM_VALIDATION_ON_SAVE should be a hard stop on Constraint Manager) F6 R# W& Z& P6 u. a
1490299 SCM OTHER ASA does not update revision properly- C! h# X0 y. y$ O) m
1490744 ALLEGRO_EDITOR SKILL axlChangeLine2Cline changes line to cline and places it on the TOP layer1 s/ W4 B6 G6 O( v/ `
1490924 F2B PACKAGERXL Save Design/Export Physical is resetting Via constraints$ {% w9 R# g- b: k- D
1491351 ALLEGRO_EDITOR OTHER Create Detail for bond fingers on a custom layer not working% ~! T1 w" E% q& r: v' F9 |6 s
1492595 ALLEGRO_EDITOR MANUFACT Dimension character substitution help is wrong" s& J+ v5 V* g' ^5 z6 a( ^
1492777 ORBITIO ALLEGRO_SIP_IF OrbitIO import of customer mcm results in crash
0 a& W2 ^ G6 L/ K1492901 CONCEPT_HDL CORE Cannot instantiate a multi-sections symbol (> 10 versions) in Design Entry HDL( ?8 G/ L; L9 p! T! p
1495621 ALLEGRO_EDITOR INTERFACES Oval pins are placed with wrong orientation in IPC2581
# W: J6 J% z; P U' W1497597 ALLEGRO_EDITOR DATABASE Show Element on pin shows wrong drill size& D z8 g/ c/ I7 j3 J8 K9 c
1497956 CONCEPT_HDL CORE ADW Library Flow test schematic generation crashes DE-HDL while saving the design when using customer adw_conf_root8 L( T! Q- [& z9 f& z9 V$ p
1498234 ALLEGRO_EDITOR ARTWORK PCB Editor fails to create artwork and no error is listed in the log file
+ ?* [+ f8 j/ I% t/ P5 B C1499363 CONCEPT_HDL CORE Custom attributes under variant management stopped working in Hotfix60 |
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发表于 2016-6-29 12:21
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发表于 2016-8-17 13:05
