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偶也跟一贴！
" Y/ d/ M/ V' o& a7 S; o5 d0 U以下内容来自《high speed digital system design》。1 O7 d& V! D7 v1 j, z$ f9 \- ~
% S) W! K& L% E2 Z1 v4 G, [A via is a small hole drilled through a PCB that is used to make connections between various
~( T# w" h+ ?. N) t# P5 [layers of the PCB or to connect components to traces. It consists of the barrel, the pad, and0 M2 C- E6 v- ?) Q) e/ N. K
the antipad. The barrel is a conductive material that fills the hole to allow an electrical. K2 A0 U9 o0 w2 Q, N3 s8 j' }
connection between layers, the pad is used to connect the barrel to the component or trace,/ c+ M& I. T; J( b
and the antipad is a clearance hole between the pad and the metal on a layer to which no
* ^5 X$ _; i3 r$ I. Sconnection is required. The most common type of via is called a through-hole via because it5 M7 D6 ]$ h9 E5 R6 [6 D3 P w
is made by drilling a hole through the board, filling it with solder, and making connections on/ Z! ^! \5 H# k3 M3 q5 y# o
appropriate layers via the pad. Other, less common types of vias, used primarily in multichip- L+ Q9 l# b! u
modules (MCMs) and advanced PCBs, are blind, buried, and micro-vias. Figure 5.1 depicts# ]; h9 z; Q* [( O* ?" O
a typical through-hole via and its equivalent circuit. Notice that the pads used to connect the- I" m6 U4 Y# o% Z* b& y' O
traces on layers 1 and 2 make contact with the barrel and that there is no connection on
4 Z* \ L. }0 X k5 p% F& q% @layer 3. Blind and buried vias have a slightly different construction. Since through-hole vias
5 z. k. J# A: ^+ s) o" \are by far the most common used in industry, they are the focus of this discussion.
" Q9 C1 b7 T, B7 K- W0 D7 z! q) C- V; }5 u4 g' I- |5 H$ \
Notice that the via model is simply a pi network. The capacitors represent the via pad8 n! _! h7 _( X4 o/ }5 N6 y
capacitance on layers 1 and 2. The series inductance represents the barrel. Since the via
/ ]) T/ H9 ]! D+ E* Cstructures are so small, they can be modeled as lumped elements. This assumption, of+ S# W% ~# ?. B0 E9 W
course, will break down when the delay of the via is larger than one-tenth of the edge rate.% r3 }4 e* A3 Z2 ^/ T
The main effect that via capacitance has on a signal is that it will slow down the signal edge
% `- Q; V4 x$ r2 H% o8 l4 [, ?rate, especially after several transitions. The amount that the signal edge rate will be slowed
2 E+ c' S3 S* Wcan be estimated by examining the degradation of a signal transmitted through a capacitive( e2 W. U) [! C
load, as shown later in this chapter in equation (5.21). Furthermore, if several consecutive* g7 e. S2 H2 U
vias are placed in close proximity to one another, it will lower the effective characteristic
& c, B. h/ A! d# F4 t3 S! j4 R+ {impedance, as explained in Section 5.3.3. The approximate value of the pad capacitance is4 r4 X3 I8 b& `* i( c. |
[Johnson and Graham, 1993]
& |3 `' B" ~9 }
; N- n2 o* ?, C[ 本帖最后由 killerljj 于 2007-11-21 20:51 编辑 ] |
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发表于 2007-9-11 14:20
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发表于 2007-9-15 15:34
俺也顶一下,因为焊盘描述的太形象啦!
发表于 2007-12-19 08:39