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Fixed CCRs: SPB 17.2 HF021
- ?$ |0 m0 {6 Q; K* t* K+ W$ _+ a06-3-2017
2 Q+ u t% c( P; y& R+ g2 K========================================================================================================================================================# ] }, q% Y& b' Q
CCRID Product ProductLevel2 Title
, Y% r1 ]: e' }" v5 A0 y, {0 i# `* F9 o" E========================================================================================================================================================) T7 D8 v# s+ Y6 u" z+ M- u
1401318 ADW DBEDITOR Bulk Edit - Previously modified cells do not turn blue when selected9 j, D3 n2 L5 F' m' `5 V3 N
1621446 ADW DBEDITOR Bulk Edit - sorting highlights incorrect cells to mark them as changed
/ k, r8 i# a; O6 ~2 g1743997 ADW LIB_FLOW Match file for standard models is incorrect
! e: B. N! N4 O! x3 N7 c1746052 ALLEGRO_EDITOR DATABASE PCB Editor crashes when applying no drc property
# t. T7 ~: k7 o1736067 ALLEGRO_EDITOR DRC_CONSTR Interlayer checks not reporting DRCs between cline and mask layer$ k9 @9 w* s- K/ [* D, ?
1738587 ALLEGRO_EDITOR EDIT_ETCH Line width changing on slide for ETCH - Conductor (Not on a NET)
1 l4 z$ g; o6 K1745277 ALLEGRO_EDITOR EDIT_ETCH PCB Editor crashes on using the slide command
) Z6 l k6 u$ x1747942 ALLEGRO_EDITOR EXTRACT Fabmaster Out does not export arc in pad_shape, k! G, N/ G6 w
1737202 ALLEGRO_EDITOR GRAPHICS Setting the variable display_raster_ops
, o9 ]/ Q" q0 f1744042 ALLEGRO_EDITOR GRAPHICS Unused pad suppression is not working on few nets
# E7 A% u d `% J( v; s& c/ e1703848 ALLEGRO_EDITOR INTERFACES IPC 2581 fails with error 'E- (SPMHGE-268)' and the log file is empty# j6 \& E9 v/ F" s& W' a: W
1743899 ALLEGRO_EDITOR MANUFACT Glossing dangling vias crashes PCB Editor
! Z7 Q- p5 {: g: D2 e1744467 ALLEGRO_EDITOR OTHER The 'logical_op_new' variable is not displayed in User Preferences Editor
/ x2 P' y+ ~) U6 |3 d n1 C& W, \1748520 ALLEGRO_EDITOR OTHER TDP fails to load on an empty database
7 T# X/ g' f- t- G- ^! S! U1748581 ALLEGRO_EDITOR PAD_EDITOR Padstack Editor crashes when changing default pad geometry, h d6 K6 `' ^- }& ~5 U# E
1751469 ALLEGRO_EDITOR PAD_EDITOR Padstack Editor crashes/freezes when browsing for a shape symbol
' `3 k- @; }# J; A. n1 M) v1725948 ALLEGRO_EDITOR SHAPE Shape differences after conversion from release 16.6 to release 17.2-2016
' U# m. K* b3 q X) O1729306 ALLEGRO_EDITOR SHAPE Seting shape_rki_autoclip variable causes no void to be generated
, J/ i) }- r# ?: E+ ^1698876 ALLEGRO_EDITOR UI_GENERAL Tabs are large and text is compressed in release 17.2-2016
* s" \' B6 W. i1 W ]7 O1698883 ALLEGRO_EDITOR UI_GENERAL In release 17.2-2016, enlarging icons makes selection boxes/text unreadable on 4K monitors
" g+ A( \( Q& j! n' C0 O1707933 ALLEGRO_EDITOR UI_GENERAL axlUIMenuFind not locating menu as per x_location; \' \1 E+ x. [1 x9 r, d: d& Y
1741460 ALLEGRO_EDITOR UI_GENERAL Right-click, context menu options grayed in some cases after choosing Edit - Copy9 b7 Q4 b2 L+ N1 [' U
1747588 ALLEGRO_EDITOR UI_GENERAL Interacting with PCB Editor by sending messages is not working
1 p& G9 q0 w( U! K% c. |, c* l1747488 APD EDIT_ETCH Route connect is improperly affecting existing routes in locked high speed via structures$ {% x7 q0 M: y! y8 ?: }% Q: B
1750182 APD STREAM_IF The stream out settings are not saved) j+ I2 f: c- V3 P ~' i
1752067 ASI_SI GUI Links to differential waveforms do not work in Sigrity SI report( S' R' Y% m% L. W; ]/ r
1752131 CONCEPT_HDL COMP_BROWSER Symbol view in part manager doesn't match the symbol version, j- T8 ?3 W5 j' {
1754116 CONCEPT_HDL COMP_BROWSER Default Symbol selected is n°2 instead of n°1 in component Browser8 U3 A k6 [" _! l
1754949 CONCEPT_HDL COMP_BROWSER Part Information Manager displays preview window with the wrong symbol and missing footprint. H+ T( c: j; M/ O
1721334 CONCEPT_HDL CORE dsreportgen not able to resolve gated part on schematic
5 W( ?: ]( r& A( i1750916 CONCEPT_HDL CORE DE-HDL crashes when trying to uprev a project in release 17.2-2016+ V7 u* S5 Y6 Y8 D
1711487 CONCEPT_HDL INFRA Restrict opening of release 16.6 designs from a release 17.2-2016 design using File - View Design
) P P" _6 z$ e% R' C7 J1746915 CONSTRAINT_MGR CONCEPT_HDL Unable to copy a Physical and Spacing CSet generated from the Constraint Automation flow+ m2 y- z% |6 {
1743523 CONSTRAINT_MGR DATABASE Suppress warning pop-ups from the constraint automation script
( l/ b9 o" d" ^- W1 }# [1746941 CONSTRAINT_MGR UI_FORMS 'Go to Source' from DRC tab is not working in release 17.2-2016 K% @9 i$ U4 Y& {, N5 W
1753010 ECW METRICS Metrics not getting collected due to old license in use4 b* l# l$ c( q
1713052 FSP GUI Pin/Port Name and Group Name are not aligned properly in FPGA Port and Use Pin Mapping for DeviceInstance
" g- y. s$ s' `+ [3 _0 H1 T4 b' W1719099 FSP GUI Net naming wrong after building block% N; U0 D5 }. J$ c2 A
1719105 FSP GUI Tabular sorting not working in FPGA System Planner
$ ]# e; }2 a2 k1 c1720479 PSPICE ENVIRONMENT Probe window does not open consistently on Windows 10 systems
5 _8 ~8 e& _9 K3 r; [1 z. X" z1723411 PSPICE ENVIRONMENT Probe window does not open consistently on Windows 10 systems3 k% ]0 f2 A* C3 Q0 H$ ?
1746628 PSPICE ENVIRONMENT PSpice Simulation Manager displays same message for all simulations in release 17.2-2016, Hotfix 0164 S2 D2 b3 j& J: M5 a4 R9 X- E7 F
1745976 SIG_INTEGRITY GEOMETRY_EXTR Arcs with coplanar waveguides are extracted with incorrect spacing7 ^9 C$ Z' D6 z/ }6 `* h6 A
1690820 SIP_LAYOUT PLATING_BAR Cannot add fillets to pads with plating bars in release 17.2-2016: W/ _: Z; @- Y& b7 N$ Y6 [
1725042 SIP_LAYOUT PLATING_BAR Creating a plating bar removes dynamic fillets
8 M- R. E1 \/ j6 ]5 E I* [1747534 SIP_LAYOUT SHAPE Moving fiducial crashes SiP Layout
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发表于 2017-7-2 18:37
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