|
|
EDA365欢迎您！
您需要 登录 才可以下载或查看，没有帐号？注册
x
Since the earliest days of microprocessors, system designers have been plagued by a problem in which the) P) p; f# B4 C* {; r
speed of the CPU's operation exceeded the bandwidth of the memory subsystem to which it was connected.
+ b/ P; ]: E$ U6 F) ~To avoid wasting CPU cycles while waiting for the memory to fetch the requested data, the universally) g: s; {& x+ B, a2 t
adopted solution was to use an area of faster (and thus more expensive) memory to cache main memory data.1 X, X: z8 E H
This solution allowed the CPU to operate at its natural speed as long as the data it required was available in z' a7 R7 [: Q, i5 z. R `; U4 L
the cache. |
|
/1 
发表于 2016-8-22 10:05
QQ好友和群
QQ空间
腾讯微博
腾讯朋友
微信
收藏
支持！
反对！
