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$ P1 {- f0 y% P& p1 ?; [SystemVerilog for Verification:" ^; D% X2 o( W1 x' ^
A Guide to Learning the Testbench Language Features; w8 V! r6 Z# N0 M: k' \
1. VERIFICATION GUIDELINES 19 Y( Q' J* c% D- g O3 d- t# V
1.1 Introduction 18 V! Z# G6 N5 Q O* X
1.2 The Verification Process 21 b! \. \* u' A& Y4 n
1.3 The Verification Plan 4; N! y+ B( @7 M3 g
1.4 The Verification Methodology Manual 4- J; z! f4 A$ I
1.5 Basic Testbench Functionality 58 b& `( K& _/ Q: a9 k" B& n
1.6 Directed Testing 5
! I/ S; a1 M7 _* I1.7 Methodology Basics 7, I( S0 [; Q$ n; r: ^7 h( P
1.8 Constrained-Random Stimulus 8! P# a5 F- j7 w, h; u+ T! _
1.9 What Should You Randomize? 10
F; q6 A2 n5 U v: o: o' s5 x1.10 Functional Coverage 13
1 @) G4 ^$ k7 J$ f+ ?% l) J. j1.11 Testbench Components 154 L( j8 G. c8 q5 x
1.12 Layered Testbench 16
! }8 C" a! Q. [4 G% d. c1.13 Building a Layered Testbench 22
* q( ], [8 N3 q6 C7 @8 ]4 J3 l+ |1.14 Simulation Environment Phases 23
' F# f9 X$ M; C0 T1.15 Maximum Code Reuse 24. ?- y7 j6 M- X( n
1.16 Testbench Performance 24
, v& M' X. M. Z) Q1.17 Conclusion 25
8 c; w! l3 W4 ~0 t z9 b# N- L2. DATA TYPES 27
1 x7 l* j+ W0 C2.1 Introduction 273 L- u7 Z. v, f, O
2.2 Built-in Data Types 27
4 C# V$ h4 E% `. s8 qviii SystemVerilog for Verification
; j( ~& J; t: M) k5 o7 N+ z' l2.3 Fixed-Size Arrays 29: y2 w! a9 a: Y+ k! `4 c: _2 F
2.4 Dynamic Arrays 34 P/ V# N8 j: e c/ z4 w" M
2.5 Queues 36
T( O+ o0 L: Y& g; N2.6 Associative Arrays 37
Q, u, o: f, b2.7 Linked Lists 398 Q3 g) P& P# k1 w1 q; Y' h
2.8 Array Methods 40
1 B1 F6 y# S) w' D. ]: c( N- H2.9 Choosing a Storage Type 42
2 @5 B. ~7 V5 D+ x9 A4 D2.10 Creating New Types with typedef 45
# ?) o0 u# o' ^3 [3 @- }2.11 Creating User-Defined Structures 46" W8 G) y; R! X$ Y. F+ f6 s
2.12 Enumerated Types 47
3 X @8 X1 A5 l0 F! p. `2 G2.13 Constants 51
% P$ r4 e7 S. B. {, d0 w* G2.14 Strings 51
/ }) H1 B; R* n* g2.15 Expression Width 52
% V' v% I$ f2 ~* b/ i6 r2.16 Net Types 53
# ^- C2 T. W x! R7 R2.17 Conclusion 53
- d/ M! v" D" s9 q3 b3. PROCEDURAL STATEMENTS AND ROUTINES 55
6 c+ `8 q& o9 `% G4 a/ O/ |# z: y3.1 Introduction 556 C" W5 R1 L. ` |
3.2 Procedural Statements 55. ^) b5 n) G( \% E& \* @
3.3 Tasks, Functions, and Void Functions 56
4 X7 W2 I! W# e3 E3.4 Task and Function Overview 57
2 i5 l' y+ Z! J& n) q: ?3.5 Routine Arguments 57! U9 C+ t1 |7 Y4 `
3.6 Returning from a Routine 62/ [+ n( n' Z) K0 a0 q: A5 g
3.7 Local Data Storage 62; ~$ q! M7 V3 ]& P0 O3 ?
3.8 Time Values 64. c1 N, U+ i& h
3.9 Conclusion 65
8 S1 r6 l+ }, ?$ [* l4. BASIC OOP 67
9 M2 Y" e+ a( J/ k4.1 Introduction 67
; c5 ?& Y* C+ s# w" B8 B: h( t. x4.2 Think of Nouns, not Verbs 67
6 Q! [- F6 ?) j( G+ m: L3 d; C6 F4.3 Your First Class 68
/ A+ @) H+ `) [) L' v N4.4 Where to Define a Class 69
; s: r# F; B; r v8 @! p4.5 OOP Terminology 69/ ^# T/ ^ o1 V: r, F, x
4.6 Creating New Objects 70$ y- u$ ?- }6 l& |1 }8 }, G1 j
4.7 Object Deallocation 74
% K! v( Q. A# ^+ s" h4.8 Using Objects 761 @1 B( `% Q: y7 \
4.9 Static Variables vs. Global Variables 763 [/ S' X) h! G( @6 `
4.10 Class Routines 787 g' F* P9 n) T1 X! s8 |% O7 S5 a
4.11 Defining Routines Outside of the Class 79
2 f! I0 ~- F& w2 i4.12 Scoping Rules 81) \. a. v4 X) c6 F `6 c- \
4.13 Using One Class Inside Another 85
' S( d0 |+ ]7 J* q4.14 Understanding Dynamic Objects 87
; F" _9 p( [$ B$ H4.15 Copying Objects 91
( z* H. V/ j9 R: b5 z( Z4.16 Public vs. Private 95: ^# u$ k, t& A. J- K6 C- X& ~7 R
Contents ix
3 j& J: y7 P, S X( |( I. J9 n4.17 Straying Off Course 96
; ?# U% _( o L0 F6 p4.18 Building a Testbench 96% _6 x1 a& v$ o- R& y, `7 ?/ [% P1 p
4.19 Conclusion 97
; m1 M" ?+ X6 k9 U! Y; O: y5. CONNECTING THE TESTBENCH AND DESIGN 99, P7 m- H" z) {1 Z; ?" w7 j
5.1 Introduction 99# y! T: |8 z a
5.2 Separating the Testbench and Design 99
" V, Q$ T7 e4 b# d8 R( m- ^: ?5.3 The Interface Construct 102
$ X3 k6 j) \& u2 N7 s5.4 Stimulus Timing 1087 D6 C. Y0 s i+ O' H; i
5.5 Interface Driving and Sampling 114
7 ?5 J: Q; f3 V) i1 M, [6 N2 [5.6 Connecting It All Together 121+ e5 k: o% W4 E
5.7 Top-Level Scope 121
0 M F# v! [# R# I1 s5.8 Program – Module Interactions 1239 ~" r5 A/ C( r( f
5.9 SystemVerilog Assertions 124
* Z. |) X4 K; k8 M5.10 The Four-Port ATM Router 126! F. }; C/ T0 \! P f' l( k
5.11 Conclusion 134
- E6 t4 Y. W! Q4 F2 ^+ N6. RANDOMIZATION 135
' Q6 m r; z( S8 K6.1 Introduction 1353 f; @. U( P. \3 w" @
6.2 What to Randomize 136
# w7 M8 d' F: i6.3 Randomization in SystemVerilog 138 Z* |: L& k* l e4 ^# X
6.4 Constraint Details 141
" V/ L0 R& `- q% K2 n6.5 Solution Probabilities 149
( u2 ^; k' t+ n: b. `- P6.6 Controlling Multiple Constraint Blocks 1545 @# L* v+ \2 `7 }
6.7 Valid Constraints 154
1 @ V3 f% f) p! _' E9 {6.8 In-line Constraints 155
! f) V$ i- y# u3 r+ A6.9 The pre_randomize and post_randomize Functions 156
' j4 }5 c7 T5 U+ e9 z q6.10 Constraints Tips and Techniques 158
# Q- o6 \/ F+ d: H, ^6.11 Common Randomization Problems 164
& `3 a `2 ?' i# O9 d6.12 Iterative and Array Constraints 165- D" K! |4 i o' x
6.13 Atomic Stimulus Generation vs. Scenario Generation 172" C4 @- G6 g- x
6.14 Random Control 175
6 L S" a, a# v/ S- d- h6.15 Random Generators 177+ H# e0 }4 ~# @
6.16 Random Device Configuration 180+ M d* x/ R0 R# p- ~
6.17 Conclusion 182
# C- V, |# l' R' q% g; \7. THREADS AND INTERPROCESS COMMUNICATION 1833 K6 O+ b+ @6 j4 E
7.1 Introduction 183
. g) L. Q! a1 { {* M7.2 Working with Threads 184
: d0 Z% A7 j$ M: `2 p3 F7.3 Interprocess Communication 1942 u1 v& ]: | L4 g% [
7.4 Events 195
9 o9 f# }0 h' I4 f7.5 Semaphores 199& r/ \# L5 e1 t6 I+ @
7.6 Mailboxes 2018 b- A" o* ~1 V
7.7 Building a Testbench with Threads and IPC 210
3 g' o S% x" N# K% Yx SystemVerilog for Verification: ~% I- e% b% i
7.8 Conclusion 214) E# L# _& w; e$ L" e7 q
8. ADVANCED OOP AND GUIDELINES 2151 C% ]9 `6 n1 g# x
8.1 Introduction 215
) g% G- `% O# F1 o% R8 S8.2 Introduction to Inheritance 216
* i, x: \) K' l/ c$ E% C8.3 Factory Patterns 221
4 Y. `# u1 D; @" L( L8.4 Type Casting and Virtual Methods 225& d6 `! A% _# K
8.5 Composition, Inheritance, and Alternatives 228( t e; Y# v t4 i" E& |- d6 k; i
8.6 Copying an Object 233" Q/ Z1 F- P4 l) H( D4 ~
8.7 Callbacks 236) o8 Z$ t$ R L" ^+ ~ ~
8.8 Conclusion 240
: Y1 q7 D" z+ q& ^; n" ^$ \+ \1 p9. FUNCTIONAL COVERAGE 241
* W1 x0 `3 ^+ N& a. ?9.1 Introduction 241, B7 C5 C7 c. s; u0 B
9.2 Coverage Types 243
- U; Y8 j( e, k+ `9.3 Functional Coverage Strategies 246
. X9 e# c* X( a( Z9.4 Simple Functional Coverage Example 248* R) D4 T; c8 W
9.5 Anatomy of a Cover Group 251
4 g( V% \# h) e8 R" ~% U9.6 Triggering a Cover Group 2538 W: H( Y( Y. ?5 x2 ~
9.7 Data Sampling 256
2 C; p2 V( [0 G, m0 C- I2 }0 ]9.8 Cross Coverage 265+ a+ w ^" E j* h
9.9 Coverage Options 272
1 v5 A7 r( s+ Z3 r9 i9.10 Parameterized Cover Groups 274
+ F: O0 K" g7 w( ~- i9.11 Analyzing Coverage Data 2751 B X; R7 [1 B" Y7 i6 Z/ K
9.12 Measuring Coverage Statistics During Simulation 276
/ p- B; _4 c# O) o9 J9.13 Conclusion 277. R+ I9 ~( U; \/ s+ { h
10. ADVANCED INTERFACES 279
3 z! J+ Q6 w; K10.1 Introduction 279 Y8 A1 _4 S% P, [0 Q" k9 i! I
10.2 Virtual Interfaces with the ATM Router 279$ ~- I) O" P/ S, W3 y2 r
10.3 Connecting to Multiple Design Configurations 284
- T4 G8 q) D \- u2 |10.4 Procedural Code in an Interface 2902 Q. c6 c# u/ o
10.5 Conclusion 294
; c4 h" i( Y2 y! QReferences 295; I1 `$ L8 R; }
Index 297
8 Y4 S0 s. ]" q2 f) S! g |
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