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SystemVerilog for Verification:) n. b/ {: N# L4 X* Y _
A Guide to Learning the Testbench Language Features
; A; y$ V) u- E0 z1. VERIFICATION GUIDELINES 1
5 A3 u1 n W( V* u" n1.1 Introduction 14 J0 W6 T3 }- o0 J
1.2 The Verification Process 2
$ ?, u* P" B; x9 ^( S' [5 i1.3 The Verification Plan 4+ C8 B5 G) d' a/ C" l
1.4 The Verification Methodology Manual 40 [% C) u2 c3 U# H$ Y' A) w
1.5 Basic Testbench Functionality 5) p j P" N/ h O J6 w
1.6 Directed Testing 52 v% ^+ _2 V- B
1.7 Methodology Basics 7
C& z6 ^, B r( I, L1 G1.8 Constrained-Random Stimulus 8) F2 H( m% ~: C# \
1.9 What Should You Randomize? 102 D- }# e T5 q+ a2 N( W& Y% s+ `
1.10 Functional Coverage 13( @, H Q" I; i9 u) _4 U2 }
1.11 Testbench Components 15$ ~; d8 y) m4 ?# n2 R3 [7 q
1.12 Layered Testbench 16
6 n( ]" r! q) ^+ @ L: I. N1.13 Building a Layered Testbench 22
N' \/ X" B$ ^7 R. u f& \) b, G; @1.14 Simulation Environment Phases 23
: l4 {; d, p/ p# L7 ?# |6 `1.15 Maximum Code Reuse 24
" k: |( l" O/ {% X5 A* h& p1.16 Testbench Performance 24$ h' R+ y8 s, b, l
1.17 Conclusion 250 r9 k' o3 h6 k
2. DATA TYPES 27- M9 j4 v- a) p' \% j
2.1 Introduction 274 S: _" m1 z: s/ c, {/ D0 t
2.2 Built-in Data Types 27
! N+ E V' g. oviii SystemVerilog for Verification' k9 B( f" o: c9 K! _
2.3 Fixed-Size Arrays 29
% G8 |1 N ]* _1 T; x9 }2 ?0 a% K: Y4 a2.4 Dynamic Arrays 34
0 z) z, u+ m; X6 \6 [2.5 Queues 36' D) p+ K% ^- ?' t$ g
2.6 Associative Arrays 37) G) K! }' s& ~+ n
2.7 Linked Lists 39
5 N1 k% A6 I# q0 w6 @, v1 A" M5 ^+ E2.8 Array Methods 40
0 ^) ]1 K0 q& d& Z, j1 }2.9 Choosing a Storage Type 42
6 h( D* |' i9 N: c7 v, m2.10 Creating New Types with typedef 458 @. ?* }) Q# Z# _7 K" y6 v B
2.11 Creating User-Defined Structures 46
3 E$ C" e) a' ^) J( p" a2 Q7 y2.12 Enumerated Types 47
5 P& d6 \ S4 i2.13 Constants 519 _ a* J! m% x# I7 C
2.14 Strings 51. K6 i& n( Y! J& X _
2.15 Expression Width 52
9 s1 P. Q4 J% s2 G; }# ` `2.16 Net Types 53
1 [# ?: J( G1 o$ O+ Y2 d2.17 Conclusion 53
& D3 o6 J' d7 K$ ?+ N3. PROCEDURAL STATEMENTS AND ROUTINES 55
/ _2 u* q, I3 {4 g+ s- Q4 y3.1 Introduction 558 j% @% J1 U: ~* `
3.2 Procedural Statements 55
) @3 F$ A$ O# h: l- A* E3.3 Tasks, Functions, and Void Functions 56
+ g% I% Z$ `1 n2 _: p9 p& L3.4 Task and Function Overview 57' U( V* b. @3 c7 t9 F1 p4 u
3.5 Routine Arguments 57: a+ i5 d0 F O/ [- `% i6 t$ f* y
3.6 Returning from a Routine 622 u8 ]9 G) H6 s; u
3.7 Local Data Storage 62" c q& M! x% L B
3.8 Time Values 64
E( [/ f( T% r! f. T( ?6 {3.9 Conclusion 65+ B2 |8 _! d( U4 ]5 N$ P4 u
4. BASIC OOP 673 ~" _4 v6 v# C, v u6 ^9 o
4.1 Introduction 67
3 w r+ k& X3 v7 ^. G, B* c2 c4.2 Think of Nouns, not Verbs 67( @& i4 T: |9 {; i4 c8 I
4.3 Your First Class 68
5 J, t5 T: H2 M! S, U2 D/ G4.4 Where to Define a Class 69
' ~5 W4 B2 D' J; p8 ~4 Y6 R4.5 OOP Terminology 69
& `0 a( Y% ~! I0 O) B. F4.6 Creating New Objects 70( Q$ u4 [" g, R8 {% f; [: p
4.7 Object Deallocation 74
$ o' j+ v6 L2 Y) q' ~, c' w4 ~4 T8 D) G4.8 Using Objects 769 S/ g8 [$ E U' a- ~% ^
4.9 Static Variables vs. Global Variables 76: h" R4 p4 K4 G. q
4.10 Class Routines 78# ]# C$ h T; @& j
4.11 Defining Routines Outside of the Class 798 n2 x: S; E0 _: B1 j% q
4.12 Scoping Rules 81
7 q% g- W" V9 n5 P9 O4.13 Using One Class Inside Another 851 W k, [+ U: q- O2 W
4.14 Understanding Dynamic Objects 87
; L& {2 k4 h$ b b! D* \4.15 Copying Objects 91
8 L1 P! X9 C% R& q) r5 s' Q' M* x4.16 Public vs. Private 95
4 t/ k" p% b. w/ m0 ^" M* H, q3 hContents ix* a3 j4 U) i% Y
4.17 Straying Off Course 96- |8 l* Y7 [4 Q. g. V
4.18 Building a Testbench 963 _8 F/ c3 t" v, t9 A1 b }# B: E
4.19 Conclusion 972 g: M( I& G) y9 k$ d9 b
5. CONNECTING THE TESTBENCH AND DESIGN 99
+ K0 _& ?8 u! d* k) m5.1 Introduction 99
/ G! T) X, K5 ?' m% I. U( \5.2 Separating the Testbench and Design 998 n$ ?0 i) o( E, _1 e
5.3 The Interface Construct 102
6 ]9 m' _% x/ Q- l3 ]( ]- R& t5.4 Stimulus Timing 108
4 F6 W- l. d3 V* ^" k# f5.5 Interface Driving and Sampling 1145 U! R! z' |3 n6 u& R+ T
5.6 Connecting It All Together 121' c7 W4 V; F1 b- p, [1 `
5.7 Top-Level Scope 121+ C' X* i; H8 ?6 S
5.8 Program – Module Interactions 123
3 I" P( F9 o4 T# P2 a4 U$ N5.9 SystemVerilog Assertions 124& G2 ~' B! b2 I ^7 D& E& @( R
5.10 The Four-Port ATM Router 126. R! D7 Q ?. k! W |* V
5.11 Conclusion 134
0 E' [" J1 V2 I9 b$ J0 E6. RANDOMIZATION 1352 h+ Z& n: C" ~" W0 [# J+ \1 B% [
6.1 Introduction 135
% d% [) h4 [3 i2 S, I, L$ S6.2 What to Randomize 136& B. X) K2 y3 G6 @! N8 T
6.3 Randomization in SystemVerilog 138
- _) ?+ d+ V8 N6.4 Constraint Details 141& K6 P( l7 \3 Q8 L+ P' V
6.5 Solution Probabilities 149
/ O% k7 l. R+ I: F5 h4 } u; f0 c9 M6.6 Controlling Multiple Constraint Blocks 154/ T% U* ^; O: a2 d" N/ |% } |
6.7 Valid Constraints 154
* a" k6 H$ b- |6.8 In-line Constraints 155
& `0 \: L- C: \2 } P6.9 The pre_randomize and post_randomize Functions 156
" F( }4 s* t" m8 K. a6.10 Constraints Tips and Techniques 158
* c. j( C% `" r( W. r6.11 Common Randomization Problems 164
: O& \$ J6 A" b6.12 Iterative and Array Constraints 1650 v; s7 U* k5 A. r8 |1 O
6.13 Atomic Stimulus Generation vs. Scenario Generation 172
8 `; U6 e# v6 \) v, n/ o7 {7 s+ b- J6.14 Random Control 175
- o2 A& p. g& F6.15 Random Generators 177 B2 s0 j3 _/ F! W/ i
6.16 Random Device Configuration 180
- e( K/ b G# B3 J; ]8 o3 s6.17 Conclusion 1820 [; Q, g. N; h% j; q. q
7. THREADS AND INTERPROCESS COMMUNICATION 183
" I% \* n1 g: C7.1 Introduction 183' i, ^8 M: _0 J% S
7.2 Working with Threads 184
) E- X. C8 E3 o$ C& H! L4 m' K3 n7.3 Interprocess Communication 1949 [* O# s {8 Y6 N" x
7.4 Events 195% S$ u- i: F- x5 c4 L/ s
7.5 Semaphores 199# T" l" d6 ^, r
7.6 Mailboxes 201
$ _3 A. c% ^ M0 a/ _5 M2 s7.7 Building a Testbench with Threads and IPC 210
4 p9 S8 U: q" \) r& \x SystemVerilog for Verification
* k }1 I$ E" Q7 p- r) j, N7.8 Conclusion 214
: B K; M; M) f1 `4 J8. ADVANCED OOP AND GUIDELINES 2151 d/ x9 I/ D8 Y/ m. j
8.1 Introduction 215
( \0 x% O3 N! F5 ]8.2 Introduction to Inheritance 216" f$ R0 q( }/ L' g/ _
8.3 Factory Patterns 221
8 Z" Y+ F# l3 q$ U D8 g$ k( n8.4 Type Casting and Virtual Methods 225
5 p( T v# S/ Z6 B7 ?! W7 `8.5 Composition, Inheritance, and Alternatives 228
+ n0 R' N- Z6 [: a0 `" W8.6 Copying an Object 233
% b8 g2 j: W0 b8 x! f! o8.7 Callbacks 236
$ \$ P X# J& x% K8.8 Conclusion 2405 K9 s( I: ^! v6 E }
9. FUNCTIONAL COVERAGE 241
4 N- t) H& x: p* f9.1 Introduction 2411 B8 j9 N( s) t$ b( M6 N
9.2 Coverage Types 243
+ H& @/ B2 E4 Q1 u8 f" l) s9.3 Functional Coverage Strategies 246" j: { ^9 V: T9 [4 n7 }
9.4 Simple Functional Coverage Example 248
0 x/ e; z7 l3 C, a9.5 Anatomy of a Cover Group 251
" U5 U, L& e' d; x5 M' g% o2 v* u9.6 Triggering a Cover Group 253: [+ c6 ^2 r e n5 O- o( p
9.7 Data Sampling 256" x9 t/ a a! y2 S! Q. C
9.8 Cross Coverage 265, r( n2 I' |, r4 \/ s" F* j
9.9 Coverage Options 272" j* z7 D7 C4 ^' U- a* p' S
9.10 Parameterized Cover Groups 274
# l; _- d5 W0 P! P9.11 Analyzing Coverage Data 2757 n$ J- x( l- C( A+ X5 J7 ?6 c) J! H
9.12 Measuring Coverage Statistics During Simulation 276
8 ` E; X' v7 \( C" N9.13 Conclusion 277
# v% M. ^& C8 d! b/ d10. ADVANCED INTERFACES 279
. @9 C$ }: d n( j: x9 V! |10.1 Introduction 279
% D/ s/ f- n; V; Q9 ?1 O# I4 T10.2 Virtual Interfaces with the ATM Router 279
, M2 G { C7 Z10.3 Connecting to Multiple Design Configurations 284
' I6 Y& t- _8 \# j" O* p: S10.4 Procedural Code in an Interface 290& Y: G( w: a. ?3 Y% x
10.5 Conclusion 294- X \' P3 f& Z# ^, h
References 295
( J( z: X% H* E0 pIndex 297
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