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通过Verilog HDL用数码管设计了一个40s的倒计时，想在10s之后加上一个蜂鸣器，无奈本人初学FPGA，苦试多次无果，故来此请教各位大神，能帮我在40s倒计时上面加上一个蜂鸣器吗，跪求了，谢谢！！！！module led_rxd(clk,rst_n,SOS_En_Sig,led,led_seg);
: M& g8 C& U% d# }% b: _input clk,rst_n;
" u% d+ F- {3 l' q& R. i. }output [7:0]led;+ Z ^ R+ H4 }: @
output [5:0]led_seg;" P! i6 N7 s7 e
output SOS_En_Sig;
; K/ `; Q% y6 w. nparameter seg_num0=8'hc0,
. z6 ?( P, ~5 p! t, u- Z seg_num1=8'hf9,
0 V0 s% U; I. [; s5 q6 f' x, w seg_num2=8'ha4,- U2 X# @5 f# A2 F0 l
seg_num3=8'hb0,/ L3 Y: G2 B4 C7 C/ o# z8 ]
seg_num4=8'h99,, K9 v" ]* Q7 T' T3 t$ [
seg_num5=8'h92,
; M# F! V; |* d seg_num6=8'h82,0 s3 C" W3 ^2 o, w9 r/ a& c
seg_num7=8'hf8,+ b2 J2 G/ I6 U. W7 m, S
seg_num8=8'h80,# ^# i, C$ G3 x r, q: Z
seg_num9=8'h90;1 p5 ~0 ]1 a7 I( `
parameter seg_en0=6'b111110,$ q5 y& C0 r- }: s2 I1 G- i+ `
seg_en1=6'b111101,
/ v3 L7 y5 S1 F% y& S& f seg_en2=6'b111011,$ L3 Z2 d8 s* O a
seg_en3=6'b110111,
. R' R1 m+ _ J2 S: S seg_en4=6'b101111,
3 x9 y1 o4 N& ^$ J- Q; \ seg_en5=6'b011111;
& @' ]! q& M5 x! creg [26:0]count;) ~# f' z. I/ i1 E+ y# B
reg [3:0] count1;; F. Q2 l) q3 ?' S$ ]% f' h0 ?
reg [3:0] count2;
o8 g O8 m* K* d3 Hreg [7:0] led_reg;
. e5 S1 e+ Z9 t, \; t" A; k5 \reg [5:0] led_seg_reg;
2 ?' Q' v( r& }) p. H2 i) z7 Ralways@(posedge clk or negedge rst_n)7 G: N$ e+ ^" U7 T
if(!rst_n) count<=27'd0; z. f6 ?0 b5 s1 b
else if(count==27'd49_999_999) count<=27'd0;
r& d4 \3 {; U k# q# gelse count<=count+1'b1;0 e# k: ^7 @: P# [" f
wire clk_div=(count==27'd49_999_999);
" o6 i9 l: h+ D& L, G! lalways@(posedge clk_div or negedge rst_n)9 a: v0 K6 X! S# T
if(!rst_n)/ e; i4 y, B! L& a
begin
% E6 {* }) _( z# Acount1<=4'd0;8 K& J" t- R. n. S# I7 J* m
count2<=4'd4;
$ M! f0 e8 R% V( B( { {9 ]1 w# Wend0 a9 t+ O" o* _2 x8 V% j
else if((count1==4'd0)&&(count2==4'd0))6 `( {" {3 X f% s# _
begin5 K% D2 z r8 M9 A& I5 f/ W2 Q6 g
count1<=4'd0;
! x7 c/ _" v' ?* y6 f0 Kcount2<=4'd4;
8 j3 a" a3 z) iend8 D& H' q+ X& J
else if(count1==4'd0)6 [; k3 J* p8 H2 I' U4 S( z
begin
1 t4 Y8 C8 Y2 pcount2<= count2-1'b1;
' z6 T# M) Y0 _6 H) n; f Ecount1<=4'd9;) P' g. N% X/ p: g
end1 S" e e; t, a5 x t) d# B! P
else count1<=count1-1'b1;
' I9 z5 b3 ?- C: F; [reg [26:0]count_1ms;//1 Y$ [5 a" G+ w& n- x( O
always@(posedge clk or negedge rst_n)) F6 Y/ _7 q: \, Q/ u4 v
if(!rst_n) count_1ms<=27'd0;
/ C6 Z T( o4 telse if(count_1ms==27'd49_999) count_1ms<=27'd0;6 v7 w& w/ R( m
else count_1ms<=count_1ms+1'b1;
+ n+ C w" d/ J0 U ~- L" Vwire clk_dis=(count_1ms==27'd49_999);//
' ?0 r7 ^7 h( w' { y& u- ?; d//
( @* H* B5 @" B) [2 o* G6 |( hreg [1:0]state;) q/ U0 Z3 {$ y( y: g6 a# \3 r: U
always@(posedge clk_dis or negedge rst_n)
, ]4 S( {5 b# E) t/ a) ~5 K- _if(!rst_n)1 J$ B. e1 p1 v& H
begin
; y; l$ o% j# s- @. |; t5 vled_reg<=8'hff;
! J; d+ D- E; tled_seg_reg<=6'b111111;# }5 j. B: j' m" O
state<=2'b00;
$ W, Q: m, B& x9 h" r7 nend7 s# V% d# o% V6 d. {& G/ @
else if(state==2'b00)
0 }( h& D- o. a1 R3 D: x: Qbegin; B5 C4 ^# r0 \4 E3 ^& {
state<=2'b01;
- X1 N& I" s$ T& tled_seg_reg<=6'b111101; ~9 g5 l8 N% L2 j' D- I
case(count2)) y4 Q" S- a. x, P% j
4'd0: led_reg<=seg_num0; " D' {, F( K0 U- m6 E! L$ ^! P
4'd1: led_reg<=seg_num1;
. I f' f9 B/ Q8 s4'd2:led_reg<=seg_num2;
4 D# @! `/ z1 w$ ^8 A4'd3: led_reg<=seg_num3;
, F* P, O3 a2 k& m; v' R X, n2 F4'd4: led_reg<=seg_num4; # B: I" U6 x8 ?
4'd5: led_reg<=seg_num5; 1 D( ^% j$ h5 I9 A: ^* e" j) o
4'd6: led_reg<=seg_num6;
) X. \6 g$ c* z! J+ k4'd7: led_reg<=seg_num7;
! a9 N. w- P& x0 N" s4'd8: led_reg<=seg_num8; # v- ]7 C( E6 D- i
4'd9: led_reg<=seg_num9;
9 U0 ~: r8 l& k, Udefault: led_reg<=seg_num0;
3 z+ N: L) E6 x/ F' k* ?7 Fendcase
5 W, d6 o1 c4 vend
* U Z# N+ H+ v1 _else if(state==2'b01)$ q$ Q5 \9 V; n' r" c, w. l
begin ! f& v- P- s: ` L6 c. {( m
state<=2'b00;6 }" ~' n9 A0 @5 m" y
led_seg_reg<=6'b111110;3 G7 B( }4 t9 \( p$ v$ E
case(count1)
5 {9 T" a' E5 p, w/ {' s, k" t" X4'd0:led_reg<=seg_num0;
/ U. r% W/ q" j6 P4'd1:led_reg<=seg_num1;0 X1 |: R# Z0 q- v) m/ v
4'd2:led_reg<=seg_num2;' ~* k# w3 @3 P& p% J, Y2 G
4'd3:led_reg<=seg_num3;+ L* H% u4 Z2 O8 {3 ^1 J; `
4'd4:led_reg<=seg_num4;
! i, }0 z3 t& l* |. P9 {; p4'd5:led_reg<=seg_num5;
' v; ]& E$ P% z. C) K# i+ Z& L- F4'd6:led_reg<=seg_num6;! r- q4 z m; v& M
4'd7:led_reg<=seg_num7;1 u1 Q# l! Y. q9 @
4'd8:led_reg<=seg_num8;/ {0 _3 }; _8 S2 R$ g5 w& O
4'd9:led_reg<=seg_num9;( T4 m9 [, P% h0 W; B
default:led_reg<=seg_num0;
0 t+ Q$ M' Q) r' @& w1 @7 Zendcase# Z- s3 s' q2 B4 X, a9 ~& Z
end
0 `9 a7 P8 |: d! x' Vreg isEn;
% X f7 j3 p* p( Ualways@(posedge clk or negedge rst_n)
L0 @* f# r$ e4 v) C& j% yif(!rst_n)
, K: k+ f% V7 X3 w/ J8 M' Abegin+ {, @) u" M; I \1 v% \( w( `
isEn<=1'b0;
7 I; r! f1 o! I1 a# z! v9 p1 mend7 R) o- {4 ]* V, v; B
else
- f) K& Q7 Q j4 _. Ybegin
. z- a+ g1 h4 f6 R5 _* T, S9 y# bisEn<=1'b1;
% X* ?* P. i" Q1 ^: m8 y- Lend
/ p0 N% q; d- |& Gassign led=led_reg;
3 o e5 p* o# K% Z' Jassign led_seg=led_seg_reg;
% T" X: s# `$ V K9 Z' ^assign SOS_En_Sig=isEn;1 n+ h, n& ^6 n, f7 H: Z
endmodule
& V' Y9 K5 P% z% x- ^+ x: X) C3 g/ }
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发表于 2016-4-13 18:01
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