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本帖最后由 紫菁 于 2017-9-14 14:38 编辑 1 x" L. A% ]) i
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DATE: 04-26-2013 HOTFIX VERSION: 008$ X* X$ K6 e& A$ g5 L
===================================================================================================================================
/ N, \% C& ^9 O2 w+ Q9 o+ b. nCCRID PRODUCT PRODUCTLEVEL2 TITLE
1 J$ X F3 ~: X( Q===================================================================================================================================
( A% `! w1 g& ~& O/ ^* b1 J( i876711 ALLEGRO_EDITOR GRAPHICS Mouse wheel will only zoom out using Win7 64 bit
8 Z/ H4 ^4 j' M( d2 W8 ~1080386 CONCEPT_HDL CORE Unable to highlight netclass on every schematic page using Global Navigation5 D$ j: ^1 f4 y- n
1082587 FSP FPGA_SUPPORT Support of Xilinx's Zync device% w& y* S- S. g U
1105286 FSP DE-HDL_SCHEMATIC FSP crashes while creating board in Schgen if it does not find any available license.
9 d" O7 h1 F5 ^# E: p$ `2 l1105461 ALLEGRO_EDITOR DRAFTING Dimension Enviroment deletes Diameter symbol whenever we add anything to Text section
& @) I& n) B* V" L7 f1105504 PCB_LIBRARIAN CORE PDV on Linux Move pins by arrows does not stop when release arrow key but keeps on running
1 v& w% [- ?1 a4 h/ o, A1110126 ALLEGRO_EDITOR GRAPHICS Display Hole displays strange color.
A+ }. Y( G- X3 {- `/ y# _1113518 CIS DESIGN_VARIANT Incorrect Variant information in Variant View Mode for multi-section parts with occurrence
$ c3 G) b/ [+ B8 `" O% c G m) v1117580 SCM OTHER DSMAIN-335: Dia file(s) error has occurred.
) B5 D v, W, h j$ Z1117845 FSP DE-HDL_SCHEMATIC Schematic Generation fails without a reason
. [9 Q5 j# R' y* o0 E' {1119864 FSP TERMINATIONS Auto-increment the pin number while mapping terminations.3 ^' Q+ |% G0 A% M y" a8 x: W
1120250 ALLEGRO_EDITOR MANUFACT Why is the parameter File altered?
6 N3 t$ |+ `. {) g1120414 ADW LRM TDO Cache design issue
) x* m$ J3 }- i' n. z* E1121044 SIP_LAYOUT SKILL axlDBAssignNet returns t even when no net name is assigned to via5 M! ^3 x6 {6 d, w Z
1121148 ALLEGRO_EDITOR PLACEMENT Ratsnests turns off when moving symbols with Net Groups
0 L2 c, K+ X) S9 A! a1122440 ALLEGRO_EDITOR DATABASE Cannot unlock database using the password used to lock it: m6 t* G+ B6 D
1122449 ALLEGRO_EDITOR DRC_CONSTR Uncoupled length DRC for diff pair shows different actual length value between show element and CM.
+ Z/ _! B. G* a" S1122990 ALLEGRO_EDITOR INTERACTIV RF PCB Symbol which is part of Reuse Module cannot be replaced
% n7 ^0 i# e6 S3 t1123083 ALLEGRO_EDITOR PLACEMENT Saving after mirroring a Place replicate mdd create a .SAV board file.0 Y3 Q$ P9 k) _7 u1 j% R" z* [
1123257 SIG_INTEGRITY SIMULATION some of the data signals at the receiver are not simulatable
; } B3 f% O6 R# z. w" { ]1123764 CONSTRAINT_MGR OTHER Allegro crash while importing DCF file( P! o' ]; ]) \4 E
1123816 CAPTURE PART_EDITOR Movement of pin in part editor, @. [: ]. {8 _+ L1 H( K, f
1124183 ALLEGRO_EDITOR EXTRACT Output from EXTRACTA gets corrupted with refdes 50
0 H5 T" G$ B4 T1 \: cDATE: 04-13-2013 HOTFIX VERSION: 007
4 y4 N. i: X- u" G+ J* V8 ^===================================================================================================================================: ]+ z# ~0 t" k) g
CCRID PRODUCT PRODUCTLEVEL2 TITLE# s k- g6 ~. |. v! G: y
===================================================================================================================================
' ]( p9 E" d% ? r: |+ [/ m! W1107397 SIP_LAYOUT PLACEMENT Place Manual-H rotates die
% K; O) R$ J+ r% T! r1111184 ALLEGRO_EDITOR PLACEMENT NO_SWAP_PIN property does not work in 16.63 h( ]0 V1 x( W; S0 W+ Q9 V1 X
1112295 APD DXF_IF Padstacksї offset Y cannot be caught by DXF.# x) ^# z0 ^" v$ V. N# F1 \) w7 H5 M
1113284 ALLEGRO_EDITOR INTERFACE_DESIGN Rats disappear after moving components) |$ j+ ^5 E2 e* U
1113317 CONCEPT_HDL SKILL skill code to traverse design not working properly
* R, e5 l% g" `3 g% O+ }/ A1115491 ALLEGRO_EDITOR SKILL telskill freezes command window
. x8 w+ T5 b& I: b" g0 ?$ j) p+ v1115625 ALLEGRO_EDITOR SKILL Design extents corrupted when axlTrigger is used.
4 p* O% V6 Q& d3 X- I1115708 ALLEGRO_EDITOR INTERFACES Export DXF is outputting corrupt data on one layer.
8 B7 ~" y) X! z+ D2 }1115850 ALLEGRO_EDITOR GRAPHICS Text edit makes infinite cursor disappear( p, n" d1 w- ^) e9 `) m
1116530 ALLEGRO_EDITOR MANUFACT Import artwork show missing padstacks
5 d' o9 `& G- ~0 I, h% y1117498 ALLEGRO_EDITOR DATABASE Why does dbstat flag LOCKED?
$ \0 i0 c5 M% \8 [$ n; z1118407 SIP_LAYOUT DIE_EDITOR net connectivity is getting lost when running die abstract refresh+ T+ n* K! P* H4 U" {, @4 l
1118413 SIP_LAYOUT DIE_EDITOR pin number is getting changed when running die abstract refresh
, ~3 V+ G$ S6 b3 s" w" n3 M1118526 CONCEPT_HDL CONSTRAINT_MGR Upreved design now has Constraint packaging errors
2 W; M% P n: J; n* H- [1118830 ALLEGRO_EDITOR SHAPE Performance issue when moving/refreshing shapes in 16.6- i( w! M' z- i
1119784 ALLEGRO_EDITOR INTERACTIV ipickx command gives drawing extent error inconsistently) k+ {/ |2 t2 X( I
1120469 SIP_LAYOUT DIE_ABSTRACT_IF use different padstack for different, but look-alike bumps
' _" U: s( v( b7 H2 j0 ?7 g/ `1120669 CONCEPT_HDL CORE DEHDL crash on multiple replace of hier blocks$ O3 s A2 f7 U1 M+ l
1120810 ALLEGRO_EDITOR EDIT_ETCH Cannot slide cline segment.
9 \" i. L9 n. i3 S1 @DATE: 03-29-2013 HOTFIX VERSION: 0060 f: `7 o& O6 ?) {% z
===================================================================================================================================
" W$ B& t1 E4 m! S+ B" T- W- wCCRID PRODUCT PRODUCTLEVEL2 TITLE
- P" B0 x8 k% D===================================================================================================================================
' c- ]% Q/ \" ^2 \4 T) V+ _) b' R110139 FIRST_ENCOUNTE GUI Error in Save OA Design form
1 d: Y3 H9 O- Z; L; e+ M1 S. V; K625821 CONCEPT_HDL CORE publishpdf from command line doen not work if temp directory does not exist.
& X! m% D$ J% w$ |: l! K6 U4 k( G642837 PSPICE SIMULATOR Option to disable Bias Points when Primary Analysis in Active Simulation Profile is DC Sweep
4 N- M1 c+ t6 ]) V# u650578 ALLEGRO_EDITOR SHAPE Allegro should do void only selected Shape without "Update Shape".
3 |! b1 c, A f0 Y* T& Z653835 ALLEGRO_EDITOR MANUFACT Double character drill code overlaps with "cross" in NC drill legend e) \- V9 U; i5 L
687170 SIP_LAYOUT DRC_CONSTRAINTS Shape to Route Keepout spacing DRC display incorrect6 e: L2 a7 h/ G9 J; ^- q
787041 FSP DE-HDL_SCHEMATIC FSP Refdes inconsistency when gen schematics
# p- f; x- X; C8 H8 }825813 CONCEPT_HDL CORE HDL crashes when copying a property from one H block to other5 @; R, C' `/ G" M1 l! t/ p9 I
834211 ALLEGRO_EDITOR SHAPE Constant tweaking of shape oversize values is time consuming
! D. n% _7 M: e: U/ Y- v835944 ALLEGRO_EDITOR OTHER Customer want to change for Jumper symbol by other Alt symbol.
2 j4 t3 a( X3 n; o( B' z868981 SCM SETUP SCM responds slow when trying to browse signal integrity6 `3 |0 ?3 b& Y$ f$ Q e
871899 CONCEPT_HDL CORE 'Multiple:' column of Grid window in DE-HDL option is too wide
( ]( G8 h" I* S' J, H2 v b5 R* a873917 CONCEPT_HDL CORE Markers dialog is not refreshed
9 Y& n" K( c7 g. v2 n9 Q0 R. A& P i887887 CONCEPT_HDL CORE Option to find unconnected Pins/Nets with DEHDL L License
% d: M% a- ]( m* M9 @888290 APD DIE_GENERATOR Die Generation Improvement
3 E* w; [7 _5 m892857 CONCEPT_HDL CORE packager treats R? as a unique reference designator
' O$ C: V& F& w902908 PSPICE SIMULATOR Support of CSHUNT Option in Pspice
9 c; i6 A9 z' G _! H6 Q908254 ALLEGRO_EDITOR INTERACTIV Enhancement request for DRC marker to have a link to CM' [% E6 W7 }. x# U- h
922422 CAPTURE NETLIST_ALLEGRO Netlist errors when using mix of convert and normal symbols
y4 o# ^) |4 ?, h' t; F' v923361 ALLEGRO_EDITOR INTERACTIV Stop writting PATH variables in env file if no modifications are done using User Preferences# F& S- A4 u$ l5 v. f: p+ b
935155 CAPTURE DRC No any warning messages listed in the On line DRC window even executed "Check & Save" to on line DRC Y' ]9 v3 O! m( p& `7 O$ Z
945393 FSP OTHER group contigous pin support enhancement4 @$ a0 _! N3 k: U+ W) W. W2 S2 R
969342 ALLEGRO_EDITOR DATABASE Enhanced password security for Allegro database2 z# H4 _5 D3 P7 b- A
1005078 CAPTURE ANNOTATE Copy paste operation does not fill the missing refdes
9 y/ e3 z0 v3 `, F1005812 F2B BOM bomhdl fails on bigger SCM Projects8 c& e* h l& M
1010988 CAPTURE OPTIONS ENH: ADD ISO 8601 Date Time format to Capture
) l, u1 Y' |" Q! I& S' ^) {1011325 ALLEGRO_EDITOR PLACEMENT Placement replication creates modules with duplicate names& J6 C; T. e( Y
1016640 ALLEGRO_EDITOR PLACEMENT Error/Warning Message for not finding or unmatched mechanical symbol or fiducials or which are not on a net
+ j9 d+ a0 |) u2 ]2 o1018756 CONCEPT_HDL CONSTRAINT_MGR Match Groups with Pin Pairs are not getting imported into the schematic CM during Import Physical
" H2 m4 C$ n' ?) Y) h% x: v1032387 FSP OTHER Pointer to set Mapping file for project based library.
1 ?: ]+ e- d2 Z4 Q# m1032609 FSP IMPORT_CONSTRAIN Import qsf into FSP fails with ї LL PLL_3 does not exist in device instanceї
! s `) C8 y2 O8 n( D2 s% ~1040678 ALLEGRO_EDITOR MANUFACT Text spacing is inconsistant for top and bottom SM layer in xsection chart
3 K3 z! G+ ^2 m! k9 w* U1042025 APD WIREBOND Order placement of power rings for power/ground rings generation with using Perform Auto Bonding
9 V% R9 c6 k3 U0 [" r; g1045500 CONCEPT_HDL CORE Why Search results does not display the correct Physical Pages., Q5 f$ g) v* Q$ _
1047259 CIS EXPLORER Sorting in CIS Explorer is not Numeric even for columns which are of Numeric data type4 H; m7 m) n5 N' h$ D' b
1047756 CAPTURE NETLISTS Not adding user defined properties in netlist generated by orDump.dll/ _2 E+ m* j7 j# L
1052455 RF_PCB DISCRETE_LIBX_2A RFPCB IFF Export to fix port direction for ADS for footprint having the same pin rotation9 O8 k0 @$ r; E* |1 x1 U
1054314 CONCEPT_HDL CORE Zoom of custom text is different from other schematic objects$ P/ |( u) Q4 `6 w7 k! J
1061529 CONCEPT_HDL CORE Space can be included in LOCATION value and cannot be checked by checkplus- k2 |7 n4 i5 b4 J) J8 ?. }
1064035 CONCEPT_HDL COMP_BROWSER Component Browser crashes on part number search using a library containing >23K parts1 g3 H. R+ C- I' }# T
1064604 ALLEGRO_EDITOR MANUFACT Enh - Include ability to add slot notes to designs
) s' \2 ?% B; W$ k& }& C' W( n4 @3 t* j1065636 CONCEPT_HDL OTHER Text not visible in published pdf
' y. |5 L7 e1 ]2 v1 T" D2 Y1065843 CIS PART_MANAGER time stamp on library from different time zones triggers part manager lib out of date warnings& Q! f0 d+ Z4 s3 h8 I# h
1066701 ALLEGRO_EDITOR OTHER Missing padstack warnings not in Symbol refresh log summary$ k' T, Y) {0 k
1067283 SCM PACKAGER ALLOW_CONN_SWAP does not work for lower level schematic parts
+ @* J. O7 g, p% Y5 V+ f1067400 CONCEPT_HDL CORE ERROR(SPCOCD-171): Port exists in symbol but not in the schematic
' G, g1 d0 F+ [ G/ s! D/ C1 Z1068878 CONCEPT_HDL CORE Rotating symbol causes the pin name to be upside down
6 `4 i! P8 U, ~, e1069896 ALLEGRO_EDITOR EDIT_ETCH Cline changes to arc when routing even when Line lock is set to Line 45 Q9 v3 u0 y8 x7 E7 m! i# b) n/ E: w
1070465 CONCEPT_HDL CORE Why does ConceptHDL crash on renaming a Port Signal
* M1 S- z# ?5 R. T8 ?1071037 PSPICE SIMULATOR Provide option to disable Index Files Time Stamp Check+ a* y! K, c$ Y% v
1072311 CONCEPT_HDL OTHER Schematics are incorrect after importing design.5 I. Y, @3 _: B# t1 F6 F% Z
1072691 CONCEPT_HDL CORE Customer has the crash from Run Script of DE-HDL 16.51 again(#3)# G+ f! @0 j1 V* t( o2 e
1072859 SIP_LAYOUT DIE_EDITOR padstack selection window crash from Die Editing: Component editing of Co-Design Die. z7 v- ` q/ T5 z
1073354 CONCEPT_HDL CORE Bubble defined on symbol pin is not visible on the schematic
! O0 a+ i% e7 j7 h; f7 A H6 U3 W1073837 ALLEGRO_EDITOR GRAPHICS Some objects disappear on ZoomIn ZoomOut
# G3 j4 L2 q) w' v. l7 {$ }. ~1074243 ALLEGRO_EDITOR GRAPHICS Allegro WorldView window does not always refresh after dehighlight of objects
3 y! ^" w2 y5 A# e1 U& ^1074606 ALLEGRO_EDITOR INTERACTIV Enh - Cosmetic change in Filter Option UI of Replace padstack to indicate multiple pin entry format0 E$ n3 r \" M$ O4 F. I" \6 U
1074794 ALLEGRO_EDITOR REPORTS add commonly reguested via reports to Allegro and ICP reports. Via per net, via per layer per net
' V9 a/ L# v; s1075587 CONCEPT_HDL PAGE_MGMT Unable to insert page in schematic/ @; K. g1 s% Y5 I" _ m: n
1076117 PSPICE PROBE Copy & Paste text/label in probe window changes font size and later gets invisible1 Z; e+ M; M" R0 r7 Y% q% o- Q
1076145 SIP_LAYOUT DIE_ABSTRACT_IF Issue message in Add Codesign and Refresh Die Abstract if Pin Numbers from Die Abstract exceed 31 chars.$ ]+ l- T: X" f& ]. g/ f7 `: b
1076566 ALLEGRO_EDITOR EDIT_ETCH Sliding diff pair cline that has a min/max prop rule displays the HUD meter inconsistently.
4 [& V. ~& m- ^6 p# @3 I/ U1076604 ALLEGRO_EDITOR SHAPE Sliding via in pad corrupts surrounding shape and generates false DRC Errors
* U4 j. {, W, S" q2 W1076820 SPECCTRA FANOUT Fanout fails to stack vias in bga pads.
1 ?8 K' w, Q0 E8 U: a0 D" R1076868 ALLEGRO_EDITOR PARTITION Symbols become 'read only' inside a design partition
3 I1 }. z u0 F' `) U7 A/ w1076879 GRE IFP_INTERACTIVE Plan Column should not be present in Visibility tab for Symbol Editor1 |3 w: V) W2 [! Y/ F" e" l
1076898 CONCEPT_HDL CORE User can not increase logic grid size value continuously using Up button on Design Entry HDL Options
) P, m8 ~5 @; k4 m9 Q. n5 X6 @' [; M1077026 CIS LINK_DATABASE_PA fonts changes while linking db part in 16.5
( H% {! E8 g6 D! Z4 C1077187 ALLEGRO_EDITOR DATABASE DBDoctor appears to fix database but nothing is listed in the log file.
2 h' g1 g% o2 _5 o& Q1077527 CONCEPT_HDL CORE ConceptHDL net with name U cannot be found using Global navigate# `& s: z, U! d+ E0 d
1077621 CONCEPT_HDL CORE DEHDL crashes when saving page 3
{; w! Z. t# _3 @0 v1078270 SCM UI Physical net is not unique or not valid
( G( b3 ?: F7 D7 S; n* w1079616 CONSTRAINT_MGR CONCEPT_HDL Packager error in 16.5 which is resolved when system is re-booted
! V+ r3 S! G! y, N# r' y$ |1079821 CONCEPT_HDL CORE Project Setup does not respect $TEMP variable for temp_dir and creates a directory in project calle
6 f9 w, T/ r9 G& K* C% m, T( c1080142 CIS CONFIGURATION peated entries in Allowed Part Ref Prefs) X0 y$ W0 C$ a, ~
1080207 ALLEGRO_EDITOR INTERACTIV Separate the 2 types of SOV violations."Segments over voids & Segments with missing plane coverage"0 S# l3 f5 Y; a+ W) l
1080261 PSPICE SIMULATOR Encryption support for lines longer than 125 characters
+ q6 t' A: Y o" X$ P. J1080336 CONCEPT_HDL CORE Backannotation error message ehnancement, z8 L2 H3 w$ S+ o$ W( ^" \$ q. h4 ~
1081001 ALLEGRO_EDITOR PLACEMENT Package boundary is not visible while manually placing a component when using OrCAD license" f: u3 j9 l9 y6 }6 B0 k
1081237 ALLEGRO_EDITOR PLACEMENT Place replicate > apply does not apply component pin properties stored in .mdd
& a' s: d) q: N) t* K1081284 MODEL_INTEGRIT TRANSLATION Space in the file path will create a bogus error
" W5 P# h8 W3 t) k1081346 ALLEGRO_EDITOR INTERACTIV With Place manual, rotation of the symbol is not updated.
% c/ b) L! w) k( u6 ^2 N' T1081760 FSP CONFIG_SETTINGS Content of їFPGA Input/Output Onchip terminationї columns resets after update csv command2 q" o2 ]/ f8 K" }1 m
1082220 FLOWS OTHER Error SPCOCV-353
! k0 S8 X/ @/ [$ W* h1 o! r1 l1082492 ALLEGRO_EDITOR PLACEMENT Place replicate create does not highlight symbols.2 _6 [7 j A+ ~! y
1082676 ALLEGRO_EDITOR EDIT_ETCH HUD meter doesnot display while sliding / add command
& b D* t9 ]4 P1082737 CAPTURE GENERAL The їArea selectї icon shows wrong icon in Capture canvas.
+ ^ Q( E. U' @ J, R1082739 CAPTURE OTHER The product choices dialogue box shows incorrect name- ^) R' V s+ G9 _ m$ D
1082785 CONCEPT_HDL CORE DE HDL should clean the design with non sync properties in some automated way; w! t( S6 u3 W$ }% @3 c
1083761 CONCEPT_HDL OTHER AGND text missing from PDF Publisher
2 U% O. t8 I; j6 C- w5 H1083964 CONCEPT_HDL OTHER Do not display Value and other attributes on variant parts which are DNI
1 V$ f- V s, V1084023 PSPICE MODELEDITOR Model Editor is slow/unresponsive while opening a Model by double-clicking on .lib file; G$ n0 U" ]0 B( D) m* A; j E1 |
1084178 ALLEGRO_EDITOR SHAPE Spike create on dynamic void.
& s Y. h; p% y/ D1084637 ALLEGRO_EDITOR INTERACTIV Enhancement: Pick dialog should automatically be set to enter coordinates! r4 S$ o/ u8 l. L( j
1085010 CONCEPT_HDL CREFER Crefer crashes if the property value in the dcf file has more than 255 characters O7 ^ i; U7 l( l
1085347 CAPTURE SCHEMATIC_EDITOR Replace cache results is loss of net graphic changes.' j( T' V3 {) a- t: K
1085522 ALLEGRO_EDITOR INTERACTIV Allegro add angle to Display->Measure results' b% r& ?; d6 K+ l
1085791 CONCEPT_HDL CORE Publish PDF can not output Constraint Manager properties into PDF file.; C- `, l# d8 l( _. x
1085891 ALLEGRO_EDITOR INTERACTIV about DRC update
$ a$ b1 ]5 D) |/ P1085990 CAPTURE DRC B1: "ERROR(ORCAP-2207) Check Bus Width Mismatch" should be INFO* M6 @) p) ^" Q0 N9 D. c( L- I' l
1086514 CONCEPT_HDL COMP_BROWSER Component Browser placement restrictions not working" O, d/ p7 g. H: U3 p, k/ F6 @ k
1086576 CONCEPT_HDL CHECKPLUS CheckPlus hangs when running Graphic rules.
, |2 X7 ^' k* J% L7 S& z# }# H. U* _2 h1086671 PSPICE SIMULATOR SPB16.6 pspice crashes with attached design5 M! M# B3 P3 H& T( n- d
1086749 ALLEGRO_EDITOR MENTOR mbs2brd: DEFAULT_NET_TYPE rule is not translated3 m: e+ t- E, q. }6 |* |& l0 N
1086886 CAPTURE PROPERTY_EDITOR "Is No Connect" check box in property editor doesn't work for power pins
3 N% R- A5 A( [. @$ n! a/ ]( O" o `: {1086902 CONCEPT_HDL INFRA Problems occurred while loading design connectivity
6 ]" U: U7 A" f( z; J4 i% e3 _1086937 PSPICE ENVIRONMENT PSpice Color map getting doubled leading to crash after colors are modified number of times.
* T0 s* p4 e( z! r) f: C3 z% m9 ~% o# g1087221 CONCEPT_HDL OTHER Part manager could not update any parts.
" u6 I4 n5 J' L1087223 CAPTURE CROSSREF Cross Probing issue when login into system with user name containing white space( O1 `7 Q; i: c
1087295 SIP_LAYOUT EXPORT_DATA Enable "ackage Overlay File for IC" for concurrent co-design dies too
: H5 ?$ g: n- `9 X( f1087658 CAPTURE PRINT/PLOT/OUTPU Lower level design pages are getting print twice" V7 Q6 M/ {4 q* f2 I
1088231 F2B PACKAGERXL Design fails to package in 16.5$ Q! E* F* w3 d' a# B( L9 i
1088252 CONCEPT_HDL CORE Menu commands grayed out after Save (with 16.5-s035) when launched from ASA.6 b* J' a; I [& I+ [2 D' Z9 Y
1088606 ALLEGRO_EDITOR INTERACTIV Pin Number field do not support Pin Range for Symbol Editor( n# c; k0 s; X7 T- J( E& u
1088983 CONSTRAINT_MGR CONCEPT_HDL Units resolution changed in 16.6 Constraint Manager
" m8 S( Q# e$ x7 R3 `( h' Z0 s1089017 ALLEGRO_EDITOR SHAPE What is the cause of the shape not filling?0 k2 R( }" w k" B9 T, w, v" X+ i
1089259 SCM IMPORTS Cannot import block into ASA design) _4 J0 R* k' k! ?( ]1 ?
1089356 SIP_LAYOUT DIE_EDITOR Distributed co-design : launching die editor taking more than an hour to bring up edit form
c* ?6 i3 `; Z8 |' I( C9 [1089362 PSPICE STABILITY Pspice crash on pspice > view simulation result on attached project
2 i) E: K' l3 U1 r% ]% n1089368 SCM OTHER Can't do Save - cp: cannot stat ... No such file or directory* W) Y7 a! Z4 q1 J) [3 P" ~
1089605 CONCEPT_HDL CONSTRAINT_MGR Power net missing from the CM opened from DEHDL Schematic editor.
4 n6 U- h% z" |( B' r1090068 ALLEGRO_EDITOR SHAPE shape priority issue in SPB1659 Z/ R6 J# w$ i& v& A
1090125 ALLEGRO_EDITOR DATABASE Q- The rename resequence log file is not giving correct message.* J) N8 F+ Y+ ]
1090181 GRE CORE AiDT fails for the nets with errors SPGRE-21 & SPGRE-223 w- m% ]/ _, K. T; U( q! W
1090930 CONSTRAINT_MGR CONCEPT_HDL DEHDL-CM does not retain customized worksheet.
3 n) b5 q X) c5 s- ^1091335 CONCEPT_HDL OTHER Color change cannot remain in some situation.$ W' b7 s- |; u- R; ^
1091347 CAPTURE TCL_INTERFACE The Project New link on Start Page doesn't work when Journaling is enabled
2 P5 k# S5 F$ M1 t* g# k% ?1091359 CAPTURE GENERAL Toolbar Customization missing description
$ F1 l% d" G1 p5 r) w1091662 CONCEPT_HDL CORE Incorrect behavior with the SHOW_PNN_SIGNAME directive
" q$ I( N8 {4 w& I1091714 CAPTURE PART_EDITOR More than one icons gets selected in part editor at the same time
, k; o# h% x$ D% ]4 s* w. t1092411 CONSTRAINT_MGR INTERACTIV In v16.6 CM multiple net name selection under net column is not working as in v16.5
- K0 X% y, T: M1092426 CONCEPT_HDL CORE Getting ERROR(SPCOCN-1993) while saving a Hierarchical Design, q- p1 \$ ?, C' i/ o
1092874 CONCEPT_HDL CORE DEHDL wire short during move not detected with check enabled/ ?. \- I" C, N0 ^0 U
1092882 ALLEGRO_EDITOR EDIT_ETCH AICC should be removed from orcad PCB Designers design parameters1 Z& f8 H% Z0 w1 M R5 L5 X- Q: r
1092918 CAPTURE GENERATE_PART Generate part functionality gives no/misleading information in sesison log in case of error2 C# E7 U; ^- P
1092933 CONCEPT_HDL OTHER PDF Publisher saves the pdf generated in the previous project folder9 r N5 y3 p+ v" l7 p6 p1 @
1093327 CONCEPT_HDL OTHER Getting error SPCODD ї 369 Unable to load physical part in variant editor
1 N) z* H1 D! G9 j1093391 CONSTRAINT_MGR OTHER Setup > Constraints > (domain), doesn't open correct worksheet with OrCAD PCB Editor Professional license.
: o" \3 S- O8 s1 x1093886 SPECCTRA HIGHSPEED Pin delay does not work in PCB Router when specified in time/ Q) [0 D1 v' H) U* F+ a r v. {- u
1094223 CAPTURE PROPERTY_EDITOR CTRL+S does not work in Property Editor but RMB > Save.
8 E1 y; E# @; V2 O' Y4 t1094513 CONCEPT_HDL CORE How to display $PNN for which SIG_NAME is not visible?
) Z" u. I7 m6 |/ \! f. I1094611 CAPTURE PROPERTY_EDITOR E1: 'Tools->Update Properties' should list parts which are present in .UPD, but not schematic
A- J! z+ E' T0 m' s1094618 CONCEPT_HDL INFRA Unable to uprev the design in 16.5
9 Z: I1 u0 l* E4 H& A1094867 CONCEPT_HDL CORE Page Up / Down Keys are hard-coded assigned to Next /Previous Sheet# z+ P G( X" A2 D3 ^) v7 d( L
1095449 SIP_LAYOUT LOGIC Allow netlist-in wizard to work on a co-design die, ~% k; A0 ]( L3 m* Z; p% a
1095701 CONCEPT_HDL CORE Replace part in replicated block only preserves the Refdes in 1st instance of the replicated block0 B2 `0 X/ `+ [$ |; W0 A% T0 n
1095705 CONCEPT_HDL CREFER Cref_to_list not updated on repl icated blocks in 16.5 release worked fine in 16.30 T6 m( \: e( Y! f- d4 L9 W
1095861 F2B BOM Using Upper-case Input produces incorrect BOM results" _4 C# O1 @( x/ w9 k" M$ R6 o
1096318 ALLEGRO_EDITOR INTERFACES IDF import not removing MCAD tagged objects during import4 r k+ V3 m$ I$ B# V
1097241 CONCEPT_HDL CORE Concepthdl - zoom in to first object in Find result automatically
. q( p* L0 f0 o5 E1097468 ALLEGRO_EDITOR INTERACTIV Need ability to hilight and assign color to vias
+ \% q% G4 F$ Y8 H$ t" s6 ~3 k" Z A1097675 CAPTURE ANNOTATE Enhancement:Option to have Incremental reference Update to be checked at all times when we click on Tool>Annotate; b$ e+ z8 S: S% {
1099151 SIG_INTEGRITY SIMULATION All Neighbor crosstalk numbers reported when there are no aggressors( {& n3 U4 `0 m. k# ?" u' G( Q
1099175 CONCEPT_HDL CORE CPM directive that enables the Command Console Window in DE-HDL# a7 h6 m4 I6 u( O0 s
1099838 CAPTURE TCL_INTERFACE TCL library correction utility is not working correctly.
7 n7 x2 q y% l: w3 k" h2 V- i4 p1099903 ALLEGRO_EDITOR PLACEMENT Mirror and rotating component places component mirror side
2 K' b4 \: j2 o0 r% q1099941 ALLEGRO_EDITOR PLACEMENT Problem in rotating bottom components when using Place Manual or place manual -h command, X0 ~, T4 o/ {9 |% W" f
1099998 CONCEPT_HDL CHECKPLUS CheckPlus marker file not locating signal when signal name includes the # character.6 h1 C' A+ z7 R. @; d
1100018 CONCEPT_HDL COPY_PROJECT CopyProject gives errors about locked directives
1 ?, r$ `+ S: N1100449 ALLEGRO_EDITOR ARTWORK Pad with Net_short property and shorted to shape supressed wrongly with Pad Supression in Artwork" c C& g/ G2 d7 n
1100758 CAPTURE LIBRARY Import properties does not update pin numbers of multi section parts
# P a- p& I, j5 c4 }# O1101009 CONCEPT_HDL CORE Cursor stays as arrow after performing File > Save Hierarchy
9 W9 }. r# F5 v1101497 ALLEGRO_EDITOR UI_FORMS Allegro PCB Editor crashes using attached script when working with RF PCB Clearances.
0 C8 v% S9 j. v: w1101813 SIP_LAYOUT DIE_ABSTRACT_IF Support die abstract properties. h: }+ |! J2 H, @2 W I
1102531 ALLEGRO_EDITOR GRAPHICS Allegro graphics distortion infinite cursor 16.6- w; c8 W# I! }4 f( R
1102623 ALLEGRO_EDITOR SHAPE Strange void around the pad) M/ B* V W3 q2 | b k5 r6 v
1103246 FSP FPGA_SUPPORT New FPGA request - Arria V - 5AGXMA1D6F31 - IN2P3' e6 v% p7 O" [* X$ G
1103631 MODEL_INTEGRIT OTHER Model Integrity license when using orcad
) O9 \. e/ i' Q* V5 N+ b# n1103703 F2B DESIGNSYNC Toolcrash with Design Differences
* w. D! J! j9 m9 g: V1103712 CONCEPT_HDL COPY_PROJECT Copy Project crashes on customer design attempting to update symbol view: J8 M/ H3 s% F* m, v+ I3 B. Z
1104068 CAPTURE DRC "Check single node connection" DRC gets reset in 16.6
5 X4 b9 L3 k% t) V* L" h1104121 PSPICE AA_OPT їarameter Selectionї window not showing all the components : on WinXP1 C/ B" g! {7 G9 G% m- E
1104575 CONCEPT_HDL CORE Allign does not allign offgrid symbols correctly. y+ x+ s7 ]" U' P& E- `
1104727 CONSTRAINT_MGR SCM Net Group created in sip does not transfer to SCM3 S" C; z: P( ~& p) m4 i
1105128 CONSTRAINT_MGR DATABASE Import dcf does not clear out user defined schedule., d+ t' B! P0 C& f" ?5 s# x! G
1105195 SIP_LAYOUT WIREBOND Request that Tack points default to a "fixed" position after Generate Bond Wires.
. |6 A' m$ n% y1105249 ALLEGRO_EDITOR OTHER PDF out--- component user defined prop doesn't list the prop selection form' d+ P1 }0 Q. I b7 V8 d# d
1105443 PSPICE AA_OPT Parameter selection window in optimizer does not list param part
' h( U$ \) R" U9 E0 T$ g9 d% ?8 W1105818 ALLEGRO_EDITOR INTERACTIV Menu-items seperators are clickable and menu goes away when clicked7 ]0 c4 p! g4 {" }6 O+ w0 f, z( p
1105822 ALLEGRO_EDITOR SCHEM_FTB Netrev failing with compact pin syntax
% H, y5 E' b7 R, s& o$ w& `$ i7 K1105993 SIP_LAYOUT LOGIC Import netlist no longer works with co-design die in SiP 16.6) m2 p: F g+ M, C& [( [# A
1106332 SIP_LAYOUT OTHER sprintf for axlSpreadsheetDefineCell writes characters in upper case only
/ c4 \. f, g. g# L1106786 CAPTURE SCHEMATICS Bug: Pointer snap to grid
# [1 n q% r% |& h. j1107132 FSP OTHER Altera ArriaV (5AGXMA5GF31C4) support.
: K1 W& T3 z2 ^! t6 p9 J- K" ~- l, o1107151 ALLEGRO_EDITOR ARTWORK Shape filling removed when changing artwork format to RS274X in Global Dynamic Param1 Z; }7 v" V3 I. p S
1107237 SIP_LAYOUT WIZARDS Updating a Die using the Die Text In Wizard will error out and not finish# W* | |- N- G$ B$ o
1107371 ADW COMPONENT_BROWSE ADW preset Warning filter is spelt incorrectly. (Wraning)./ @. H, A0 l1 S4 }7 X& f
1107599 CAPTURE STABILITY Capture 16.6 crash when trying to invoke7 P& Z& ~- e% F' {
1108118 ALLEGRO_EDITOR OTHER PDF Publisher pad rotation messed up with flashed pad.4 t! }' `" A( Y
1108574 ADW COMPONENT_BROWSE LifecycleStatus functionality does not work when in Metadata mode. Work correctly in PPT Mode
( P1 p7 B2 F" u) i# S/ e: O1109095 SIP_LAYOUT WIREBOND Bondfinger move in hug mode create drcs
9 J( z" l0 C; i/ i, N( C1109113 ALLEGRO_EDITOR DATABASE Allegro Netrev crash with SPB 16.6
8 f: N2 Y9 ?5 E# D6 _0 D2 O1109622 SIP_LAYOUT DATABASE In a wirebond design, the ratsnests with 'Closest Endpoint' should not point to the die pins.
- o k! y' v% Z& X1110077 ALLEGRO_EDITOR DRC_CONSTR Duplicate Drill Hole DRC's are not shown for Pins overlapped in same symbol unless "Min metal to metal" DRC is turned ON
/ d C6 m9 O5 u! I9 k7 q1110256 ALLEGRO_EDITOR SHAPE Auto void on dynamic shape is not correct in 16.6
- |0 S! u) k N! @7 M$ m1110264 RF_PCB FE_IFF_IMPORT IFF Import in DEHDL has component offset
1 y! A6 A6 `/ {1 \+ L/ B% P1111226 ALLEGRO_EDITOR DATABASE Name too long error with Uprev command when output file name exceeds 31 characters6 g7 O; l, M/ C' L( R* Z
1111234 ALLEGRO_EDITOR MANUFACT Double digit drill character overlaps with figures triangle, hexagon and octagon in NC drill legend
b& S* q, _8 Q* y2 e1112431 SIP_LAYOUT COLOR Frequent crash while working with latest version of CDNSIP
4 j9 j5 _% Q" `% M" I4 P1112493 ALLEGRO_EDITOR DATABASE Customer does not like 16.6 Ratsnest points Closest Endpoint. l0 @, ]( d, V
1112774 GRE CORE Allegro GRE not able to commit plan after topological plan& e7 z( O0 [! f2 ]2 R9 C& a; l
1113908 ALLEGRO_EDITOR COLOR Dehilight command fails to remove highlight pattern on a cline, without removing net custom color.' y; x/ ?9 [. P2 y* L
1114815 ALLEGRO_EDITOR OTHER Q1: Switchversion error when reading -fa file4 ^! e7 e! d2 A/ C5 z( _0 a' Y
1114994 ALLEGRO_EDITOR DATABASE Getting an error after upreving components to 16.6
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发表于 2013-5-2 11:34
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