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LAYOUT GUIDELINES4 U! f* f. F; K# K, L% ~6 V, B
Figure 78 presents a basic schematic of the ADE7953 together with its surrounding circuitry, decoupling capacitors at pins VDD, VINTA, VINTD, and REF, and the 3.58 MHz crystal and its load capacitors. The rest of the pins are dependent on the particular application and are not shown here. Figure 77 presents a proposed layout of a printed circuit board (PCB) with two layers that have the components placed only on the top of the board. Following these layout guidelines will help in creating a low noise design with higher immunity to EMC influences. The VDD, VINTA, VINTD, and REF pins each have two decoupling capacitors, one of μF order and a ceramic one of 220 nF or 100 nF. These ceramic capacitors need to be placed closest to the ADE7953 as they decouple high frequency noises, while the μF ones need to be place in close proximity. The exposed pad of the ADE7953 is soldered to an equivalent pad on the PCB. The AGND, DGND, and PULL_LOW pins traces of the ADE7953 are then routed directly in to the PCB pad. The bottom layer is composed mainly of a ground plane surrounding as much as possible the through hole crystal pins.
: T. N# m2 F& y- I5 T1 F- Q" K佈局指南. M# s5 N# |/ |: I, n
圖78給出了ADE7953的基本原理圖連同其周圍的電路，在引腳去耦電容VDD，VINTA，VINTD和REF，以及3.58 MHz晶振和負載電容。銷的其餘都依賴於特定的應用，這裡不再顯示。圖77提出了一個印刷電路板（PCB）的兩層具有只放在板的頂部的部件的建議設計。遵循這些佈局指南將有助於創造一個低噪音設計，具有更高的免疫力EMC的影響。在VDD，VINTA，VINTD和REF引腳各有兩個去耦電容，一個μF和220 nF的陶瓷一個或100 nF。這些陶瓷電容器需放置最接近的ADE7953，因為他們去耦高頻噪聲，同時μF的必須到位近在咫尺。該ADE7953的露出焊盤焊接到PCB上的等效墊。該AGND，DGND和PULL_LOW引腳ADE7953的痕跡，然後被直接發送到PCB焊盤。底部層主要由周圍盡可能貫通孔晶體引腳接地平面。 |
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发表于 2015-11-6 11:52
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