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高速数字信号设计和高速互连% ]6 c; j2 H4 T& w8 o, M% `: f
CHAPTER 1 Transmission Line Fundamentals.......................................... 1- V" p1 f6 G9 t K
Basic Electromagnetics.................................................................... 1) l) P& f8 ]. G& n: J( X# _$ G
Electromagnetics Field Theory................................................... 1
# h/ }8 G5 R' @3 M! W4 IPropagation of Plane Waves....................................................... 6
! x7 m: d- R6 v" q X) G- q6 wTransmission Line Theory............................................................. 10
+ ?7 `; J% f$ }! G( J# }Wave Equations on Lossless Transmission Lines.................... 11
1 k7 \* Q, l) fImpedance, Reflection Coefficient, and Power Flow
; \3 K. X- }9 e; L7 ]8 }on a Lossless Transmission Line......................................... 145 x' R$ [$ ^6 g/ K* v# ^5 ~6 s
Traveling and Standing Waves on a Transmission Line ......... 168 D% M) g3 }! K# T$ {$ o9 ?
Transmission Line Structures ........................................................ 18+ P6 [3 p6 m3 p) ?2 D1 j4 {
Stripline ..................................................................................... 19
, g( C0 H9 E- ~7 J- r3 QMicrostrip.................................................................................. 20( l2 p$ D6 H8 x; `
Coplanar Waveguides ............................................................... 21 w9 h0 H1 z" S0 }. k4 f4 \
Novel Transmission Lines ........................................................ 22
& g$ K% u+ s5 P, yReferences ...................................................................................... 261 v5 _5 H7 R/ p d5 k. U
CHAPTER 2 PCB design for Signal Integrity........................................... 27/ z, N) t5 b" M6 l, j) W$ r
Differential Signaling..................................................................... 27) G( V9 Z2 f% J, j7 ^ }* Y
Impedance ................................................................................. 28
: h" r& T% r, F+ \, `Time Domain Analysis .................................................................. 31
" E1 d6 G/ B4 ~! a: a) }Eye Diagram ............................................................................. 317 ?& e% S5 w K
Jitter........................................................................................... 33
, @ @; L& u: M h- bFrequency Domain Analysis.......................................................... 42+ G1 x# q0 v; U7 j+ ^3 Z* \
Spectral Content........................................................................ 42
( p# r4 Q$ G: BInsertion Loss............................................................................ 44
1 q# Z0 Q# a3 o; r( p7 ]% oIntegrated Insertion Loss Noise................................................ 46
/ i% k9 A) {0 rReturn Loss ............................................................................... 498 Q* y, P1 H5 \
Crosstalk.................................................................................... 51
% \2 k* S( L' {" t, d! {Integrated Crosstalk .................................................................. 54
+ L! x# g/ M- h. @4 \) `) |Signal-to-Noise Ratio................................................................ 55
9 f/ q* L1 P5 R7 gStack-Up Design ............................................................................ 58
9 o P H0 R7 ~4 m3 [- nImpedance Target (Routing Impedance) .................................. 59
g5 J; \- h0 q6 [; {PCB Losses ............................................................................... 61
: g9 M# q. l9 O# H9 EDielectric Loss .......................................................................... 62
! m' m4 b* Y- z' f4 HConductor Loss ......................................................................... 65
) |7 }& s& N- F. c; Y1 U# rCrosstalk Mitigation through StackUp..................................... 689 B7 K T5 C3 y
Dual Stripline ............................................................................ 73# C8 C# P v( k# P' p
v
) x6 X, \: C) ]' v3 ZDensely Broadside Coupled Dual Stripline.............................. 845 N" b4 W1 G0 c* f, }
Via Stub Mitigation .................................................................. 86: a# f: N0 t# n/ J$ u# X0 B
PCB Layout Optimization ............................................................. 95# G! \, E* Z$ \3 W% h
Length Matching....................................................................... 96
M* l* c2 ]# bFiber Weave Effect ................................................................... 99
: K% u# L, v9 ~- |% b2 W" L$ zCrosstalk Reduction ................................................................ 101
; m p- p' ]5 y4 ^; k( WNon-Ideal Return Path ............................................................ 1077 q$ }5 R7 w9 `7 u; s' G# u
Power Integrity........................................................................ 110
' ^8 f) i3 d" x! Q# |3 T7 }" iRepeaters ................................................................................. 111- N0 h; g0 I1 V7 L
References .................................................................................... 115
& I$ Q1 O! g6 R0 E8 Y% FCHAPTER 3 Channel Modeling and Simulation.................................... 117
% i: J) K- f2 Z1 u* OTransmission Lines ...................................................................... 117
( e: A9 }1 x: JCausality.................................................................................. 117. B) T, h3 x3 ]7 \
Checking for Model Causality................................................ 118
4 M H# v6 X$ r9 {Causal Frequency-Dependent Model...................................... 120 J, x f$ C9 r& L }/ P
Copper Surface Roughness..................................................... 121
0 e3 F- n+ _, |4 |Conductivity............................................................................ 126* G' ~" D1 u8 i7 h
Environmental Impact............................................................. 127
& l6 S6 b0 z4 t9 UModel Geometries................................................................... 130
# k$ w- s& T; W) DCorner Models......................................................................... 133, X9 A$ q' s$ |1 h
Ideal Assumptions: Homogeneous Impedance....................... 137 R3 x" D f, T1 r
Ideal Assumptions: Crosstalk Aggressors .............................. 137
. y8 A& d7 y6 m3 @" cTransmitters.................................................................................. 1382 z9 [4 n2 @; \5 R
IBIS Models ............................................................................ 1386 ]6 U0 r+ \! t
Spice Voltage Source Model .................................................. 139
Q, }7 k, ~" [$ W8 n3D Modeling ................................................................................ 141
. G0 @% G* G5 O" [, qPorts/Terminals ....................................................................... 142( H# n# h; p2 C @0 y. d0 x( F0 g
Model Analysis Settings ......................................................... 144
w2 z8 g2 |) sPlated-Through-Hole Via............................................................. 146
) g$ R3 }" J; M! l" | F* ~Model Techniques................................................................... 147, w' W6 w7 z6 B! w
Pre-Layout Approximation ..................................................... 148
9 K; L7 |9 o! oPre-Layout Modeling .............................................................. 148
- ?* l% b7 B3 E8 j" z. EPost-Layout ............................................................................. 1499 Q3 t2 {% w' H, b
Connectors.................................................................................... 150# i. j4 @9 v8 \/ r2 [- Y
Connector Variability.............................................................. 150
9 F0 z0 {1 Z/ x: aSignal Selection....................................................................... 150
& N: Y* ~( [) Z0 ESeparated Via Models............................................................. 152; v1 j7 s6 V* ?* w5 N( E, y
Unconnected Pins.................................................................... 153- \* Y% q3 m# p/ o
Physical Features..................................................................... 154: [2 b, @8 `# b% M9 ?9 O
Design Optimization ............................................................... 154
7 |4 T- P- Q% m% j* b" j5 ~! UPackages....................................................................................... 156
$ K1 B+ R% A% d! W2 v% Y$ qC4 Escape................................................................................ 1588 t. \$ A2 t2 M4 G" `
vi Contents b: F7 l2 u9 w# E4 J
Transmission Line................................................................... 158. t5 C2 ]% M2 ~- `
PTH Via .................................................................................. 160
- T7 ^1 g* A5 M/ \( {: k9 X+ h" nBGA Model............................................................................. 160/ I4 H3 t# g1 P
Signal Selection for 3D Package Structures........................... 161- `; c, l4 v# h, ?3 E
References ....................................................................................161
S4 b: J- e3 D$ J# z5 i2 {CHAPTER 4 Link Circuits and Architecture .......................................... 1634 k! l3 V- J, A7 C
Types of Link Circuit Architectures............................................163
9 H+ \7 y [8 k2 eEmbedded Clock Architecture................................................ 1633 s, w/ |3 m# Y6 m! t' e+ ]
Forwarded Clock Architecture................................................ 164
0 A& G2 q& `& R; Q4 VTermination ..................................................................................165
+ N! ~/ v" n. Q) E! FDC and AC Coupling.............................................................. 165! r" \! `$ p/ }# y! W
Termination Type.................................................................... 166
; d% q( N$ ?0 L: YTermination Circuits ............................................................... 167
; i4 O7 S9 ?/ r1 KTermination Calibration Circuits............................................ 168
; V+ k" n2 w6 B9 P7 m+ i/ oTermination Detection Circuits .............................................. 169
3 x ^3 {( d% p" B/ o# O6 wTransmitter ...................................................................................170
7 c* ]7 V) F0 H; H7 G; _Transmitter Equalization......................................................... 171
+ N& ?# D( [5 u! D: L. K% XTransmitter Data Path ............................................................. 1733 a* A; B, w6 J E
Current-Mode Driver .............................................................. 174% u) y! z+ G& ?' R! G9 d$ ?4 C$ B
Voltage-Mode Driver.............................................................. 1777 q n7 N. |* E$ r P% k
Receiver........................................................................................179# ~4 G! F* Y E: x
Receiver Equalization ............................................................. 180; c1 C. G, c- P% m$ H8 ]6 ?1 k5 n
Receiver Data Path.................................................................. 1827 |. s- j4 L+ b4 x
Continuous-Time Linear Equalizer ........................................ 184
- z4 b* Y: n' vDecision Feedback Equalizer.................................................. 184
- R2 D G) ?/ H2 s6 y# h6 ~Data Sampler........................................................................... 186
% _/ U# b( L6 A( |0 o- x% _Error Sampler.......................................................................... 186; ~. K2 ~: r* S& X( o2 l1 Y
Receiver Calibration ............................................................... 187
$ n7 D' Q% k/ `4 qReceiver Adaptation................................................................ 188
/ `" c$ `! k8 R6 a5 dClock and Data Recovery............................................................190
5 V1 w4 ^$ m6 A5 r% c/ yClock and Data Recovery Loop ............................................. 191; L' ~$ f- B0 P+ b2 D3 S8 H
Phase Detectors....................................................................... 192
0 v$ ?$ W5 M" w- E' qForwarded Clock Receiver ..........................................................1950 p |6 H: {0 e, u: V: y
Delay-Locked Loop ................................................................ 195: F- a r8 w! D0 b
Design for Test/Manufacture.......................................................195
, R' \/ V+ l# v6 SAnalog DFx Features .............................................................. 1968 j* o2 W6 D9 n- I
Digital DFx Features............................................................... 196
v6 V8 ]' M" K/ @0 E$ F( @0 TReferences ....................................................................................198
* h& m, y8 h7 o9 r: h' b! RCHAPTER 5 Measurement and Data Acquisition Techniques............... 1990 |) y1 J* y, ?% K! B4 L
Digital Oscilloscope Measurement..............................................199
7 w; e/ E: a" zReal-Time and Equivalent-Time Sampling Scopes ............... 199
: f4 ]* ?: R+ v d& u/ X6 IContents vii
) d2 c- a4 F6 fBandwidth ............................................................................... 200
& S' ^, T8 r! M: x2 x. f& IScope Digital Filter Applications ........................................... 202
" \9 S- C/ R; l5 y; ~' d1 s$ v" KTDR Measurements ..................................................................... 204
7 [! q( v2 [, @3 C5 [) z- c- J4 bDe-skew Differential Pairs with TDR .................................... 205
- X% E# ^$ h; l; vChannel Characterization with TDR ...................................... 207$ H4 U5 h/ [7 p: o. X
Return Loss Measurement with TDR..................................... 209
2 _8 Z3 o/ S3 wVector Network Analyzer Measurement..................................... 2112 Z& t. A+ i) z# K/ n& {1 ^+ k5 @: A d
What is VNA?......................................................................... 211
+ ^4 D, D1 t8 ~VNA Error Sources and Calibration....................................... 2131 P5 s' m# k; _3 g! c
Full Two-Port SOLT Calibration Procedure .......................... 217( X; ^8 S4 s5 X8 {9 p9 j' ]* ?
Example of Measurement Using VNA................................... 217
7 B# P. G+ l; S& F) v' o& AVNA Measurement Procedure................................................ 218+ F3 a" I) j( b* B, d+ Q0 t
References .................................................................................... 2190 q$ l* [5 c( V1 b, M
CHAPTER 6 Designing and Validating with Intel Processors............... 221# q6 Q& t k- o3 A
Designing Systems with Intel Devices........................................ 221
* X5 c/ m. Y6 K4 MInterconnect Model ................................................................. 221
2 d8 U4 p! D; R7 o3 M/ T; OEqualization Models ............................................................... 223
6 `, \6 t( a. B7 O' |; XAutomatic Equalization Adaptation ....................................... 225$ O% {% o# [! U4 ?2 M, }$ H
Performance Analysis ............................................................. 227; `( R5 N9 K/ {& H+ _! `
Solution from Design of Experiments.................................... 2321 D: x2 d- R! x) `0 y) i
Solution from Typical Models................................................ 234
$ s+ A" `, J. ~ V( q5 tSystem Validation with Intel Devices ......................................... 237
) X: ?0 A( ^3 J, S, k+ a0 XPower-on Preparations ............................................................ 237. `' o- p) t/ a: M& m/ h! i
Types of I/O Design Validation ............................................. 238. j. p' E" K' t. S9 R! X9 I
System Margining Validation Overview................................ 239; M" {' _1 U$ l+ }
DDR System Margining Validation ....................................... 244
# |, g, O H5 q/ }) E" s- I7 wHigh-Speed Serial I/O Margining Validation ........................ 246
" H; j- q/ T; H# X1 E! jLow-Margin Debug Guidance ................................................ 2490 H9 u! K' f2 a$ n& S( H
Summary ...................................................................................... 250
! K9 ?0 x* m# R5 u, d/ n& sReferences .................................................................................... 2500 }8 f9 _1 G) G; U8 |: A3 {
Index .............................................................................................................) B9 n0 {& n( z4 n
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