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高速数字信号设计和高速互连# x2 Z0 t4 U2 f' r6 Z. L& M; z/ E" j0 J
CHAPTER 1 Transmission Line Fundamentals.......................................... 19 ~6 X# [* w$ m6 h% }+ L
Basic Electromagnetics.................................................................... 1
5 ?" ^3 H0 d. w# W! b* [# eElectromagnetics Field Theory................................................... 19 g$ {4 m7 k7 D6 a# A. P: l5 L
Propagation of Plane Waves....................................................... 6
# E& C' x4 A: e' K2 m9 ~3 ~Transmission Line Theory............................................................. 10+ e" m" X9 ^# }$ @! X
Wave Equations on Lossless Transmission Lines.................... 11. n* X1 b9 a* F( Q6 O
Impedance, Reflection Coefficient, and Power Flow
_+ k0 p( p+ \3 W$ K* j4 m4 K3 h$ `on a Lossless Transmission Line......................................... 140 @4 `$ g) z) Y6 a5 }5 w5 Z
Traveling and Standing Waves on a Transmission Line ......... 16
9 I, Q4 I v' S5 W2 c' ]Transmission Line Structures ........................................................ 18
# w' ?5 _/ j' JStripline ..................................................................................... 19
4 ~) N- K. J! O" Y# [Microstrip.................................................................................. 20
6 [, H; X( h6 E: g& i2 t$ ~Coplanar Waveguides ............................................................... 21
6 V6 E5 D" C$ c1 Z& mNovel Transmission Lines ........................................................ 22& T W9 ~. w* E$ d% d- F
References ...................................................................................... 26* e5 n! d4 ]. r$ I X6 E. U
CHAPTER 2 PCB design for Signal Integrity........................................... 27; I+ h4 q' |9 {! C, t7 k3 E. d
Differential Signaling..................................................................... 27
7 k, |* w2 n+ i2 | s# AImpedance ................................................................................. 28' v$ O/ f! {. E9 ^
Time Domain Analysis .................................................................. 31
' p" ?# ?) v& S: X* xEye Diagram ............................................................................. 31
# u) \( k% |! q1 I' K* E) fJitter........................................................................................... 33/ Y; G- U8 ~* M2 K$ a# O) r
Frequency Domain Analysis.......................................................... 42
$ S- o2 x0 X4 @/ E5 [5 v2 z% m! VSpectral Content........................................................................ 42; q/ @) C# Z' s* ~4 d+ A7 }$ v
Insertion Loss............................................................................ 44
: Z& S! |% q. t" o& j! X( K# Q7 UIntegrated Insertion Loss Noise................................................ 46, {( P3 X- o! v$ R. K" u7 q: O
Return Loss ............................................................................... 494 S( x" c5 {+ k7 L. \
Crosstalk.................................................................................... 51
7 ]( k% s7 s3 \0 w, MIntegrated Crosstalk .................................................................. 548 I. c8 d; H2 t H
Signal-to-Noise Ratio................................................................ 55* A" a' j. x6 d+ e+ k7 b5 i
Stack-Up Design ............................................................................ 584 p( p7 ]# U8 F; c# t
Impedance Target (Routing Impedance) .................................. 59& `( ^2 ~3 D3 Y& n/ _( e) b8 P+ x) j5 f
PCB Losses ............................................................................... 61
6 D% f4 P" c$ U [ R, j" G& m. K$ lDielectric Loss .......................................................................... 62, a$ x9 R! C7 ]2 g- v
Conductor Loss ......................................................................... 65( I6 o. _3 l( _: ]! m9 t+ l6 A
Crosstalk Mitigation through StackUp..................................... 68
+ l) t+ B/ ^6 M6 O/ G0 FDual Stripline ............................................................................ 73
8 I# M1 b2 |+ x4 z1 ^# ?v4 i8 b1 g8 o3 s# J9 p/ W
Densely Broadside Coupled Dual Stripline.............................. 84% p3 m9 T/ n& j" q, H2 Y& d
Via Stub Mitigation .................................................................. 86" V. S% }; ]7 F) E
PCB Layout Optimization ............................................................. 95
6 { }* z5 K |) E6 [Length Matching....................................................................... 96. ^. j' p5 N+ K4 Z
Fiber Weave Effect ................................................................... 99. V$ ^9 F1 H; ^4 @2 \
Crosstalk Reduction ................................................................ 101: x2 U" m2 O" K/ @- p) h {; |
Non-Ideal Return Path ............................................................ 107
& f/ z w6 J# |" h$ r0 mPower Integrity........................................................................ 1106 U' k& `1 \ l6 c- x
Repeaters ................................................................................. 111
$ R, x9 i. `! B8 DReferences .................................................................................... 115
5 w, q: ]% [2 VCHAPTER 3 Channel Modeling and Simulation.................................... 117
* {! T& B5 x4 _' Y q# HTransmission Lines ...................................................................... 117
$ C6 e" J- y. TCausality.................................................................................. 1176 v: }" ~4 I8 y9 D6 v0 Q* u
Checking for Model Causality................................................ 118
- V) S- m4 N! Y9 N$ B# b& a6 S9 lCausal Frequency-Dependent Model...................................... 120' Z4 b* I6 W) ?
Copper Surface Roughness..................................................... 121
& ?! Q/ z, [9 e5 g kConductivity............................................................................ 1268 j# }* x1 j" X% b/ M6 C) [
Environmental Impact............................................................. 127
3 F$ J8 g, s, f% ?1 JModel Geometries................................................................... 130
5 `2 J: x5 W2 tCorner Models......................................................................... 133+ d$ ?) H- M7 X) ^3 M8 I5 A; E
Ideal Assumptions: Homogeneous Impedance....................... 137: e2 F: z7 \7 G+ O
Ideal Assumptions: Crosstalk Aggressors .............................. 137
0 U3 z. ?" F% |1 _6 KTransmitters.................................................................................. 1386 {8 W2 C- x, S7 Y$ O
IBIS Models ............................................................................ 138
/ Y8 l* j1 t- ^. Q# {' HSpice Voltage Source Model .................................................. 1399 C8 u# K1 H" E7 E
3D Modeling ................................................................................ 1415 W- d3 O- \- w. B$ _
Ports/Terminals ....................................................................... 142
/ s7 `) P/ h. L1 PModel Analysis Settings ......................................................... 144. A \& g9 Y j: _8 @
Plated-Through-Hole Via............................................................. 146
& S. N8 x; F7 d" B- i+ N% `% L) i3 ]Model Techniques................................................................... 1477 z' C$ X) F0 \2 X' V5 C4 ?: P- j: l
Pre-Layout Approximation ..................................................... 148- }; f" s; F' ]3 [6 y; g
Pre-Layout Modeling .............................................................. 148* u* x$ W% ^1 g$ B- d6 i1 {
Post-Layout ............................................................................. 149
7 I0 O# U# e& B6 J" rConnectors.................................................................................... 150" i5 E# p$ V j" t) Q
Connector Variability.............................................................. 150
) U+ `! @! @ a8 F8 a \! D [Signal Selection....................................................................... 1507 _5 \" b2 B$ L4 F) D) }. ? I
Separated Via Models............................................................. 152+ q8 S% `+ ^% a" t& ]) w
Unconnected Pins.................................................................... 1533 p7 h/ i# z/ y. Z
Physical Features..................................................................... 1545 {; P& }% i7 h
Design Optimization ............................................................... 154
3 B: c* q7 |: A* k! Y1 c$ z- x2 J% o* APackages....................................................................................... 156
$ a* S" F3 X" }2 lC4 Escape................................................................................ 158
8 g+ {+ k' d7 P* d4 ^vi Contents
$ q0 a1 M' e; F7 f0 MTransmission Line................................................................... 1588 _8 _7 |; f {& z; M( n2 I
PTH Via .................................................................................. 160
' N& d$ D8 H& ~( mBGA Model............................................................................. 160
0 n5 w7 B- A' ASignal Selection for 3D Package Structures........................... 161
. S( @, V3 }, q& A. s/ S% r" QReferences ....................................................................................161( o, h0 o' M3 K/ s: i* T6 ?
CHAPTER 4 Link Circuits and Architecture .......................................... 163& `' [+ M, L+ y0 R! h/ J3 ]
Types of Link Circuit Architectures............................................163, M4 h# C! z- B2 @& R j$ N/ K
Embedded Clock Architecture................................................ 1632 Y6 h, q! K. [3 h/ P7 @5 y' F( h
Forwarded Clock Architecture................................................ 164
" |6 y! f7 J. Y4 l7 _! Y, ATermination ..................................................................................165
9 [. ~- ^' V2 G' d% d+ t4 PDC and AC Coupling.............................................................. 165
( m+ F# g( h& X+ E7 y, ^Termination Type.................................................................... 166( `3 T+ e1 D9 m0 L! b1 a
Termination Circuits ............................................................... 1674 O4 k2 @% S2 q- c2 U" v% D
Termination Calibration Circuits............................................ 1687 v6 F: }7 T- K; w3 J) y; g
Termination Detection Circuits .............................................. 169
" W4 Z; Z6 x4 s: D+ x. d1 R: D) WTransmitter ...................................................................................170# j$ q5 l0 q( p: n) ?" _+ q! |& S8 @* `/ I
Transmitter Equalization......................................................... 171
7 [, T) g/ n* pTransmitter Data Path ............................................................. 173" B% Y. Q% t2 G4 E7 T
Current-Mode Driver .............................................................. 174
% F6 U$ i- i+ ~* W) a, VVoltage-Mode Driver.............................................................. 177
/ `) v- i3 a/ p! L8 GReceiver........................................................................................1791 v* \+ A1 H, R; _$ s9 ^
Receiver Equalization ............................................................. 1805 O( [& d6 H0 i \
Receiver Data Path.................................................................. 182$ H6 w4 F( @( X. r! L
Continuous-Time Linear Equalizer ........................................ 184: k4 u1 x. Q' S% l f) V
Decision Feedback Equalizer.................................................. 1849 f6 x$ F* o, m+ E3 H
Data Sampler........................................................................... 186, U2 N8 \4 J6 J( q: p9 t
Error Sampler.......................................................................... 186% q: m: ^8 Z' f: f4 [" h
Receiver Calibration ............................................................... 187+ a) y$ W4 l: @4 B8 j$ k
Receiver Adaptation................................................................ 188
$ |/ r6 M' j; R2 y2 ZClock and Data Recovery............................................................190
5 T9 M$ k3 X+ ?% XClock and Data Recovery Loop ............................................. 191
7 D0 C; b! a# Q9 g7 L' M5 F; B. BPhase Detectors....................................................................... 192
( o/ n+ y* p+ ], D% a# OForwarded Clock Receiver ..........................................................195" j" e$ X8 R, {1 B" s3 V
Delay-Locked Loop ................................................................ 195
% O5 W% S; V4 k- @% q4 Z) k" xDesign for Test/Manufacture.......................................................195
/ q9 ~4 P$ {# _% cAnalog DFx Features .............................................................. 196* z3 u6 p& s( f& q k$ L* w
Digital DFx Features............................................................... 196/ Q& D4 `$ a7 B
References ....................................................................................198
; w3 l) j( q" ?( ~% _CHAPTER 5 Measurement and Data Acquisition Techniques............... 199
4 @5 o% Y8 y" E3 _ p; xDigital Oscilloscope Measurement..............................................199
. A. V! Z* k# k- t( aReal-Time and Equivalent-Time Sampling Scopes ............... 199
) E) @$ s+ s/ x2 u0 SContents vii" j5 I& u+ J' J
Bandwidth ............................................................................... 200
6 q7 z3 d9 M9 hScope Digital Filter Applications ........................................... 202
) P, Q# d: T+ K% x* ~% }TDR Measurements ..................................................................... 2045 O/ ?; u/ ^% P, j
De-skew Differential Pairs with TDR .................................... 205
# W% j u! n3 s4 [Channel Characterization with TDR ...................................... 207
: @/ O6 g' j+ X# D9 {# s0 C- R4 O. ~Return Loss Measurement with TDR..................................... 2094 R. @2 j6 m2 _
Vector Network Analyzer Measurement..................................... 211
* @! a- s2 n/ R, f9 e$ LWhat is VNA?......................................................................... 2111 C2 Z, S$ R; q
VNA Error Sources and Calibration....................................... 213& X' W- M4 }. V1 q9 ]
Full Two-Port SOLT Calibration Procedure .......................... 2174 s* N0 H9 w2 ]1 p( I7 U
Example of Measurement Using VNA................................... 217
1 ^7 V8 c+ l! N _$ W8 y7 `VNA Measurement Procedure................................................ 218
% D, F+ g1 x: S7 }References .................................................................................... 219( x; h* H" w2 U, k: `" i# s% ~) v6 x
CHAPTER 6 Designing and Validating with Intel Processors............... 221
: v/ Y+ _3 v0 [Designing Systems with Intel Devices........................................ 221
% ]6 C1 E$ [2 ^8 OInterconnect Model ................................................................. 221( X3 O0 w' u% ]. {, a( d q. ?7 p
Equalization Models ............................................................... 223" q+ I+ r) P# d6 R, n; t
Automatic Equalization Adaptation ....................................... 225
@# T' X. u2 _: U/ ZPerformance Analysis ............................................................. 227: K `8 w5 E8 }+ s
Solution from Design of Experiments.................................... 2320 e/ j4 O2 F: @ ^
Solution from Typical Models................................................ 234+ D' j8 E3 |$ t& B; u
System Validation with Intel Devices ......................................... 2370 T* T. w6 D2 O% T
Power-on Preparations ............................................................ 237$ X1 Q+ U) s) [9 E8 V6 M
Types of I/O Design Validation ............................................. 238
) f% |- O8 ?& DSystem Margining Validation Overview................................ 239+ d, x: D8 `' C% A" K- z
DDR System Margining Validation ....................................... 244( b. r! k* Z: ]( y# u1 a
High-Speed Serial I/O Margining Validation ........................ 246
& M$ h. j, A" W- pLow-Margin Debug Guidance ................................................ 2495 G3 x* d# b7 h! X$ k. x( X
Summary ...................................................................................... 250
$ C8 _' [8 q+ H; \- SReferences .................................................................................... 250% Q! t# i$ t# i2 X" D1 t
Index .............................................................................................................) W4 @/ Y$ { r
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发表于 2017-7-6 14:49
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