|
|
EDA365欢迎您！
您需要 登录 才可以下载或查看，没有帐号？注册
x
高速数字信号设计和高速互连. N" d |, H- ~" a( P& m
CHAPTER 1 Transmission Line Fundamentals.......................................... 1- t% c$ r% g4 t
Basic Electromagnetics.................................................................... 1
7 i3 V# d3 g9 CElectromagnetics Field Theory................................................... 1
& F1 l3 o: o5 n; w3 Y- FPropagation of Plane Waves....................................................... 6
" u8 p5 S" ]& k' LTransmission Line Theory............................................................. 104 [6 R, E6 U6 a$ ?
Wave Equations on Lossless Transmission Lines.................... 11
" ^4 j& n: S5 o8 v2 mImpedance, Reflection Coefficient, and Power Flow
7 L! k3 C) D( N( X5 ?& g3 g5 Pon a Lossless Transmission Line......................................... 14
: c& E' i7 P0 B7 F) RTraveling and Standing Waves on a Transmission Line ......... 169 s' \# i. ]2 h
Transmission Line Structures ........................................................ 18$ ? P+ ^0 f1 B% _/ a
Stripline ..................................................................................... 19
8 |/ C. Q+ ]- O' eMicrostrip.................................................................................. 20
: D: F# g9 r5 h4 BCoplanar Waveguides ............................................................... 21
( V9 H$ J) A/ ?6 W+ H( v% fNovel Transmission Lines ........................................................ 22' b7 c' W% ~ x: C$ b: M
References ...................................................................................... 26$ g9 ]. W4 T9 W0 x, g- ~8 `$ e$ [
CHAPTER 2 PCB design for Signal Integrity........................................... 27. X! j: R8 x x F% \. H3 Q
Differential Signaling..................................................................... 27- ]) V u# c9 L- d; Y8 j
Impedance ................................................................................. 28. q' ?4 `+ F! O) q
Time Domain Analysis .................................................................. 31) v" P# S) T4 [/ V) y6 Z
Eye Diagram ............................................................................. 31
, ^: W) \; s; C: A* PJitter........................................................................................... 33
* d7 H/ T1 p3 i0 B1 X* s. }Frequency Domain Analysis.......................................................... 42+ U6 k8 ?$ Y& f! ?9 m3 k( N
Spectral Content........................................................................ 42
4 T3 S# D, u/ V x8 B& n) g" r ^Insertion Loss............................................................................ 44) z$ x u! W! Y: L8 _1 H0 x& z
Integrated Insertion Loss Noise................................................ 46
5 Y1 z0 C; _% Y8 eReturn Loss ............................................................................... 49% x# _0 t) H3 J; U% v
Crosstalk.................................................................................... 517 h5 W" {, Z Z, U g D$ q
Integrated Crosstalk .................................................................. 54
0 s! ^8 p g* q/ u! ]$ {2 YSignal-to-Noise Ratio................................................................ 55; c' j, U+ w1 Q, A/ ~" ^- w
Stack-Up Design ............................................................................ 58; p2 S4 E+ Z7 y \3 n* y( Y
Impedance Target (Routing Impedance) .................................. 59
) c5 W, n p; X3 _6 b+ {6 ?: A" S, dPCB Losses ............................................................................... 61 p) k) N; J R4 e' C8 C8 A
Dielectric Loss .......................................................................... 629 q! K, R8 h9 a K1 B$ A
Conductor Loss ......................................................................... 65, Y5 R6 `1 J2 _4 z. A
Crosstalk Mitigation through StackUp..................................... 68
3 ~! ?& T' _9 G+ U/ R) q$ V: {3 S+ _" lDual Stripline ............................................................................ 73
; m; }$ ^" G( z7 qv
% v& W/ |* W8 Z! X" v9 h) G" R0 EDensely Broadside Coupled Dual Stripline.............................. 84( J) i% I I& W2 }
Via Stub Mitigation .................................................................. 86& A' v/ a% E' A
PCB Layout Optimization ............................................................. 95; J! i- \0 [/ m" C7 N; p. F0 S" C, b
Length Matching....................................................................... 96
9 K3 ^' Q0 F$ W1 d+ rFiber Weave Effect ................................................................... 99/ a: s/ n3 u5 F& E( {& |
Crosstalk Reduction ................................................................ 101
9 |1 s* @- v+ l0 S+ f% DNon-Ideal Return Path ............................................................ 107) V' a1 C2 v& P, d# N
Power Integrity........................................................................ 1102 p, |0 ^( L$ a) k6 n8 X
Repeaters ................................................................................. 111
- w1 c, J+ V2 ^' d7 W0 `% k9 r2 a/ `References .................................................................................... 115/ o' Z# b, E- g, l9 c9 i9 o S
CHAPTER 3 Channel Modeling and Simulation.................................... 117& \( J! p3 p9 A- L2 y7 L
Transmission Lines ...................................................................... 117' P* U0 J5 v7 j; ]
Causality.................................................................................. 117
9 L- G% s2 G' }/ vChecking for Model Causality................................................ 118
; ]( z3 F* @7 ^) Y" c" P5 }Causal Frequency-Dependent Model...................................... 120
$ N7 p i$ U2 M: p3 |4 qCopper Surface Roughness..................................................... 121
/ p$ `3 |8 U# l* h' X sConductivity............................................................................ 126# u2 A1 @+ M* V' B7 I- e5 b* ?
Environmental Impact............................................................. 127
/ z7 q: Z6 `( y9 vModel Geometries................................................................... 1301 P- u) v0 ]; \8 C0 g1 }0 k4 ]) D4 r
Corner Models......................................................................... 133( x8 S$ g# R. m5 K( C$ u. S
Ideal Assumptions: Homogeneous Impedance....................... 137
( _) ^' V) Z$ @+ M d: i: i+ WIdeal Assumptions: Crosstalk Aggressors .............................. 137" x/ Z4 M3 s% e4 E4 K C8 j
Transmitters.................................................................................. 138
) M& F9 k/ T3 Z- [7 ]IBIS Models ............................................................................ 1389 _) V) f7 u- p& U! |
Spice Voltage Source Model .................................................. 139 o& e( m7 v8 N1 V( X! q6 W* i: H
3D Modeling ................................................................................ 141
6 m9 |) c, _$ {2 W+ h, yPorts/Terminals ....................................................................... 142+ p/ i$ i3 A' ]" L& T0 W/ r% _
Model Analysis Settings ......................................................... 144" Q+ i4 i- y0 Q3 m' `9 X
Plated-Through-Hole Via............................................................. 146
& S- r+ U7 `) C$ @3 a; qModel Techniques................................................................... 147* V) x# L; o: Q, Y7 M! z
Pre-Layout Approximation ..................................................... 148
9 i4 e% s; u. D- f; O( a( P9 QPre-Layout Modeling .............................................................. 1483 V: ^# H; F; D
Post-Layout ............................................................................. 149
% b: H9 T1 x& R& V |3 qConnectors.................................................................................... 150
9 d' v, s! k& i3 a3 c6 k" i# zConnector Variability.............................................................. 150# k+ G3 O6 S$ F4 h! Q1 l; T9 I0 J7 x( x
Signal Selection....................................................................... 150) g8 g7 `: g9 @+ d5 V
Separated Via Models............................................................. 1526 F; z0 x4 @0 \5 @4 I) Q4 p; T. Z
Unconnected Pins.................................................................... 153
2 n7 A1 Y' J% b/ B ^Physical Features..................................................................... 154
& {9 R8 m" I) N6 t5 ]Design Optimization ............................................................... 154
0 _; Y4 _& y3 \5 e9 ?. fPackages....................................................................................... 156: I K1 b+ `+ ` L" e; l
C4 Escape................................................................................ 1587 a! S5 s) R0 t; k" ]
vi Contents
+ M- Y- f" ?3 I! m$ kTransmission Line................................................................... 158
8 A2 u, \& R5 \4 O( Y8 cPTH Via .................................................................................. 1608 B2 U0 o6 }: l8 k' K, u8 ^
BGA Model............................................................................. 160
. {# X( ^% @8 YSignal Selection for 3D Package Structures........................... 161: _3 @. h8 }7 X( o/ y5 O, d+ \) m
References ....................................................................................1619 l' n8 _- ^$ ?% W6 _
CHAPTER 4 Link Circuits and Architecture .......................................... 163
$ W1 W( q, [+ K* f. BTypes of Link Circuit Architectures............................................163+ I; T9 ?! d& P) {% X2 T* Z% G
Embedded Clock Architecture................................................ 163; o: Z& @- x1 E# N: i" r" j- p
Forwarded Clock Architecture................................................ 164( \. J4 M+ A2 _" E% {
Termination ..................................................................................1656 y! d( W6 o4 Q* {
DC and AC Coupling.............................................................. 165
1 H5 b q( g1 g+ m. p2 u/ ]Termination Type.................................................................... 166
7 g% O/ q/ a$ |- l8 aTermination Circuits ............................................................... 167
2 U& @& G# S8 LTermination Calibration Circuits............................................ 1687 _# v3 L9 {+ ^- O" W- X9 ]
Termination Detection Circuits .............................................. 169
) D$ Z# y% A. ^1 R: ~Transmitter ...................................................................................170
, j& C' D# Y+ B V) BTransmitter Equalization......................................................... 171* c8 l! M: H( H% w8 g
Transmitter Data Path ............................................................. 173
! K2 |9 {( n, GCurrent-Mode Driver .............................................................. 174
8 ?4 B$ n8 ]% r: d# H/ T" oVoltage-Mode Driver.............................................................. 177) d5 i, g4 L. G; g% Q9 f
Receiver........................................................................................1792 X. s# v' Y) @# i' @9 A/ C' q
Receiver Equalization ............................................................. 180" \6 u h6 T4 U; S/ G. P
Receiver Data Path.................................................................. 182
2 v* k- l, V, \7 Q5 X( o) S/ P6 ?1 P, sContinuous-Time Linear Equalizer ........................................ 1840 K& q' \; \; @9 S3 l
Decision Feedback Equalizer.................................................. 1840 p2 w. A* q8 ~- P
Data Sampler........................................................................... 186: J! \5 l3 V9 m* J: ?/ X# Q
Error Sampler.......................................................................... 186
* q: u4 M8 J+ \4 u" S/ R& TReceiver Calibration ............................................................... 187
$ H& Z7 G8 ~5 cReceiver Adaptation................................................................ 188
& B, ~+ [5 T. X8 J$ X$ RClock and Data Recovery............................................................190$ Y: e! ?+ `" g) h+ x
Clock and Data Recovery Loop ............................................. 191% Z q9 b |' S y* @. O: V
Phase Detectors....................................................................... 1925 c6 x+ `8 u- f* L# u2 g
Forwarded Clock Receiver ..........................................................195
' @. C3 @2 ?& {. O% x# f$ C+ a8 y. jDelay-Locked Loop ................................................................ 195
6 L- r$ g5 o; N7 Y/ I( aDesign for Test/Manufacture.......................................................195" G6 a, K* C; ]0 G6 k
Analog DFx Features .............................................................. 1968 R- r. {7 m$ v4 ]
Digital DFx Features............................................................... 196' |9 h0 `) m# Z+ `" F
References ....................................................................................1989 K# W1 K3 G/ c( \' T; N% v
CHAPTER 5 Measurement and Data Acquisition Techniques............... 199
; v) }1 y# z/ o9 yDigital Oscilloscope Measurement..............................................1998 q5 E, H5 s' ^) ^+ o V
Real-Time and Equivalent-Time Sampling Scopes ............... 199
3 T! l! @' P- t' W' A6 ^; ]Contents vii6 d, X0 r) ?2 i7 \& ]
Bandwidth ............................................................................... 200
* U% D. x. V0 B2 _Scope Digital Filter Applications ........................................... 202
8 A, @# g f& o6 g7 P8 S eTDR Measurements ..................................................................... 204
% Q0 {/ n* e, n* HDe-skew Differential Pairs with TDR .................................... 205
" f; J5 J1 [0 n& D9 Y) y5 D3 eChannel Characterization with TDR ...................................... 207/ c3 S- S4 h' M! o' K4 c7 F; O: l# Z2 p
Return Loss Measurement with TDR..................................... 209
f5 R+ b, A. k2 ?+ m/ LVector Network Analyzer Measurement..................................... 211" ^* l6 i d4 b7 a+ H o u& \; `
What is VNA?......................................................................... 211, y6 n) k$ J/ y$ ]. D
VNA Error Sources and Calibration....................................... 213
4 R0 o7 ?. R) O: ~, c( \( oFull Two-Port SOLT Calibration Procedure .......................... 217
$ K# ~2 {/ q+ i0 e+ Z1 vExample of Measurement Using VNA................................... 217
; }# x: F9 Z5 c9 u( K% QVNA Measurement Procedure................................................ 218( t4 j* ]% I. E* `
References .................................................................................... 2193 W4 |3 t1 [. H w6 {' R
CHAPTER 6 Designing and Validating with Intel Processors............... 221* @. R9 B9 i+ J
Designing Systems with Intel Devices........................................ 221
( K) n1 ]" m4 M+ O! bInterconnect Model ................................................................. 221$ u2 a3 l4 \0 P8 l8 \
Equalization Models ............................................................... 223' W# c% {9 x, U) f" o% q. `9 H6 d
Automatic Equalization Adaptation ....................................... 2256 C9 n3 g& O5 p- b: A
Performance Analysis ............................................................. 227
! ~7 n9 }- J, P8 i! q% u& N8 kSolution from Design of Experiments.................................... 2322 M) N+ e' K# A* D; D, x* ]+ J) Q5 p
Solution from Typical Models................................................ 234
9 \2 ~/ R. I& r g( P; X" ySystem Validation with Intel Devices ......................................... 237- k/ U+ R+ i7 V4 ]' F$ l1 l
Power-on Preparations ............................................................ 237& [7 t$ E# J! a. c% q/ E
Types of I/O Design Validation ............................................. 238' Q0 r2 {9 S, u4 G$ f( q
System Margining Validation Overview................................ 239
+ H7 X) k4 T$ L, A4 h: pDDR System Margining Validation ....................................... 244 j7 d' J% y0 A7 p [, x
High-Speed Serial I/O Margining Validation ........................ 246
/ t$ `# W8 ~* R. oLow-Margin Debug Guidance ................................................ 2497 n. ~9 |" A2 [. y" y h
Summary ...................................................................................... 250% @5 w, K4 _ X7 [+ o7 l7 k" O
References .................................................................................... 250' ?( d6 T* v; e% j8 B
Index .............................................................................................................7 V/ p* D u }7 M; E( d* o
# l. y# X0 l6 K- z9 _
! z. T- o$ c4 }3 r1 `/ W5 i
- ?- o' ] t( Y5 c: {* e0 @ |
|
/1 
发表于 2017-7-6 14:49
QQ好友和群
QQ空间
腾讯微博
腾讯朋友
微信
收藏
支持！
反对！
楼主
