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高速数字信号设计和高速互连4 ~, {) @$ F( t0 ?$ x8 }9 n
CHAPTER 1 Transmission Line Fundamentals.......................................... 1" ^1 R0 r4 e9 U4 T5 w6 |1 H: P
Basic Electromagnetics.................................................................... 14 _+ a$ [ Q' v/ h: f9 [
Electromagnetics Field Theory................................................... 1
' d9 J# m1 o# ?3 xPropagation of Plane Waves....................................................... 6" j. A- Z& V+ B0 N
Transmission Line Theory............................................................. 10
& m9 ~7 s" |" v2 ^$ N0 ZWave Equations on Lossless Transmission Lines.................... 11) H4 b2 s$ |3 r1 N/ E
Impedance, Reflection Coefficient, and Power Flow0 ]$ F; f+ c e7 A% }7 [' R/ }
on a Lossless Transmission Line......................................... 140 G1 K% G# }: v& C
Traveling and Standing Waves on a Transmission Line ......... 16" G- q, g3 e- C# @ T1 h/ P+ Q
Transmission Line Structures ........................................................ 182 f/ p) n5 Y# o. L9 L
Stripline ..................................................................................... 193 O, s% Z8 z/ c# T
Microstrip.................................................................................. 20
; Q1 d7 m/ _2 F" {6 Q# w6 ICoplanar Waveguides ............................................................... 21
' s/ ~' `) h" _3 j4 @! Y3 d/ hNovel Transmission Lines ........................................................ 224 d) C T' p3 W( l$ x7 v
References ...................................................................................... 26
& X. _$ f! J- Q, @CHAPTER 2 PCB design for Signal Integrity........................................... 27
7 F5 y1 y$ G+ q! IDifferential Signaling..................................................................... 27
5 O; P8 l6 L2 iImpedance ................................................................................. 28
+ K1 S4 Y6 @1 C% K" u4 f% q0 `Time Domain Analysis .................................................................. 31
7 ^" L/ Q. B/ i c4 Z$ IEye Diagram ............................................................................. 31
3 s' k$ S& d# O% Z2 xJitter........................................................................................... 337 O9 Z2 {! p$ O8 P; [: b& k
Frequency Domain Analysis.......................................................... 420 V- D* ?" m& |- i; L0 x
Spectral Content........................................................................ 421 T( o ~' j" \5 R4 u, u1 H
Insertion Loss............................................................................ 44
) u) h4 d+ |2 \; e; V1 v, L+ pIntegrated Insertion Loss Noise................................................ 46# _- ?% t* |$ d8 J
Return Loss ............................................................................... 494 n6 L' h! t8 g, j
Crosstalk.................................................................................... 51
p: A2 u1 X3 D: F8 q: h0 HIntegrated Crosstalk .................................................................. 54
0 T. }7 y% a! C+ P$ p3 fSignal-to-Noise Ratio................................................................ 55% i8 \. ?8 c, V/ n: E" P
Stack-Up Design ............................................................................ 58
" O- M1 o' ?0 ]; rImpedance Target (Routing Impedance) .................................. 59" |6 b3 v, y1 ?) @
PCB Losses ............................................................................... 61
! [! n& x0 v. ^2 vDielectric Loss .......................................................................... 629 V- S: ]) d$ J" }5 S" c* P
Conductor Loss ......................................................................... 65) c+ S. I3 C; a) u- Q3 z R
Crosstalk Mitigation through StackUp..................................... 68
0 X& O1 u, h. iDual Stripline ............................................................................ 739 a4 z! f( J$ ^6 U: L& ^1 s/ b: [& G
v) N( H0 I4 M5 y3 y+ [/ d6 @
Densely Broadside Coupled Dual Stripline.............................. 84
/ i% h% F( g7 y+ i' @$ oVia Stub Mitigation .................................................................. 86' @2 |, r9 b a: l: i, l$ ^
PCB Layout Optimization ............................................................. 95% g2 L/ J& K2 V
Length Matching....................................................................... 96& ]0 L j8 L9 J0 w3 Z# H7 J
Fiber Weave Effect ................................................................... 99
. b" p9 S# x7 d) y5 V; CCrosstalk Reduction ................................................................ 101
/ s' }( M A S$ O2 B" u5 iNon-Ideal Return Path ............................................................ 1070 u& e& e4 }4 _8 f, f! ^
Power Integrity........................................................................ 1107 @8 y! {( e4 R5 V8 H7 H
Repeaters ................................................................................. 111/ t9 o4 P X [. ~+ @
References .................................................................................... 115( O, J7 S& g% L
CHAPTER 3 Channel Modeling and Simulation.................................... 117
) Q1 q$ p7 x" ~4 V" mTransmission Lines ...................................................................... 117
9 x3 E; H3 C! UCausality.................................................................................. 117
) x( C2 e2 X: vChecking for Model Causality................................................ 118! x w/ t4 K' \7 c' R) s7 C
Causal Frequency-Dependent Model...................................... 120
0 W9 {) t! n9 L; I( N4 wCopper Surface Roughness..................................................... 121 d9 E; \* u% x1 P+ D& t
Conductivity............................................................................ 1265 ]) B- B T4 k' ?
Environmental Impact............................................................. 127
) {: O1 d" R" I- ]Model Geometries................................................................... 130" ?% K5 c# Z4 ]4 @! n9 K1 g. k. D
Corner Models......................................................................... 133
( x$ D: ]" H3 S R6 oIdeal Assumptions: Homogeneous Impedance....................... 137
, H3 n0 o0 v$ ]! WIdeal Assumptions: Crosstalk Aggressors .............................. 137
; [; A4 |1 z5 oTransmitters.................................................................................. 138/ Z! X$ O& l; j: j
IBIS Models ............................................................................ 1389 V) S9 x {8 x2 C) Y
Spice Voltage Source Model .................................................. 1391 P" M3 \ n. Q: t2 s% r% v" O
3D Modeling ................................................................................ 141
! B, F6 v! w' y- u* F& c) cPorts/Terminals ....................................................................... 1426 h% ^" Q) x; x
Model Analysis Settings ......................................................... 144
! R/ h0 p' P2 d3 w8 v' BPlated-Through-Hole Via............................................................. 146
3 }5 p- ~# [* ^7 S) a1 I; cModel Techniques................................................................... 147% m; d5 r6 H; m. ^: Y A
Pre-Layout Approximation ..................................................... 148
; N4 G [% E+ oPre-Layout Modeling .............................................................. 148
: |; w! d4 X) Q- X/ W: |9 w: FPost-Layout ............................................................................. 149; b, N3 @" v I1 y' j
Connectors.................................................................................... 1505 O: e' c% |1 X2 Z; @
Connector Variability.............................................................. 150
" y7 z5 b8 A/ L( K A# jSignal Selection....................................................................... 150
" |. m5 {- ~: _: t, @+ pSeparated Via Models............................................................. 1525 h! ]; ]) ^: \! X' m0 P% L
Unconnected Pins.................................................................... 1531 Y) V, l G$ Y/ @) K7 X1 q2 K
Physical Features..................................................................... 154
8 O: d. [+ p2 S2 K' s) X$ n8 oDesign Optimization ............................................................... 154% J" x. Q& P4 s% W/ ?
Packages....................................................................................... 1564 H. J5 o4 n& H( e% [% k
C4 Escape................................................................................ 158" S3 h5 n- W0 M
vi Contents" G* G& x8 t1 K) k( r+ ^# K6 E
Transmission Line................................................................... 158
7 Z |2 j8 u( ?) c8 ~PTH Via .................................................................................. 160
N6 R" ]6 h0 i9 uBGA Model............................................................................. 160, Z. _1 R( m; _* c5 z) @" Y
Signal Selection for 3D Package Structures........................... 161
. [. F: f) {5 p/ O# o# bReferences ....................................................................................161
% g" g0 W( k+ A0 ]+ T, ~CHAPTER 4 Link Circuits and Architecture .......................................... 163# G- i8 {1 G% V( W6 u8 s2 R4 S( X
Types of Link Circuit Architectures............................................163
* p4 j! `8 Y w, W& dEmbedded Clock Architecture................................................ 163
2 m/ H) t j* P5 d; w, iForwarded Clock Architecture................................................ 164
u' ^& z: I- N" [Termination ..................................................................................1658 Y. m8 }3 x, V! X# \8 f
DC and AC Coupling.............................................................. 165
# f B! S+ O8 M5 D, }Termination Type.................................................................... 166
/ h1 V) F1 t3 u/ dTermination Circuits ............................................................... 167. w( Y) ?# m+ b
Termination Calibration Circuits............................................ 168
9 U( C3 @4 ?% C8 VTermination Detection Circuits .............................................. 169
+ x) t: i6 g7 g5 u& GTransmitter ...................................................................................170; Z" Q. j* o( [4 O4 r9 }
Transmitter Equalization......................................................... 171( ?4 B9 w- y2 o; v8 N" I
Transmitter Data Path ............................................................. 1737 K% h9 z5 f; E% a
Current-Mode Driver .............................................................. 174/ ?9 \" E/ m, g% L1 j- _
Voltage-Mode Driver.............................................................. 177
; ], z# M: i1 n7 L4 wReceiver........................................................................................1794 r4 [& u6 r" j) l" t' y% ^/ W1 G
Receiver Equalization ............................................................. 1801 P5 K% X. M, p
Receiver Data Path.................................................................. 182
+ n3 \6 z# d; E w; e3 qContinuous-Time Linear Equalizer ........................................ 184
1 \# i6 Y/ g9 Q+ a2 e1 ^* j1 NDecision Feedback Equalizer.................................................. 184
5 b# x8 A7 g! d* r+ W' v' UData Sampler........................................................................... 186
0 X3 }+ b* @. l( T1 j; kError Sampler.......................................................................... 186
/ D; O) F" i" `/ `$ JReceiver Calibration ............................................................... 187
7 {( S- V- d9 b9 vReceiver Adaptation................................................................ 188
1 ? h4 @! w s7 f+ B0 RClock and Data Recovery............................................................190! c0 P2 Q# h4 l4 Q
Clock and Data Recovery Loop ............................................. 191
6 x; m/ D) x6 ?. m0 @4 U$ ?Phase Detectors....................................................................... 192
4 q8 a$ j! d0 K! GForwarded Clock Receiver ..........................................................195
0 P* Y$ G" P* q; M! f3 z7 U; DDelay-Locked Loop ................................................................ 1958 h i& r9 I* ?) g# h0 g
Design for Test/Manufacture.......................................................195
" D# s2 t/ g- s6 @+ j1 |/ e5 oAnalog DFx Features .............................................................. 196
4 A3 c; }( h) a5 M" T' ?Digital DFx Features............................................................... 196
( J6 |% a. z4 v4 u3 UReferences ....................................................................................1989 L: `7 q; G( O' x F
CHAPTER 5 Measurement and Data Acquisition Techniques............... 199& t# j& `/ J$ G7 J' k0 ?5 X
Digital Oscilloscope Measurement..............................................199* G7 H' }; D, V$ I1 s) G
Real-Time and Equivalent-Time Sampling Scopes ............... 199# Q/ v, j2 m. ~" L! T8 |
Contents vii
" X# X4 K* Y7 V0 fBandwidth ............................................................................... 200& g- Z) Q* `5 a" D
Scope Digital Filter Applications ........................................... 202
; I: i( i; g, ]TDR Measurements ..................................................................... 204% \7 E/ b0 Z7 }1 ?
De-skew Differential Pairs with TDR .................................... 205
$ z9 q% Z# W ]& KChannel Characterization with TDR ...................................... 207
% s8 W1 o' G) j5 m, v \Return Loss Measurement with TDR..................................... 209
) K) H3 ^, B1 r8 ~Vector Network Analyzer Measurement..................................... 211
$ |) }2 g, |# X% q5 VWhat is VNA?......................................................................... 211' \& y# f* S# o: l) q4 n
VNA Error Sources and Calibration....................................... 213
7 I9 ^( c0 c& p( BFull Two-Port SOLT Calibration Procedure .......................... 2172 ?) o% `0 g; k: u
Example of Measurement Using VNA................................... 217
+ s: Z1 x6 u/ `# x3 t) p5 x0 gVNA Measurement Procedure................................................ 218
y( T3 `% C* tReferences .................................................................................... 219
, `/ e- f" m% cCHAPTER 6 Designing and Validating with Intel Processors............... 221+ | Y9 a( I7 {$ F9 J; J( t8 `
Designing Systems with Intel Devices........................................ 221
. n! E( d5 i9 ^7 v( W; cInterconnect Model ................................................................. 221
% ~8 f' ]' c! ?' \Equalization Models ............................................................... 223. }$ O4 B p; n; u# k
Automatic Equalization Adaptation ....................................... 225
: O: J6 ~$ n/ |, rPerformance Analysis ............................................................. 2279 D9 h9 v0 V, O& l" `
Solution from Design of Experiments.................................... 232: ^- z+ K, {; \6 h
Solution from Typical Models................................................ 234 R2 G1 A. J$ ^# H S5 g3 _
System Validation with Intel Devices ......................................... 237" x. e4 O1 T) Z# M* F8 z3 w
Power-on Preparations ............................................................ 2375 F" ~" l" E: o( Y @: D; q
Types of I/O Design Validation ............................................. 238
7 N! }4 T/ w" m8 U/ SSystem Margining Validation Overview................................ 239: e$ B. J+ s+ x, T8 ]
DDR System Margining Validation ....................................... 2442 d0 x( B; k0 J8 @8 N! D5 U
High-Speed Serial I/O Margining Validation ........................ 246
- S; v W2 k) b3 XLow-Margin Debug Guidance ................................................ 249
1 |1 n# s- g/ y8 T) n" s7 A4 xSummary ...................................................................................... 250' H% v/ g! _) ?8 t# Y
References .................................................................................... 250
" @' u$ d# p/ ]$ y' JIndex .............................................................................................................
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