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我在做数模混合仿真的时候，在config中调用模拟电路和数字模块的symble，但是在进行display partition>all active时，系统报错：( ?. S% b3 M9 ~8 M! l1 D
\o *SYSERR: Unable to hdbBind for inst I15 in cell Module tiadc, lib design, view schematic, configViewString spectre spice verilog verilogams behavioral functional schematic veriloga vhdl vhdlams hdl system verilogNetlist cmos.sch cmos_sch ahdl.
% B5 Z3 u2 x1 l+ l4 y# l7 w/ q6 o- {\o *USRERR: Selected context view string 'spectre spice verilog verilogams behavioral functional schematic veriloga vhdl vhdlams hdl system verilogNetlist cmos.sch cmos_sch ahdl'
" u D' c9 t8 N. @! ] G\o offers no suitable view for inst I15 referencing placed master design.add_and_mult.symbol. ^) _# ^* ]7 J6 W# Q
\o in cell Module tiadc, lib design, view schematic, configViewString spectre spice verilog verilogams behavioral functional schematic veriloga vhdl vhdlams hdl system verilogNetlist cmos.sch cmos_sch ahdl." n0 u& |9 B9 C! R
\o Please check HDB configuration or library setup.
7 m8 ^- b0 [3 y! e3 j. I\o *USRERR: Selected context view string 'functional'
1 z" \" N' U. T1 t0 q: `$ C, c\o offers no suitable view for inst I14 referencing placed master design.average.symbol
$ T3 }& X( Y6 W6 ^. u\o in cell Module tiadc, lib design, view schematic, configViewString spectre spice verilog verilogams behavioral functional schematic veriloga vhdl vhdlams hdl system verilogNetlist cmos.sch cmos_sch ahdl.4 |8 \ F- a& Y% u
\o Please check HDB configuration or library setup.$ ?! w0 K1 k* e) ?; L
\o *USRERR: Selected context view string 'functional'
" q6 L5 Q6 K4 M; b' p7 p6 Y$ q1 t\o offers no suitable view for inst I12 referencing placed master design.unit2.symbol) U7 u# Z5 ^. f) V
\o in cell Module tiadc, lib design, view schematic, configViewString spectre spice verilog verilogams behavioral functional schematic veriloga vhdl vhdlams hdl system verilogNetlist cmos.sch cmos_sch ahdl.8 p `4 s- n# `* S
\o Please check HDB configuration or library setup.
1 ?) r5 {! r; l$ h\o *USRERR: Selected context view string 'functional'
6 f6 H# j1 k5 n- @+ _\o offers no suitable view for inst I11 referencing placed master design.unit1.symbol% C7 U O$ q8 N
\o in cell Module tiadc, lib design, view schematic, configViewString spectre spice verilog verilogams behavioral functional schematic veriloga vhdl vhdlams hdl system verilogNetlist cmos.sch cmos_sch ahdl.
6 S9 k/ P0 o O( n7 J+ r" V\o Please check HDB configuration or library setup.
0 B+ ]$ @0 `, V; t8 q% v, [\o *USRERR: Selected context view string 'functional'% N" @0 G" c! x6 x- `& h
\o offers no suitable view for inst I4 referencing placed master design.encode.symbol
4 Z k8 M# h" S\o in cell Module tiadc, lib design, view schematic, configViewString spectre spice verilog verilogams behavioral functional schematic veriloga vhdl vhdlams hdl system verilogNetlist cmos.sch cmos_sch ahdl. [# n9 u: X$ Q# ]4 [
\o Please check HDB configuration or library setup.- b4 I$ V7 L; A
\o *USRERR: Selected context view string 'functional'. c, J# D7 A( v
\o offers no suitable view for inst I2 referencing placed master design.encode.symbol% {* y3 a# W: N# N2 d
\o in cell Module tiadc, lib design, view schematic, configViewString spectre spice verilog verilogams behavioral functional schematic veriloga vhdl vhdlams hdl system verilogNetlist cmos.sch cmos_sch ahdl.% c2 R- k+ r$ z" g q4 Z8 b
\o Please check HDB configuration or library setup.
" w6 P+ n# I) Y4 j& g! A\e *Error* Failed to partition the design.
. J; Q3 P6 }$ B\e $ g V& H: _" o" i; W
\e *Error* mspDisplayPartition: Failed to create network
+ |* K0 L1 t% \8 W* T- j" H8 ^4 {/ P( q/ v/ t
这是什么问题啊？求大神帮忙解决一下，鄙人不甚感激！！！
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发表于 2015-9-11 16:08
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