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Cadence SPB 16.5下载地址（Hotfix更新至044）; M* O5 H$ Q+ _, r
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Cadence最新版软件SPB 16.5及其Hotfix下载链接如下：
- F4 j+ h2 G$ y1 ahttp://dl.vmall.com/c0sfvdb4yy. T) q0 o1 C( P, P0 @+ m& f+ y2 R v
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Hotfix中只需要安装最新的版本即可。% L; ^7 a/ H$ L, @3 G4 o2 s y1 Z
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DATE: 06-7-2013 HOTFIX VERSION: 044& W; J& F& i- Q
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1 s2 Y+ \# n0 H3 l, ~5 kCCRID PRODUCT PRODUCTLEVEL2 TITLE& n2 n6 h& H* G: [7 K1 y7 E9 a
===================================================================================================================================
6 j7 P& W1 y! w" K2 T1055338 SIP_LAYOUT DRC_CONSTRAINTS Soldermask to Via drcs on bondfingers
6 P+ d6 L1 y+ W7 C; @1 ]& V1084716 ALLEGRO_EDITOR OTHER Getting an MPS error when updating CM from SigXplorer9 x2 @5 r7 _% |, M5 V4 v/ A
1104145 ALLEGRO_EDITOR SCHEM_FTB User defined properties do not appear in PCB
6 W' J( q8 w) f! p5 K+ I" ?- u1106116 FLOWS PROJMGR view_pcb setting change was cleared by switching Flows in projmgr.7 w4 k1 L2 ^5 R0 h2 O v4 T
1106900 CONCEPT_HDL COMP_BROWSER Component Browser performance utility should honor CPM directives for include and exclude PPT
# O. `) H2 _; @+ h1110323 APD DXF_IF DXF out is offsetting square discrete pads.
; d1 ~. M" Z/ r% ?1119007 CONCEPT_HDL CORE PDF Publish of schematic creates extremely large PDF files
2 D+ Y6 i* x# M) m7 s- K+ w1121020 FSP MODEL_EDITOR Cut-Paste from Excel causes empty cell in Rule Editor
3 V J6 L2 D* L& T n/ B1121353 ALLEGRO_EDITOR INTERACTIV Local env setting will change after saving and reopening.8 u, u# ~; a8 B3 o- V u# r3 g
1122781 CONCEPT_HDL CORE cfg_package is generated for component cell automatically- B; t+ p# r# ?9 b, J
1122909 CONCEPT_HDL CORE changing version replicates data of first TOC on 2nd one/ ~7 l4 B0 s9 G9 q, K" f: y( h
1123581 ALLEGRO_EDITOR MANUFACT Dimension Line gets changed on board
3 x% a s/ W2 k5 L# v1124544 CONCEPT_HDL CORE About Search History of find with SPB16.5
: p6 j+ H1 Q2 s7 l4 T8 o" t0 }1125366 CONCEPT_HDL CORE DE-HDL craches during Import Physical if CM is open on Linux9 V+ r" | V& S1 V* T" Y( d R) X
1125628 CONCEPT_HDL CORE Crash on doing save hierarchy
5 B2 \& o3 _" |7 I9 Z, a9 o1126182 ALLEGRO_EDITOR DRC_CONSTR Shape fillet DRC in same net thru via to thru via was removed after update DRC.
, ? K! Y) b2 S4 m/ h1130945 SCM SCHGEN SCM Export Schematic does not copy all cells in the library
: o" @# z/ q# K7 g1131567 CONCEPT_HDL OTHER Lower case values for VHDL_MODE make genview use pin location to determen direction.+ {4 u/ {# I/ s% ^+ Y
1131650 ALLEGRO_EDITOR PLOTTING PDF Publisher doesnot display few component defination properties in Property parameters
& C: o* _! g% a _9 ~. x1131868 CONCEPT_HDL CONSTRAINT_MGR Many net-class constraints "fell off" the design after uprev and Import Design of GEP45 j2 b8 M8 Y3 F! \3 k9 @
1132457 CONCEPT_HDL CORE The schematic never fully invokes and has connectivity errors.
2 S. K/ @ `6 l& ]5 J8 Q1132575 CONCEPT_HDL CORE 2 pin_name were displayed and overlapped by spin command.
4 c% |" M- V8 N5 ]4 @ K! t) S1132638 ALLEGRO_EDITOR DFA 'dfa_update' crashes when running the utility on the attached foder.7 L6 J4 r2 Q/ [
1133677 CONCEPT_HDL CORE Cant delete nor reset LOCATION prop in context of top
6 d0 D+ h! D4 S1133791 CONCEPT_HDL CORE Cant do text justification on a single selected NOTE in Windows mode.
- O9 O# X8 u% f& @6 q V* e! N1134083 CONCEPT_HDL OTHER Published PDF file's hyperlinks do not work fine when user use double digits partitions for page Border.9 F/ V/ g; j$ u
1134761 CONCEPT_HDL CORE Why does Mouse Pointer/Tooltip display LOCATION instead of $LOCATION property% x7 I4 y: w4 W7 U6 W; l& G. ?1 C
1138586 ADW MIGRATION design migration does not create complete ptf file for hierarchical designs
" n1 H8 s% m. {0 ?1139376 CONCEPT_HDL CORE setting wire color to default creates new wire with higher thickness* V6 Z" c/ w7 t6 z# }
1141300 CONCEPT_HDL CORE DE HDL hier_write save hierarchy log reports summarizes Successfully saved block x while block was skipped
p/ s, Z! G% v8 g9 q" |2 I) T1142876 ALLEGRO_EDITOR SHAPE No DRC error when airgap between place bounds exactly zero
0 j2 Z+ C; m* K) C$ M' t ~1142884 ALLEGRO_EDITOR OTHER Boolean type user defined property doesn't export to the PDF
( |+ D' [7 N0 ^* c' X' c' ]1145112 CONCEPT_HDL CORE Warning message: Connectivity MIGHT have changed
- [" h& C4 M, l0 u( V \1145235 CONCEPT_HDL CONSTRAINT_MGR DEHDL CM gives error when trying to launch SigXP9 P( @6 v8 O9 ?3 i; P# X
1145253 CONCEPT_HDL CORE Component Browser adds properties in upper case- i. J) x- r, Z* `
1145284 CONCEPT_HDL CORE Publish PDF crashes DE HDL* I: e7 C6 _0 u s; f) u
1145333 ALLEGRO_EDITOR SHAPE SHAPE boundary may not cross itself. Error cannot be fixed.0 C# }2 \4 _' {% n
1145856 ALLEGRO_EDITOR DRC_CONSTR DRC Line to Thru Pin appear while Fillet be added
2 r; m+ d M' C8 D1146287 PCB_LIBRARIAN CORE PDV expand pins and change origin sets coordinates for few pins wrong and places pins on top of each other after collaps' d/ }$ _; o+ g& n
1146728 F2B PACKAGERXL DCF with upper and lower case values on parts causes pxl to fail
/ }$ `9 Y. ?5 P1147326 CONCEPT_HDL CORE HDL crashes when trying to reimport a block |
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发表于 2013-6-17 17:16
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