如果你是SI工程师，如何成为一个香饽饽

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How to become a hot commodity (if you're a signal integrity engineer)!

Suresh Subramanian, Cswitch Corp., and Panch Chandrasekaren, Xilinx Inc.

5/24/2006 5:37 PM EDT

These days, real estate isn't the only hot property in the San Jose Bay Area. While real estate prices make no sense, there is a very good reason why signal integrity (SI) engineers are well worth the premium. That worth has everything to do with their ability to effectively manage the simulation of high-speed systems.

SI engineers ensure first time success of very high speed systems (read fast edge rates) through the proper combination of theory, simulation, and measurements. Understanding the theory behind electrical phenomena – such as reflections on a transmission line – ensures an accurate baseline prediction of electrical interface performance. Simulations enable system-level design exploration prior to committing money and resources to manufacturing hardware prototypes – the most critical step in contemporary high-speed design. When done properly, measurements performed on prototypes provide the "proof in the pudding" that engineers seek. In other words, the "board bring-up/measurement process" validates the simulation methodology and system functionality.

Selecting a good simulation methodology is crucial when designing high-speed systems. Unfortunately, all simulation methodologies are not created equal. It falls to the SI engineer to select the proper approach by making trade-offs in terms of accuracy, complexity, resources, and time.

Data-dependent jitter
/ D1 A- Q6 B6 xSignal integrity challenges in designing wide data busses for high-speed memory interfaces (or any interface which supports large busses) pose a design problem that a good SI engineer can effectively address. Consider the classic setup (1) and hold (2) equations for a synchronous interface:

Most of these parameters are readily available from datasheets provided by the IC vendor. However, if the vendor's test load is significantly different from the system's operating environment, the value of the clock to output time (Tco) may have to be corrected to reflect the proper loading conditions. This is accurately, easily and quickly accomplished with simulation tools that work with IBIS driver/receiver models and can adequately model interconnect behavior [1]. These values can be populated into a timing spreadsheet to determine the overall timing margin.

Using such a spreadsheet, the skilled SI engineer will quickly point out that the analysis is incomplete and therefore will not guarantee a reliable system. Instead, the engineer would insist that the equations be rewritten as follows:

, [0 }) v' A) C3 X; o

Wide busses on a printed circuit board (PCB) constitute multi-conductor transmission lines which have more than one mode of propagation (especially when routed in close proximity to one other) [2]. Depending on the data patterns presented on the bus, these modes may influence trace impedance which, in turn, affects the propagation delay of the traces and causes data dependent jitter. If the impedance variation is very large and the transmission line is terminated in the nominal or characteristic impedance, even more jitter will result. The value Tcrosstalk therefore, is a function of the bus board layout. Simulation tools can help quantify these effects.

Consider, for example, a three bit-bus configuration routed in stripline (Fig 1) and the equivalent microstrip circuit (Fig 2). Trace impedances can be calculated by manipulating the stack up and trace width (using a built-in field solver) to achieve a 50- signaling environment. As expected, the nominal propagation delay for microstrip traces is faster than for stripline traces.

Jitter curves for the stripline configuration are shown in Fig 3. The middle curve corresponds to the nominal case in which the middle driver is switching high and the other two drivers are quiet. The leftmost curve results from an odd mode (010) switching pattern on the three bit bus, while the rightmost curve results from an even mode (111) pattern where all drivers are switching high simultaneously. Total jitter, measured at the mid point of the curves, is 83 ps. The equivalent curves for the microstrip configuration are shown in Fig 4. Here the total jitter is 121 ps; an increase of almost 50 percent over the stripline configuration!

Because the propagation delay for stripline traces is identical for all propagation modes, the jitter seen here is primarily due to mismatches in the termination resistor and the odd/even mode impedances. For the microstrip case, the jitter is a combination of differences in propagation speed for the two modes, as well as mismatched terminations. A good signal integrity engineer might mitigate the situation by increasing the spacing between traces.

Why should the even and odd mode impedances be different? Which is higher and which is lower? For the answer, consider Fig 5. The leftmost part of this figure shows the field solver output for the even mode case. Here the mutual capacitance is low and the inductance is high, resulting in higher impedance [Z = Square-Root(L/C)]. For the odd mode case, the inductance is low while the capacitance is high, resulting in lower Z. If these impedances are sufficiently larger or smaller than the nominal impedance, the mismatch in termination at the far end creates either a positive (overshoot) or negative (undershoot) reflection which combines with the incident wave to induce jitter. Similarly, the propagation delay (Tpd) is affected by changes in the values of L and C according to: Tpd = Square-Root(LC).

For the sake of brevity and illustrative purposes, only a three bit bus was used in this example. In reality, the number of bits to be considered in determining the magnitude of the data dependent jitter component of Tcrosstalk is a function of the routing density on the PCB.

SSO-induced jitter
3 O- t5 S p; _1 \% Y) ?; PThe SI engineer would also need to consider the empirical timing adjustment factor that accounts for timing 'push out' or 'pull in' seen when multiple bits change states at the same time (Tsso). This form of jitter is induced in the presence of multiple simultaneously switching outputs (SSO). In a poorly designed package, SSO (even mode or all switching in the same direction) will induce noise on the I/O supply rails; reducing the drive strength of the I/O circuits and resulting in timing 'push out' on signal nets. Similarly, SSO 'push in' can result when the victim output is switching in a direction opposite to all of the other outputs.

A good SI engineer will point out that these simulations are not as straightforward to set up as the previous example. The simulation methodology must involve transistor-level circuit models of the driver and receiver as well as accurate models of the package (whether based on S-parameters, RLC or some other format). Expert judgment on the part of the SI engineer is required in deciding what should go into the model while trading off complexity against accuracy. Intimacy with Electronic Design Automation (EDA) tools, in terms of their strengths and limitations, is also critical. The SI engineer may then utilize an effective approach to tackling this problem [3].

High-speed serial links3 Y+ ~0 K3 G; w6 M w0 r Q' b: ?
Today's FPGA devices, such as the Virtex 4FX, provide serial I/O speeds up to 10 Gbps. They come with a wide range of targeted features which can be employed in designing systems with multi-gigabit data rates. Careful signal integrity design is required for proper operation of these systems. Bandwidth limitations in the physical channel, caused by such things as frequency dependent losses, standing waves and mode conversion, can be overcome by selecting the appropriate level and mix of pre-emphasis, voltage swing and receive-side equalization.

Significant degradation of the data can occur after it passes through the transmission path. This degradation includes loss of signal amplitude, reduction of signal rise time and a spreading at the zero crossings. Therefore, it is critical to model the transmission path when designing a high-performance, high-speed serial interconnect system. A typical high-speed serial transmission path will include a Ball-Grid-Array (BGA) package, transmission lines, differential vias, and connectors. It becomes critical to model each piece so that the overall physical channel characteristics can be accurately modeled. An example of a differential pair model on the Xilinx Virtex series FF896 package extracted using 3D field solver based tools is shown in Fig 6. The associated insertion and return loss data of the example in Fig 6 is illustrated by the graph in Fig 7.

A model of a high-bandwidth differential via (GSSG configuration) is shown in Fig 8, while its associated insertion and return loss data is shown in Fig 9. Note that there are many degrees of freedom available to the SI engineer when designing the differential via: via diameter, antipad size, distance to the ground via, size of the ground via, and pad size. Existing EDA tools can be used to optimize these parameters for a desired bandwidth in a given application.

These individual pieces can be combined into a full-channel model. The SI engineer can then perform various what-if analyses to determine the optimal use of features such as pre-emphasis and equalization [4]. This step ensures adequate signal quality at the receiver.

These simulations can be computationally intensive as well as time consuming, especially if circuit simulators like SPICE are involved and thousands of bits must be simulated in order to generate eye diagrams. Both EDA vendors and industry practitioners are working on alternative methodologies, such as using IBIS 4.1/VHDL-AMS models for the drivers, which maintain accuracy while significantly reducing simulation run times. Very good correlation between simulation and measurements has been demonstrated using this approach [5].

Conclusion
* B$ D, x# X3 q" J. P; kThe preceding analysis offered a quick and limited survey of the domain of the SI engineer. They enable effective simulation through a nuanced understanding of the effects of each piece of the physical channel, either by itself or in the context of a bus, on overall system performance and reliability. Their expertise, coupled with the money invested in simulation tools and the time invested in simulation, are key to avoiding costly board respins while enjoying the advantages of faster time-to-market.

References

Hargin, B. (2004). For Synchronous Signals, Timing is Everything, XCELL Journal, Issue.49, 2004.
Schmiit, M, et al., (2004). Simultaneous Switching Noise Analysis for Full-Chip Power Integrity Sign-Off. EPEP 2004 Proceedings.
Thierauf, S,C.,(2004). High Speed Circuit Board Signal Integrity. Artech Press.
Subramaniam, S., & Murphy, L(2005). 10 Gigabit Channel Virtual Design Kit. DesignCon 2005.
Huq, et al., (2005). Multi-Gigabit SerDes System Level Analysis using IBIS v4.1/VHDL-AMS, Mentor User2User Conference, Santa Clara.

Panch Chandrasekaran is marketing manager for Xilinx (www.xilinx.com) high-speed connectivity solutions. Panch's background is in analog and mixed-signal design of 2.5 Gbps and 10 Gbps transceiver chips for telecom applications. He has also held high-speed application engineering positions dealing with multi-gigabit signaling and signal integrity. Panch has a MSEE from University of Central Florida.

Suresh Subramaniam is a Member of Technical Staff at CSwitch Corporation (www.cswitch.com) where he is currently involved in package design and signal integrity simulations. Piror to that he spent more than seven years at Xilinx in various roles ranging from FPGA performance characterization, and signal integrity modeling and design of a number of high speed reference boards (10 Gbps transceivers). He earned his Ph.D in Computational and Cognitive Neurosciences and his MS in Electrical Engineering (VLSI) from the University of Southern California, Los Angeles.