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本帖最后由 dsws 于 2014-4-28 12:56 编辑
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& M: [& z4 n1 \) y3 c链接: http://pan.baidu.com/s/1dD9XLPB 密码: ujuq
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~- H5 S5 u# fDATE: 04-25-2014 HOTFIX VERSION: 027
* k. v" p- _ N& d$ P: x===================================================================================================================================
, ^; g( v5 R0 _) g* ^& aCCRID PRODUCT PRODUCTLEVEL2 TITLE
{6 H4 Y4 t& S3 S===================================================================================================================================- l/ g) u4 j. r
308701 CONSTRAINT_MGR OTHER Needs to delete user defined schedule in CM9 j" v" H' `& L$ S% i% {
481674 ALLEGRO_EDITOR PADS_IN No board file saved from PADS_in1 _& t" W$ e {. Z6 B1 `; u' [
982929 ALLEGRO_EDITOR EDIT_ETCH can't route on NC pin and other that are not pin.
# h' l+ j4 m5 K- {1012783 FSP OTHER Need Undo Command in FSP
! e0 P, E3 G1 a5 h( m1017381 ALLEGRO_EDITOR DRC_CONSTR Need Dynamic Phase to be able to measure back to the Drive Pins.1 r6 H$ ]6 z5 j4 E
1072673 PCB_LIBRARIAN GRAPHICAL_EDITOR Copy paste goes offgrid if mouse is moved* x+ D) T7 F, Z6 c4 P" F* [5 A* S
1073231 CONCEPT_HDL CORE Copy-paste of signal names goes off-grid in Windows mode.
: b3 v- o. a+ _% c$ C7 w' O1105371 CONCEPT_HDL INTERFACE_DESIGN Strange behavior when shorting two Net groups @5 o1 J" i7 Q; k: W
1116498 CIS LINK_DATABASE_PA link database with modified part results in Capture crash
" p( G" p# I8 P/ Q1118632 ALLEGRO_EDITOR GRAPHICS Text display refresh issue while in Edit > text command
Q0 j% Y3 o9 k/ E- k! R9 n- H1155821 SIG_INTEGRITY LIBRARY Xnet are not recalculated correctly when model is changed on the Series switch part defined as discrete with Espice mode: J+ f' u6 d# W# L, i9 h
1157372 ALLEGRO_EDITOR DRC_CONSTR Dynamic phase for Diff Pairs not reporting back to Driver pin if pin escapes present
9 t$ t( V( _, i+ i2 o9 m1171951 ALLEGRO_EDITOR CREATE_SYM Jumper has a limited of count when it add to list.* F1 P" D5 J4 G' B! T s" L
1180871 CAPTURE LIBRARY_EDITOR Copied parts don't retain pin name and pin number settings% v, J6 _& g, y% e& o' r
1185575 SIP_LAYOUT DIE_STACK_EDITOR Updating symbols causes the graphics for the Assy layer to change from Bottom to Top.2 h2 w' M0 l+ L
1185772 PCB_LIBRARIAN CORE VALID_PACK_TYPE warning when cell was opened in PDV& H" @0 p7 e+ i. f- P+ Q! a
1192377 CAPTURE SCHEMATIC_EDITOR Pin name/number position is incorrect on schematic if it is changed for a rotated part.
& S$ D$ X/ v" k; A( X& h1202654 ALLEGRO_EDITOR GRAPHICS Zoom using mouse wheel shall maintain the center co-ordinates8 H) q: m' y/ W/ E" [
1208031 ALLEGRO_EDITOR INTERACTIV Snap to Pin for via during Copy command do not snap to connect point everytime5 M" g) V, Q1 r
1208478 PSPICE PROBE Attached project gives overflow error with marching ON.' ^/ w" c3 G' O: k
1210015 CONCEPT_HDL CORE The value of $PN should be not turned on spin or rotate symbol) L% ?6 {9 b, v$ A/ P
1210425 CONCEPT_HDL CORE When moving a circuit tool reports that connectivity has changed
& @3 |: ~% o0 U7 P: N7 x9 ]3 V1215858 ALLEGRO_EDITOR SHAPE Force update does not void cline with the shape
( `' l: [$ P/ Y: V+ Z3 J4 [( Z% ?6 V1215906 ALLEGRO_EDITOR SHAPE Dynamic shape fill smooth failed when copying to other layers$ G* ?( Z8 K+ I; d$ Z. p' d/ Y" l+ q" B
1216358 CONCEPT_HDL CORE Can we improve our export BOM function to check if user did export physical function before exporting BOM?
: K0 K( R' L# c# ]9 J" p1 q8 W1217364 CONCEPT_HDL OTHER Netlist reports fail because error: GScald failed., _* [3 n! R- F8 f, g1 U6 ?
1217529 CONCEPT_HDL CORE ADW checks do not catch single quotes in PTF values
5 k& ~4 A& f k! w) M6 e4 l1 V4 W1217556 F2B PACKAGERXL signal name change not sent to Allegro after packaging, s' J. J1 _- j4 N: a$ d. {
1219283 ALLEGRO_EDITOR DRC_CONSTR Show constraint is inconsistent when displaying region information
- w G' q% h" ^1220078 F2B PACKAGERXL Export Physical crashes when ALL the part pins are added
/ ~& V% W( Q; X- A1220393 CONSTRAINT_MGR CONCEPT_HDL HDL import physical from board file will annotate CM data back to HDL which includes cross-section thickness.2 W: ^9 q: _# K
1220540 ALLEGRO_EDITOR GRAPHICS Need an option to see the pads inside the internal plane shapes+ ~' U Q: ?- v) P C
1220936 CONCEPT_HDL CORE About crash by vpadd/vpdelete command on Linux7 H3 A( C# y5 ], ?" _* B' N' h
1221059 ALLEGRO_EDITOR DRC_CONSTR Get a "Shape to Thru Via Spacing" DRC error only the first time when the shape is manually voided.
! { n4 P& s; N1221182 ADW TDA Team Design with SAMBA4 }& P& ]7 b0 `
1222442 CONSTRAINT_MGR UI_FORMS Duplicate pin pairs appear in DiffPair, n5 b7 B$ r4 Y5 j, w m
1223175 CONCEPT_HDL CONSTRAINT_MGR Schematic crashes when opened
E$ @$ `) N V" L# F1223533 ALLEGRO_EDITOR GRAPHICS Why the through pins for STEP models are shown at an offset when viewed in 3D inside Package Symbol?
! f) ^! d2 o( Q) M. c1223680 CONSTRAINT_MGR ECS_APPLY Improve ECSet mapping by allowing user to address ambiguity of Parts
' ~1 L" F; A: g' S' J1224156 SIG_INTEGRITY SIGWAVE Exporting spreadsheet with filter Subitems in SigWave exports all waveforms
. n. u& r" I f1 I" Y1224417 ALLEGRO_EDITOR PLOTTING Hidden font pattern is not showing correct in 16.5 version also 16.6 version.
5 A# A3 f- r$ b5 g% f; k- h1224704 F2B DESIGNVARI There is no lock for the variant.dat file - multiple users can open the editor
. B! E1 P7 S# s1 [1224968 ALLEGRO_EDITOR INTERACTIV Delete >(RMB click) Cut> Snap Pick to>off grid loction does not work for lines.* S/ |/ W V$ e9 l# J5 N- J( _
1224982 CONCEPT_HDL PDF commandline publishpdf does not work when there are spaces in the path
' ?) x5 W% b. a" M, B* Y1225114 CAPTURE GENERAL H-pins added after netgroup pin get color as of netgroup pin7 @/ N8 Y8 A- Q0 y
1225494 CAPTURE DRC Different DRC results for Entire design and selection. `2 q- T! Z! V% U" U, S
1226153 ALLEGRO_EDITOR INTERFACES Export STEP should include PART_NUMBER property
! b, W- c/ l0 P9 V) f/ V% ?1 q1226235 ALLEGRO_EDITOR EDIT_ETCH Enhancement to include Pin_delay of descrete forming Xnet ?% d* O4 C* l4 {( U2 n* B/ }0 |) P
1226372 CAPTURE GENERATE_PART ENH: Functionality to add pin spacing in New Part From Spreadsheet
6 Z [+ N* M8 C2 H* y& d1226477 CONCEPT_HDL CORE DE HDL縮 `Allowed Global Shorts? function is inconvenient for Global Signal2 W1 r# }+ t1 t, z
1226813 SIP_LAYOUT LEFDEF_IF ERROR SPMHLD-120 when importing a DEF file. Request to increase the number of characters/line in a .cml file
0 Q( o0 U4 V v( ?7 x; E' s8 x1227453 ALLEGRO_EDITOR SHAPE Addition of Fillet generate Pin to Shape Spacing DRC errors and DBDOCTOR errors3 g$ q& g# z0 L& ?% h, ~5 `
1227461 ALLEGRO_EDITOR SHAPE Sliding a cline for certain net changes the thermal relief connects for pins connected to another net from 4 to 5,6,7,8
7 d9 R6 Y# Q2 c2 t/ D1227469 CIS DBC_CFG_WIZARD Oracle Views not visible on Step2 of CIS Configuration! R9 M4 D+ |" c/ I( j* b/ t
1227780 CAPTURE ANNOTATE Inconsistent behaviour when annotating heterogeneous part3 c6 O+ e0 t+ a% v( i
1227831 CONCEPT_HDL CORE Pin text and H-block name in upper case
3 ]8 L' J9 L; [% Q0 q* M! b0 Y1227954 CONCEPT_HDL OTHER supress check for global signals when wires are unconnected to pins6 k8 Y4 A5 a' p4 f8 L1 _
1228190 ALLEGRO_EDITOR OTHER Unable to close the 'usage' window during license selection
9 _3 G5 _; Y$ m: {* O# `% e, ]8 R1228899 CONSTRAINT_MGR INTERACTIV Export/Import constraints in "overwrite" mode from same design shows different results when imported second time.
3 Q0 [- N( d( @: z; ]& z1228934 ALLEGRO_EDITOR EDIT_ETCH The "View Active Layer" option like the Board Station should be provided for dynamic layer visibility.7 F% z3 F @. f6 Y, g; }! s9 M
1229316 ALLEGRO_EDITOR EDIT_ETCH When routing with Hug only enabled we were able to route through other routes(sometimes Hug).) e3 d+ O# L- e( Y5 `- @2 o
1229545 CONSTRAINT_MGR OTHER Allegro indicate bundle scheduled nets in CM2 d" i( [# e6 \! y# L7 V
1230056 ALLEGRO_EDITOR GRAPHICS Bug: 3D View of Mechanical Symbol with the drill hole defined
, K) A% z1 ^6 v1230432 CONCEPT_HDL CORE No Description information in BOM
+ U1 w* v- g( l V5 o1231148 F2B DESIGNVARI The variant.dat file is not updated with library PTF changes6 v! F! u% L) `6 k" o0 z9 U& q6 K
1231625 F2B DESIGNSYNC VDD at command line needs to support sch2sch and test variable to write out report files4 A& s6 G* v7 c
1231697 CONCEPT_HDL CORE If any locked files exist force a pop-up dialog restricting certain commands
5 I2 ]; M' i( v2 G, d* c A1231767 CONCEPT_HDL OTHER Unable to find under the search options single bit vector nets
, B$ _/ b& X- s e( h5 K0 T) N1231961 ALLEGRO_EDITOR SHAPE Shapes not updating to smooth unless we use force update and as a result false DRC's appear in board.+ V. _* n5 C4 c; U
1232100 CONCEPT_HDL SKILL Unable to execute the SKILL commands in viewer mode
# i [& v7 q! }. k* {3 A1232336 CONSTRAINT_MGR CONCEPT_HDL cmFeedback takes 5hrs to complete during Import Physical
" [! ~8 g( V; J" ^ B2 ~1232710 F2B DESIGNVARI Dehdl crash while moving component in variant viewer mode p: g7 o( b; _* J( S
1233894 F2B PACKAGERXL The page data is missing in the pst* and PCB files9 {9 {" _* k1 I( l2 u& {
1235785 CONCEPT_HDL CREFER cref_from_list custom text is not subsitituted in complex hierarchy, s, V! Z- D; k X' x7 |) q
1235928 CAPTURE SCHEMATIC_EDITOR OleObject modifications not saved
9 ~( d7 P: }/ S4 p1 @1236065 CAPTURE PART_EDITOR Mirrored part after being edited get pin name locations incorrect
5 \+ D' m A% z& J& C& Q6 J1236071 ALLEGRO_EDITOR SHAPE Airgap for Octagonal Pads ignores DRC Value when Thermal set
) E' u% N* X' }. q& h0 ?1236072 CONCEPT_HDL CORE Page 122 cannot be saved as logical page 119 has different page mapping in connectivity data and schematic9 @0 s' m6 f. c& G5 N, Z* ]; B; M
1236161 CONCEPT_HDL CORE Import Design shows the current project pages6 ^( K0 n9 J( Y4 d0 c; b1 z
1236432 ALLEGRO_EDITOR PADS_IN pads_in doesnot translate via and shape in some instances.3 {- j7 _8 w2 o# {" O" d& u# d
1236557 CONCEPT_HDL PDF Running Publish PDF on command line in linux doesn't output progress until completion/ W1 a% \' z+ ^; G0 D( _$ f' ^
1236589 CONCEPT_HDL PDF Enhancement license failure error should appear in pdfpuplisher log file
- V2 E8 M1 F# F" Y1236644 ALLEGRO_EDITOR EDIT_ETCH create fanout deletes shape
) c8 N# E7 X* L) W% Z- A1236689 ALLEGRO_EDITOR GRAPHICS Graphics displays extraneous lines when panning or zooming- o8 V* v! w2 f* n8 [1 u, b1 V
1236781 F2B PACKAGERXL Export Physical produces empty files I& X" U% Y& I! b' y( }( [
1237331 PSPICE ENVIRONMENT pspice.exe <cir file name> - hangs when run
9 L: j1 n% j( U, \1237400 CIS EXPLORER Capture hangs on 2 consecutive runs of `refresh symbol from lib? command
" ]* J' q4 }! E1237437 CONCEPT_HDL CONSTRAINT_MGR CM Crash when saving after restore from definition
; @, ?8 r& y" F* G F j1237862 CONSTRAINT_MGR OTHER A way to remove the RAVEL markers from the Constraint Manager.3 b+ Y9 K0 Q; P; Q0 Z" `
1238852 CAPTURE GENERAL signal list not updated for buses
0 {2 a. D1 W! s0 ]1238856 FSP DE-HDL_SCHEMATIC FSP schematic generation crashes& {3 E7 |" W" I6 Q# c ^
1239079 ALLEGRO_EDITOR INTERACTIV The 16.6 Padstack > Replace function leaves old padstack.& ~: Z" A- u) M* p7 k
1239706 CONSTRAINT_MGR ANALYSIS The reflection result on a differential signal in the CM when Measurement location is DIE2 ^8 o: {2 q5 z5 N8 }/ `8 `6 J
1239763 PSPICE PROBE Cannot modify text label if right y axis is active
+ y1 u7 G+ b/ G5 f& ~& G3 j! e+ e1240276 ALLEGRO_EDITOR GRAPHICS Printing to PDF from SigXp is giving unreadable images* ~2 @/ m8 M |3 D7 a
1240356 CAPTURE IMPORT/EXPORT Can縯 import SDT schematic to Capture.5 C! ?, T5 v6 I0 y
1240502 F2B PACKAGERXL Corrupt cfg_package does not stop PackagerXL from completing
% y/ H2 E: t1 ~1240607 ALLEGRO_EDITOR OTHER Footprint of screw hole got shift in DXF file
5 f- s. {4 a0 J. R& E" \' E, z5 b4 n1240670 ALLEGRO_EDITOR PLACEMENT Select multiple parts and Rotate makes them immovable! E7 W2 c5 ^4 b8 W0 m
1240773 CAPTURE DRC DRC check reports error for duplicate NetGroup Reference in complex hierarchy
+ o3 _/ S+ z# b- F. c& h C0 Y! l1240845 SIG_EXPLORER EXTRACTTOP Narrowband via models for Mirrored BB Vias not extracted in in the interconn.iml and this gives bad ringing in waveforms/ b( z, r* D0 T. S8 ^. I& J0 X
1241634 ALLEGRO_EDITOR OTHER Netshort for pad-pad connect not working
) {$ E" d" S% j' u1241776 CONCEPT_HDL CORE In hierarchal design not all pages are getting printed.
3 S+ r3 ^: H& J) p+ O6 i' v( R1241788 CONSTRAINT_MGR CONCEPT_HDL Issues with changing focus in Constraint manager using keys on keyboard
" W1 p" H2 J9 N2 v1242683 ALLEGRO_EDITOR INTERACTIV Color View Save replaces file without warning
% I" l& @, u( b4 _ ^8 l1242818 ALLEGRO_EDITOR PLACEMENT Placement edit mirror option places component on wrong side# G0 S' _. }2 G: N p
1242847 ALLEGRO_EDITOR GRAPHICS Need an option to suppress Via Holes in 3D Viewer1 N6 Y% m* m$ }0 M: P
1242923 ADW COMPONENT_BROWSE UCB reports Missing From DB only after selecting the Row in the search results$ _+ C; L+ q% g2 P4 G6 V+ V, }
1243609 CONCEPT_HDL CORE autoprop for occurrence properties! D& @$ H; d% o; F9 l! E
1243682 F2B DESIGNVARI after undocking variant icon cannot be redocked back to GUI
' \: {8 a1 ^. y [1243686 ALLEGRO_EDITOR GRAPHICS Invoking Edit->Text, the infinite cursor disappears until edit mode is changed.
1 l, w' s, P5 v8 { P) T5 V1243715 CAPTURE PART_EDITOR Pin name positioning get changed after rotating or mirroring$ C. ?& U9 S. P( M% p
1244945 CONCEPT_HDL PDF PDF Publisher does not include image when file is not located in the root folder
- ~2 p. y: z1 {% u6 W1245568 CONCEPT_HDL CORE Dual unselect needed for wires attached to other net/source and property is not deselected when component is
- V/ ^3 m& s' C. D- J, J6 M1245819 F2B PACKAGERXL wrong injected properties information passed during packaging of the design
8 Z* B/ L; e: o4 n) U8 i1245916 SCM CONCEPT_IMPORT Where does the folder location reside for DEHDL imported blocks?" g3 y2 Z5 c" r* [
1246347 CONSTRAINT_MGR CONCEPT_HDL DEHDL crash if environment variable path has trailing backslash character' V; s8 V0 X5 O2 [' H9 j+ o
1246896 ALLEGRO_EDITOR DFA DFA_UPDATE on Linux reports err message if the path has Upper case characters' h4 D' a( P! l O' O. }
1247019 SIP_LAYOUT DIE_STACK_EDITOR SiP Layout - refresh/update symbols is mirroring the assembly drawing data on DIE that is placed ChipDown
' C2 c1 D* @4 V" d1247037 CAPTURE LIBRARY_EDITOR Copy & Paste of library parts resets pin name and number- R, A7 I0 [5 N0 y9 C
1247089 CONCEPT_HDL CORE Group Align or Distribute > Left/Center/Right crashes DEHDL
, p' O5 S0 [* P/ e& V" F( z1247163 CONCEPT_HDL PDF Physical Net Names in PDF not maintained+ t( S) ?4 u' L' _( \: a
1247462 CONCEPT_HDL CORE Text issue while moving with bounding box7 K5 v- Q7 o9 C3 _- H2 z
1247464 ALLEGRO_EDITOR UI_FORMS When using the define B/B via UI the end layer dropdown arrow is partially covered
1 {5 { b& \0 j6 o* [7 `8 o8 E1249063 CONCEPT_HDL CONSTRAINT_MGR CM and SigXP doesn縯 respect PACK_IGNORE at components
0 ]) B$ Z3 K+ `1250270 CONCEPT_HDL CORE Part Manager Update places wrong parts
: s) {8 F, @& v8 U' W K1251206 ALLEGRO_EDITOR ARTWORK Aperture command cannot create appropriate aperture automatically from design.$ x1 q7 n) c# [ J* U2 x& Q
1251356 ALLEGRO_EDITOR INTERFACES Some STEP models are missing in 3D view of footprint, although all components have STEP model mapped in footprint
! Q% I. I+ G2 s/ e1251845 ALLEGRO_EDITOR EXTRACT Crosshatch arcs do not extract correctly) L# H: m+ J/ [" |9 @* s! X
1252143 APD OTHER When using the beta "shape to cline" command the tool is removing the shape instead of converting it.
- ^5 ?, a4 m7 D+ i/ Z, t% k1 c* C1252737 SIP_LAYOUT OTHER SiP Layout - Option to create shapes from Pins for WLP wafer level packaging technologies! R- u+ M" {; C. l
1253424 SCM SCHGEN Export Schematics Crashes System Architect, b) |; n8 k2 k6 I9 ^( s, W4 Q2 n
1253508 ALLEGRO_EDITOR INTERFACES Bug - Export IPC2581 exports Crosshatch shapes as filled4 ~7 n# N7 @! B6 ]! ]
1253554 SIP_LAYOUT OTHER SiP Layout - Add Netlist Spreadsheet export to SiP layout to help with connectivity auditing
+ | N3 C' I& ^: a1254578 SPIF OTHER Specctra crash with Error -1073741819 for Auto router7 L' H2 y5 e9 q5 a; z; }. z
1254637 ALLEGRO_EDITOR DRC_TIMING_CHK adding nets to a net group causes constraint assignment error3 u, ~ O3 Y& W' }+ @
1254676 GRE IFP_INTERACTIVE Rake Lines disappear when Auto-Interactive Breakout is enabled.
+ k' o- h. ~+ _. J& `( i x' _+ N) `1255067 SIG_INTEGRITY REPORTS Allegro hangs on Net Parasitc Report generation
/ {# D9 o' V! v% ^1255267 ALLEGRO_EDITOR SKILL axlDBGetPropDictEntry does not return a list of all objects
+ ^. ]% ^9 F' R% A- [ F1255383 SIP_LAYOUT IC_IO_EDITING cant move bumps or driver in app mode
% j0 ^3 Y1 E1 K! _1 _1255703 ALLEGRO_EDITOR SKILL axlCNSSetPhysical and axlCNSGetPhysical return nil if a constraint set name is provided8 h+ ^2 ^# ?; { w4 [
1255759 ALLEGRO_EDITOR INTERFACES Change the silkscreen OUTLINE from layerFunction DOCUMENT to layerFunction BOARD_OUTLINE9 T1 a8 ]+ C9 R% b/ l% H$ G
1256457 CONCEPT_HDL CONSTRAINT_MGR Extracting a XNet from CM crashes the tool0 t' M; u% ?" G) n0 J* [- c
1256597 GRE CORE Allegro GRE crashes while running Plan Spatial, on a particular design
, I8 V4 t W" m1256650 ASI_PI GUI PFE - Cannot generate model file error when using company decap library0 Z' S5 D" D, \4 d( G \3 o$ H
1256837 SIP_LAYOUT DIE_EDITOR Open and close of die editor takes too long
9 I, R0 x ^( o: b% \& W- Q1257732 CONSTRAINT_MGR OTHER Bug - Export Analysis Results in CM makes Allegro crash6 X, Y t( t" q
1257755 ALLEGRO_EDITOR OTHER Editing time in Display > Status seems to be logging wrong time
( o ~0 P; _# p$ ?5 H( e2 [1258029 APD WIREBOND The bondwire lost after import the wire information
, s$ M' I( s* S3 d! Y+ F7 v" R! n1258979 APD NC NC Drill: There is difference of number of drills.
5 x& h8 I3 g1 |4 J& b: p @# f1259484 SIP_LAYOUT OTHER SiP - calc min airgap calculate minimum airgap beta feature improvement& f h$ r) C- F6 w, f. [( M* p
1259677 CONCEPT_HDL CORE hier_write -forcereset cause component prop change.
( k9 B% p0 X" ^6 _7 @! R) Y1259913 ALLEGRO_EDITOR UI_FORMS Unable to save setting of "use secondary step models in 3D viewer"
) S4 X) N4 J) i \' k6 X1261758 ALLEGRO_EDITOR EDIT_ETCH Auto Interactive Delay tune (AiDT) is deleting clines
, l4 P8 Q- R7 H, Y# k4 |1262543 ALLEGRO_EDITOR MANUFACT merge shape results in moved void/ j" L4 W9 x( M5 m5 C
1264767 ALLEGRO_EDITOR DRC_TIMING_CHK XNET is choosing to resolve to a different name from 16.5 to 16.6 and is causing constraint loss
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发表于 2014-4-26 15:14
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