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Layout Guidelines and Topology:
1 J3 ~. f P, c6 {0 ?4 l$ QThe following are the routing guidelines followed for DDR memory interface section:( O+ R4 E, J4 x0 N1 j
1. Controlled impedance for single ended trace is Z0 = 60 ohm.
4 w& X' i9 J: Q; q! @$ D* j9 F# [2. DQ, strobe, and clock signals are referenced to VSS.# O6 S: h4 q# t
3. Address, command, and control signals are referenced to VDD.8 ^+ T' [* r& f+ p+ P6 }5 a
4. The length of address, command, and control signals are matched to clock with +/- 100 mil+ A% r3 Q) K9 ?0 M5 D
tolerance.
/ Y5 h5 k- b& Z5. DQ <0..7> & DM signals are length matched with respect to DQS with +/- 100 mil tolerance
3 V, S7 E/ r1 c; U0 t' R(byte lane).+ f, S9 `; t) U5 X4 m& z! o
6. Each byte lanes are routed on same layer.
# E5 \4 z9 r& ~. d2 m8 {% q7. Byte lane to byte lane is matched to clock with +/- 500 mils.
' ^4 ?4 l' v) |0 w8. CK & CK# are matched with +/- 30 mil and are routed as diff pair with 120 ohm differential# c$ o+ u- q* T
impedance.2 ~9 T8 n+ G% q3 M$ [ O( I
9. Clock - pair to pair matching tolerance is +/- 30 mil.6 F: A. [& @6 b5 h: q7 F6 A
10. Trace to trace spacing is 2X and signal group to group spacing is 3X.( P1 {- Y* Q0 s, H! N
11. DQS signals are routed in the middle of the byte lane (DQ<0..7>)." y9 w) U/ `( N |1 M( b
12. Clock trace split point to DRAM is less than 1 inch.
! {8 @+ K4 ^- S" c7 Q9 P! y13. VTT and VREF islands are separated with the minimum spacing of 150mils.7 B" \9 N7 f6 z% b, _9 t# I
14. VTT island width = 150 mil min.; 250 mil preferred.. N+ Y) {/ ]. }! ^! V
15. VREF signal is routed with 20–25 mil minimum trace." j4 ?, }, ]" f) z; h) y
15. All signals are routed with minimum of 3X spacing between other signals6 A9 g9 R7 B( H6 }5 S8 t
16. Layer biasing is followed for dual strip layers.. F* E+ _% z+ K2 k! k- Y( x
Figure 1 shows the data bus topology and figure 2 shows the address/control bus topology. |
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发表于 2009-8-1 13:54
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发表于 2011-9-16 14:27
发表于 2011-9-19 10:13
