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我最近在看中国电力出版社出版的FPGA嵌入式系统设计与开发指南这本书，下面的代码是本书的第第一章的第三段代码，我使用QII 11.0WEB版本无论如何无法正确编译，总是提示10559错误，请各位高手帮我看下问题所在，谢谢！8 ^6 \3 S" D7 W1 Z
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library ieee;
) U# Q# d4 n6 x, s2 cuse ieee.std_logic_1164.all;( J4 A1 e k5 F+ J
use ieee.std_logic_unsigned.all;
* x& Z! X6 w" d4 R8 H- ~0 q5 Y) ~entity counter8bit is
$ q: f0 D! e. P2 z8 X port(int ,reset,enable: in std_logic;count_out: out std_logic_vector(7 to 0));
( \/ E% A+ _. E( H& c- N# t7 p M end counter8bit;
0 W) b6 p# [ ?0 u architecture counter of counter8bit is1 F* c/ t F0 X0 q" N, R; z; v
signal count_in: std_logic_vector( 0 to 7);
+ Z5 h6 b) x5 t& v begin& \: ]+ f3 h3 t3 c ?( b
process(input,reset)
6 c8 [% _0 E- } C begin
) D1 g1 y4 D8 g wait until rising_edge(input);/ q) l7 w; d/ \- [2 |% u2 M
if reset='1' then* X) S5 G3 D% l% }% z8 }% s
count_in<=(others =>'0');
$ a' y7 t! U+ E8 F" V elsif enable= '1' then
S' n' P5 B# R! W1 E- I if (count_in="11111110") then 1 n" ^$ z* ~# H: Y* K
count_in<="00000000"; d! o' y6 b/ X$ b+ e/ T" Q6 X
else
# R$ z1 H2 G( t count_in<=count_in+1;. g$ n( q" q8 x6 B# Q5 U/ r
end if;* ~0 Z4 Y3 N+ c# e$ }
end if;
& _& y& Y; c3 {* f end process; w2 z0 Y+ \! Z) v& ?2 _8 L
end counter;
8 U) d( I' U( P* l + ^) i/ D2 N; [6 S
" a" }: ^1 D5 Z7 Z N g( h7 ]! p
lInfo: *******************************************************************
) r# j% E' E8 k& [Info: Running Quartus II Create Symbol File
4 D% B1 d' J. I+ W6 j a Info: Version 11.0 Build 157 04/27/2011 SJ Web Edition! U1 ^9 |% U6 m6 L- c" {3 ?5 d! c
Info: Processing started: Wed Jul 24 14:43:41 2013% v8 I8 i$ U& L7 x% h# _7 m
Info: Version 11.0 Build 157 04/27/2011 SJ Web Edition
( V x9 q1 E1 i Info: Processing started: Wed Jul 24 14:43:41 2013
; q) |# h7 g! p0 }$ Z! P$ P1 g! lInfo: Command: quartus_map --read_settings_files=on --write_settings_files=off penlvji -c penlvji --generate_
& f4 \3 N+ j! O* x/ e aError (10482): VHDL error at counter8bit.vhd(12): object "input" is used but not declared9 q7 ^1 o1 L: s; e
Error (10559): VHDL Subprogram Call error at counter8bit.vhd(12): actual for formal parameter "s" must be a "signal"9 x1 p5 r4 L- p* i. M0 d1 h; M
Error (10482): VHDL error at counter8bit.vhd(10): object "input" is used but not declared* W" r$ x6 ]' O! {9 U: f5 }. c
Error: Quartus II Create Symbol File was unsuccessful. 3 errors, 0 warnings( O. Z4 g+ n- M* i" G
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发表于 2013-7-24 15:01
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