PCB 导入网表出错，但是又不知道是什么错误...

xiaoyunvsmm · 发表于 2012-12-14 07:38

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错误信息显示如下。。。求大神帮我解释一下。。万分感谢~~

(---------------------------------------------------------------------)+ ^/ `. f2 u4 \$ h
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( Netrev Allegro Import Logic )
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( Drawing : SDX_Allegro.brd )
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( Software Version : 16.3p004 )
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( Date/Time : Fri Dec 14 07:39:06 2012 )
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(---------------------------------------------------------------------)
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------ Directives ------4 o, _: u; r* s. C9 c- y
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RIPUP_ETCH FALSE;
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RIPUP_SYMBOLS ALWAYS;& N' y) S6 r$ J; [$ K# L- T
Missing symbol has error FALSE;
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SCHEMATIC_DIRECTORY 'D:/SPB_Data/SDX_ALLEGRO/SDX_ALLEGRO';$ w8 A: U* h/ w
BOARD_DIRECTORY '';
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OLD_BOARD_NAME 'D:/SPB_Data/SDX_ALLEGRO/SDX_ALLEGRO/SDX_Allegro.brd';
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NEW_BOARD_NAME 'D:/SPB_Data/SDX_ALLEGRO/SDX_ALLEGRO/SDX_Allegro.brd';1 J% Y+ P3 l; |9 B" n% n
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CmdLine: netrev -$ -i D:/SPB_Data/SDX_ALLEGRO/SDX_ALLEGRO -y 1 D:/SPB_Data/SDX_ALLEGRO/SDX_ALLEGRO/#Taaaaaa05284.tmp
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------ Preparing to read pst files ------) s X2 ?5 ?5 q- {, G8 c; H
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#1 ERROR(24) File not found3 ~; C( O6 l; H
Packager files not found# F2 p+ E0 u' P* M- F9 \! i; m
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#2 ERROR(102) Run stopped because errors were detected u8 j; r2 V+ V7 z; p* d" P# F
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netrev run on Dec 14 7:39:06 2012+ G- _! r6 Z G ^9 Q0 G; u' s( i
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COMPILE 'logic'
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CHECK_PIN_NAMES OFF) L$ E7 n$ E! e+ |- m7 V
CROSS_REFERENCE OFF
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FEEDBACK OFF
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INCREMENTAL OFF
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INTERFACE_TYPE PHYSICAL
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MAX_ERRORS 500. {1 I$ f X8 ^% r2 a; y$ ~
MERGE_MINIMUM 5
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NET_NAME_CHARS '#%&()*+-./:=>?@[]^_`|'2 r4 w6 V- e7 D" W1 p1 f
NET_NAME_LENGTH 24
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OVERSIGHTS ON
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REPLACE_CHECK OFF" J R5 S% ^' _1 n; J8 @
SINGLE_NODE_NETS ON
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SPLIT_MINIMUM 0
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SUPPRESS 20, \% h( G/ d5 l M# u7 [5 u1 ~
WARNINGS ON$ D6 {# c" u* w% _, r7 R+ H
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2 errors detected M; w4 M8 p5 i# k, O# w
No oversight detected; [8 N' I$ K4 P$ m
No warning detected
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cpu time 0:00:46/ B: h# Y( ]2 R+ z; S( C! }
elapsed time 0:00:00