PCB 导入网表出错，但是又不知道是什么错误...

xiaoyunvsmm · 发表于 2012-12-14 07:38

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错误信息显示如下。。。求大神帮我解释一下。。万分感谢~~

(---------------------------------------------------------------------)1 _' S/ f/ o* X0 n, g
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( Netrev Allegro Import Logic )
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( Drawing : SDX_Allegro.brd )8 V$ E# N+ ]2 T
( Software Version : 16.3p004 )5 m7 F# F' T; g; I% ?3 t. d
( Date/Time : Fri Dec 14 07:39:06 2012 )' n- a$ n$ z; ^+ |# }
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(---------------------------------------------------------------------)
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------ Directives ------
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RIPUP_ETCH FALSE;
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RIPUP_SYMBOLS ALWAYS;4 Y* Z+ H! {# [1 B" @! ^
Missing symbol has error FALSE;
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SCHEMATIC_DIRECTORY 'D:/SPB_Data/SDX_ALLEGRO/SDX_ALLEGRO';$ m8 e2 b7 p$ ~
BOARD_DIRECTORY '';
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OLD_BOARD_NAME 'D:/SPB_Data/SDX_ALLEGRO/SDX_ALLEGRO/SDX_Allegro.brd';
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NEW_BOARD_NAME 'D:/SPB_Data/SDX_ALLEGRO/SDX_ALLEGRO/SDX_Allegro.brd';" k1 s5 S2 T$ F3 h1 U8 A
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CmdLine: netrev -$ -i D:/SPB_Data/SDX_ALLEGRO/SDX_ALLEGRO -y 1 D:/SPB_Data/SDX_ALLEGRO/SDX_ALLEGRO/#Taaaaaa05284.tmp
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------ Preparing to read pst files ------
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#1 ERROR(24) File not found, q$ ^2 W8 b2 t' e* i
Packager files not found
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#2 ERROR(102) Run stopped because errors were detected+ B1 _ }1 ?3 T3 u' G+ K4 f' ^
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netrev run on Dec 14 7:39:06 2012' I3 G% X" L1 _6 o( J. |% I* q
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COMPILE 'logic'
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CHECK_PIN_NAMES OFF
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CROSS_REFERENCE OFF
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FEEDBACK OFF
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INCREMENTAL OFF
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INTERFACE_TYPE PHYSICAL
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MAX_ERRORS 5007 ]$ }) K+ ?' l7 d! P- V/ |
MERGE_MINIMUM 5
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NET_NAME_CHARS '#%&()*+-./:=>?@[]^_`|'6 b# K; k% T* G
NET_NAME_LENGTH 24
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OVERSIGHTS ON
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REPLACE_CHECK OFF
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SINGLE_NODE_NETS ON
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SPLIT_MINIMUM 0$ A+ m7 _* V5 @' N
SUPPRESS 209 J& k$ n3 i, I% m$ C
WARNINGS ON9 b P, X6 r: O+ n, O
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2 errors detected
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No oversight detected2 W: ` g3 B4 R. d; I
No warning detected
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cpu time 0:00:465 i7 w; h1 b# f! { w, s
elapsed time 0:00:00