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本帖最后由 yueyuan2003 于 2012-12-17 21:14 编辑
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别的地方找到的更新说明，其实干嘛老是跟着公司更新软件啊，我就觉得16.3挺好的，功能就很好了
# M8 P5 r) u9 I- D# R) v0 t5 CDATE: 12-18-2012 HOTFIX VERSION: 001$ Q- z' A" l# P5 i" r& E* T4 T4 @
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CCRID PRODUCT PRODUCTLEVEL2 TITLE8 _" w4 m; Y. ^0 }, ^2 ~6 ?
===================================================================================================================================
) I2 o' V2 c- |6 i0 r$ i501079 ALLEGRO_EDITOR MODULES Enhancement for Module swap function similar to component swap
+ W* i$ j7 e! ]2 K* c745682 CONCEPT_HDL CORE Attributes window requires resizing each time DEHDL is launched
% c& L+ b/ I2 ] A" X0 L- n825846 CONCEPT_HDL CORE The module_order.dat file gets corrupted! @( H$ v0 }3 D y! i4 S0 R* h4 I
871886 CONCEPT_HDL CORE Browse button in Signal Integrity window of DE-HDL option causes program crash, G3 f0 r6 S. X& Y9 v+ n7 U G
891439 ALLEGRO_EDITOR INTERACTIV moving cline segments( h$ x9 X0 F- k! C* f# _) T% ~
898029 CAPTURE PRINT/PLOT/OUTPU ENH: TCL:To show net alias clearly in print out if alias has underscore {4 A6 e/ Z. M0 I8 a- Y
923210 CONCEPT_HDL CORE Search with multiple properties does not show all properties% Z, s, c; m/ R9 `' g- z# r1 w# b
938977 CONCEPT_HDL CORE Properties attached to standard/DRAWING symbol does not propagate to parts placed in the schematic% V' z7 S, L. i
947451 ALLEGRO_EDITOR INTERACTIV Allow the tool to select multiple shapes when assigning a net to more than one shape.
/ |" `$ \7 B0 r1 ]% h2 r2 z% h, @2 ~968646 ALLEGRO_EDITOR EDIT_ETCH The Cline to Pad spacing not followed for Multidrill pad it is more then minimum spacing
4 t V7 F2 p, @ T3 m% a" S/ c976723 ADW MODEL_MANAGEMENT SI DML Model has to be provided the Auto Generate function for discrete components on DBeditor* I6 s6 D8 G! L$ k
981767 SCM UI Add series termination in ASA will crash if both output and input pins are selected.
6 ~* z4 v8 X3 n0 x( y982273 SCM OTHER Package radio button is grayed out
& B1 u4 X1 i5 @! ]; e988438 CONCEPT_HDL CORE Visible constraint disrupts MOVE command
9 g) y; Z; B/ D3 D: C) r989471 ALLEGRO_EDITOR INTERACTIV Functionality to zoom to the selected object in Pre Select Mode
@" c3 ~& m6 z) w993562 CONCEPT_HDL INFRA After upreving the design save hierarchy is leading to WARNING(SPCOCD-34).# J% U! p7 P- O" j" S3 T& \& G
996577 SPECCTRA ROUTE Specctra not routing NET_SHORT connections- Z. t9 H5 M/ y4 C$ O1 y( l* l
997992 CONCEPT_HDL CORE Why are Page Numbers not enumerated correctly when multiple TOC Symbols are used?9 D3 h% p0 y" v* ~- a
1001300 PSPICE MODELEDITOR BUG: Simserver crash with encryptedm model$ N F) Z/ ]7 V, o& c
1010124 PSPICE SIMULATOR Monte Carlo summary doesn't list all the runs in case of Convergence error in one of the runs
+ N8 o% U7 \5 N+ z/ Q( n8 ^1013656 SCM OTHER create diff-pair should honour diff-pair setup or ask user for positive negative leg ^1 W6 G+ Z+ M
1013721 ALLEGRO_EDITOR EDIT_ETCH Routing near a 2x3 multi drill padstack does not maintain the spacing constraints.
c' Q. ^8 o# K5 ]1016859 SCM REPORTS dsreportgen exits with %errorlevel%! R5 \$ ^7 F2 E2 `
1018506 ALLEGRO_EDITOR INTERACTIV Edit copy with retain net of via will assign net to pin1 B8 g. d* [& d. s }0 _; G
1020746 CONCEPT_HDL OTHER PDF Publisher tool behavior inconsistent between OSs0 B1 j2 l/ y; b; n/ ?) `4 G8 r
1020798 SIP_LAYOUT SHAPE Shape not voiding on layer 2 causing shorts/ {( g! z( b4 f- e) t* I; y
1023051 SCM UI Wrong and incorrect message is generated while adding connectivity in SCM matrix view � DSTABLE-1406 Q' _' [3 [5 T: A- f- _1 D5 Y
1023774 APD WIREBOND After "xml wire profile data" is imported it isn't reflected to actual wire.
- }, h H3 x# `6 C2 `1023807 SPECCTRA GUI Unable to close SPECCTRA using File > Quit or by clicking on standard window red close cross button
! A: v/ `! Q ]5 Q( [6 z) A1024239 ALLEGRO_EDITOR INTERFACES DXF pin location is moved when I execute DXF out
) c$ l: ~* I4 q9 |1 m1028237 CONCEPT_HDL HDLDIRECT Error binding design when generating simulation netlist
$ T% k( t+ u' v. ~1030591 CAPTURE LIBRARY Library Correction utiltiy locks the library and deosn't frees it even after being closed, T. u8 v2 X2 ]
1035624 CONCEPT_HDL CORE Options pre-selected when launching base product
4 i/ T% U: f6 ?: y1035896 SIP_LAYOUT ASSY_RULE_CHECK Rule Wire Length under Wire on line in Assembly Rule Checker doesn't work correctly
: j' w+ T4 y* Y. S$ i _1036580 ALLEGRO_EDITOR MODULES Module created from completely routed board file has lot of missing connections in it.9 S2 ^" P& d- M) ]/ e
1037345 ALLEGRO_EDITOR INTERACTIV Enhance Allegro's Snap-To tools to select the origin of a sub-drawing(clip file)4 p; [1 H+ G7 i
1038180 ALLEGRO_EDITOR DRC_CONSTR BGA escapes not being calculated in phase tol1 N( w5 I3 A) s% y
1038285 SCM UI Restore the option to launch DE-HDL after schgen.; t; { |& b+ E* b" z5 `
1038371 ALLEGRO_EDITOR INTERFACES Import > IDF fails with error "(SPMHDB-187): SHAPE boundary may not cross itself."
/ R' _6 f. C( `0 K# t7 u) S1038577 ALLEGRO_EDITOR DATABASE Modifying Void crashes Allegro
7 n) x. g* V" {. a1039112 ALLEGRO_EDITOR ARTWORK Antietch and Boundary layers deleted when Match Display selected
* ~0 g( @5 W1 k( j1039147 ALLEGRO_EDITOR COLOR Need an option to change color of Text marker and Text select in Display listing! H, E. R" n7 |
1040653 ALLEGRO_EDITOR DATABASE Cannot update netlist data, ERROR(SPMHDB-121): Attribute definition not found.$ n' B d+ Y! w( r/ y# t
1041368 APD DEGASSING The Degas_No_Void properties assigned to Cline does not work.% ^, F0 M' S( q! x8 b* Q
1041864 ALLEGRO_EDITOR MANUFACT Allegro crashes when opening the Backdrill setup menu( O' ^ W0 H' l' Q6 X1 f$ K* T6 d: L
1042199 SIG_INTEGRITY SIMULATION Waveform list was not refreshed by switching tab.( m& s9 N) C) L& i o1 o$ I) G
1042348 SIP_LAYOUT STREAM_IF GDSII export includes the full refernce path, breaks CATS flow9 H+ U2 [, I) i
1043861 SIG_INTEGRITY REPORTS Derating values are NA in bus simulation report when derating table is not in working directory
* L6 T+ D' `' A K& X/ |$ y5 L* W1043903 GRE GLOBAL This design crashes during planning phases in GRE.% l9 d* D( q' I6 d8 I$ k+ V
1044029 PSPICE ENCRYPTION Encrypted lib not working for attached9 h! V1 A0 j. I( ]- o7 F% V6 F
1044222 ALLEGRO_EDITOR INTERACTIV Capture Canvas Image changes working directory
% l$ u% d0 S; X5 C* s1044264 PSPICE SIMULATOR Why does the 'ORPSIM-15009:This device scales to 0.0 at this Temperature' Error occur.7 e5 j/ n( f1 M5 V. m4 f7 t
1044577 GRE CORE Plan > Topological either crashes or hangs GRE
8 k# o+ P- A" ^. \+ A+ ^0 U, V1044687 TDA CORE tda does not get launched if java is not installed# B2 z; b0 Q2 U+ W; U0 n
1044754 SIG_INTEGRITY SIMULATION Incorrect waveforms when simulating with stacked die
. x5 [3 h) ^7 ~1 x3 |1 t2 b; |1045607 ALLEGRO_EDITOR OTHER Component get placed even after Cancel IDF in form.
& a* d2 ~5 F! Y( g, C1045694 CONCEPT_HDL INFRA Why to package the design twice to pass the net_short property to the board?& m* Q6 ^0 J! G, M* H4 e
1045863 CONCEPT_HDL INFRA Customer had the crash several times when they run script with SPB16.51.
$ J0 [) I3 \! i- F3 a1046929 CONSTRAINT_MGR OTHER Unable to create physical of spacing cset after rename the default cset in design entry.
6 o+ e' h/ o% d, z1047590 ALLEGRO_EDITOR SCHEM_FTB Buses created in Allegro-CM are deleted by netrev in traditional flow
. X I0 ~: K' ]$ z6 v1 Y1047823 CONSTRAINT_MGR OTHER acPutValue predicate text not being displayed at bottom of Constraint Manager window.
; r. q! c9 h1 h& g3 d7 J, T1048403 ALLEGRO_EDITOR SKILL Allegro crashes opening more than 16 files with skill
6 y; t2 ~7 d* ^+ n$ }: P1049262 ALLEGRO_EDITOR OTHER APD and extracta crash owing to Wirebond.
' ` _% D. y! _ n2 |5 P4 L7 N1049303 CONCEPT_HDL CORE Block rename deletes schematic data immediately in 16.5
5 B# [ x$ w% P% E: R5 O9 x1049317 CONCEPT_HDL OTHER bomhdl with scm mode not working on RHEL in 16.5
7 o/ N% N; y& ~; }5 }) [/ C# a1049399 SIG_INTEGRITY OTHER Toggling z-axis delay in CM shows the same value+ F' h5 u8 |% c2 F
1049956 ALLEGRO_EDITOR DATABASE BUG:dbdoctor deletes fillets as design is migrated from old version- J: Y5 W- j# u( x+ f8 ?' d* H
1050408 APD DXF_IF Symbol has 45 degrees rotation in mcm but DXF doesn縯.* R3 ~5 P: B6 A: ]) S( w
1050483 ALLEGRO_EDITOR DRC_CONSTR DRC has been waived but after updated DRC system generated a new DRC.
. H) y2 G& Z" }( f& ? E1050918 ALLEGRO_EDITOR MANUFACT Testprep Automatic generate testpoints with wrong padstack Itype in SPB165S026.
5 m7 N1 b- s- I7 |$ W5 b1051588 ALLEGRO_EDITOR PAD_EDITOR Pad_Designer library drill report omits some drill holes
/ ?8 K& f! z; y: M/ Y, N1052005 SIG_INTEGRITY OTHER Huge difference in Z-Axis delay with the latest hotfix for 16.5 that did not exist in older ISR's of 16.5.
! M% l% ~2 T# A+ v, |1 O( Z% @1052045 ALLEGRO_EDITOR OTHER Bug - Thermal relief connects not sustaining 15 degrees component spin in version 16.5 unlike v16.31 ^) M( W6 P/ u
1052449 CONCEPT_HDL COPY_PROJECT Copy Project does not update all relative paths in the cpm file
# d- [5 K- |# \* m: K1 n9 K% q1052600 ALLEGRO_EDITOR SHAPE Adding a specific cline causing shape errors! ^ b' U4 S9 Z' f1 o, {
1052753 ALLEGRO_EDITOR DRC_CONSTR Allegro showing soldermask drc only when the symbol is rotated.% L. V r0 J' F7 O
1054235 ALLEGRO_EDITOR PLACEMENT Cannot place alt_symbols for mechanical parts.
7 V. L7 V; K# \6 L4 [0 ^1054269 ALLEGRO_EDITOR MANUFACT Backdrill Setup and Analysis crashes on attached design
" ]; a5 r1 O3 L. v6 a; D1054351 ALLEGRO_EDITOR SHAPE Shape voiding fails for board having diffpairs with arcs; o3 s, N8 c8 o, O# x9 ^# Z/ w# ?' E
1054456 ALLEGRO_EDITOR MENTOR mbs2lib incorrectly translates refdes label# s1 w4 k" y: x% E! ]- t1 ~
1055273 ALLEGRO_EDITOR INTERFACES DXF exported from Allegro has an offset in pad location for Y- direction.6 k& L/ Z1 g4 w9 ~
1055328 CONCEPT_HDL COPY_PROJECT Project Manager - Project Copy2 L J8 o; J/ i0 Z! s
1055481 APD SHAPE keepout does not clear shape unless it's picked up and dropped down1 Z6 c& |6 N% [6 [' }4 I l( v! b
1055729 CIS GEN_BOM Standard CIS BOM per page is not working correctly with option Process Selection( K R0 w1 R5 y. w' ^% h3 x% j
1056418 ALLEGRO_EDITOR OTHER PDF exports the blank text markers whether or not the markers are visible.! d# h! o1 f. O& N$ h" E
1056579 CAPTURE OTHER Ability to define custom variables for titleblocks that update for specific variant views+ \; C7 q$ g I @) T/ `( v
1057003 ALLEGRO_EDITOR SHAPE Z-copy to create RKI does not follow board outline B V) z/ U, h6 ]8 g
1057976 ALLEGRO_EDITOR DRC_CONSTR No Same net Spacing DRC on attached design.
, A6 B, {4 ?# Z/ {! B' @9 \. C1058002 SIG_INTEGRITY SIMULATION Incorrect Xtalk sim netlist was created.
X9 |8 M* Y7 `9 H# m# C6 ?1058364 ALLEGRO_EDITOR SKILL axlTransformObject() is moving refdes text when only symbol pin is selected for move
. { Y5 ?1 |' ^8 V9 P1058940 ALLEGRO_EDITOR INTERFACES IDF(PTC) out command output wrong angle value7 E, E, C/ f, N/ s) a
1059037 CIS PLACE_DATABASE_P What enables the Refresh symbol libs option under hte update menu in CIS explorer$ n7 s. _, c; P/ v
1059389 ALLEGRO_EDITOR MANUFACT about back drill analisys report
) |; W" a( Y2 O1 X7 Y( J1059901 CONCEPT_HDL CORE Global Property Change and <<OCC_DELETED>> property value.
* h0 A8 \, Z( h( t+ L- ?% ]1060428 ADW DESIGN_INIT ADW Flow Manager Copy Project fails to complete- ^/ n1 \% Z( e* A% y
1060589 F2B PACKAGERXL Packager Fails with ERROR(SPCOPK-1053): Cannot find a ppt part that matches the instance properties.
) \: M2 }% \% V* V* h4 q' F5 B1060977 F2B DESIGNSYNC back annotate in 16.5 does not bring in already placed nets as global nets/ M1 k8 d, R7 X$ s% `
1061223 CONCEPT_HDL CHECKPLUS What determines a passthru pin?
) N H/ C: N- ]3 h8 h+ y; E) l1061424 CONCEPT_HDL CORE Customer creates <<OCC_DELETED>> property values.5 w! f" y2 \2 t) ?
1061572 ALLEGRO_EDITOR INTERACTIV Shortcut keys wont work after "Edit Text" command is finished.' y5 W( ?5 m! _8 ?
1061659 ALLEGRO_EDITOR DATABASE Unable to return drawing origin to 00
4 g( S; H2 R& s6 N4 u7 t+ g1062558 APD DXF_IF If set both in X and Y offset DXF only get one and not get absolutely value in 45 degree rotation% A( v6 |4 A! a' `: S
1062982 ALLEGRO_EDITOR MODULES Module containg partitions has been imported to the main design and cant be refreshed.
; m* C% t* y% j( W1063284 PCB_LIBRARIAN OTHER PDV Save As is broken( J& k! E0 t) `+ }% }4 q5 E
1063658 ALLEGRO_EDITOR SCHEM_FTB Allegro Import Logic does not remove library defined diffpairs
6 R; O: U: q# c$ g( ~2 J2 Y1063778 CONCEPT_HDL CHECKPLUS The hasSynonyms CheckPlus predicate is not returning true for all global signals.
- ~7 x2 c2 Y. L3 u' P+ d# v1063924 CONCEPT_HDL CONSTRAINT_MGR Highlight the net between DE-HDL 16.5 and Constraint Manager.
( l# I# T0 t4 `+ \: Z7 D9 }1064707 CONCEPT_HDL CHECKPLUS Rules Checker core dumps on design
1 i/ i: d' o9 C" x1065124 PCB_LIBRARIAN SETUP PTF properties cannot be deleted from the setup in PDV
8 u& i% z, ~8 N4 s3 r% ~+ u6 o1065618 CONSTRAINT_MGR ANALYSIS DRCs on board but Constraint Manager shows the columns as green.1 O. L5 i4 W7 }% y& C! g
1065641 PCB_LIBRARIAN CORE PDV symbol editor is crashing when deleting a group using delete or CTRL+X1 X& d2 ]; k4 R) ?3 L- h
1065745 SIP_LAYOUT DATABASE The logic assign net command crashes the application
# P# J! O9 D5 {5 Z* s1065860 ALLEGRO_EDITOR REPORTS Design crashes when running a padstack usage report6 z$ b% ]% r5 G7 e% ] a: L3 b$ D
1066051 ALLEGRO_EDITOR TESTPREP Auto Testprep generation creates TP with Testpoint to Component Locatin DRC
, C9 q( p5 @/ Q$ {1066318 CONCEPT_HDL CREFER Issue with LOCATION visibility in flattened schematic
; h" w$ A* T0 u5 J6 N- m1067339 CONSTRAINT_MGR ANALYSIS Relative Propagation Delay analysis in the Partition file seems very inconsitent.
: @, B) f. R H7 L1 v1067984 SIP_LAYOUT OTHER layer compare batch fails with write protected file% }0 P( D _' [. \7 b
1068425 F2B DESIGNVARI Out of memory message in Variant Editor while 縞hange properties� command
) t4 ~) d! g: `' G! T1068547 ALLEGRO_EDITOR EDIT_ETCH Outward Fanout is not fanning out this 4 sided part as intended* z9 x( w% {2 l O3 t5 N2 {
1068966 SIP_LAYOUT DRC_CONSTRAINTS DRC update aborts on this design with ERROR -3000067
3 r* ~; L" G- J; `# f# V/ H1069215 CAPTURE DATABASE Capture Crash on usnig a TCL utltiy to correct design: l( a6 i% u7 S, `
1069517 SIP_LAYOUT DIE_EDITOR change die abstract pins tab default action from delete to modify
* b% `% Y, S8 K% Q! j1069915 ALLEGRO_EDITOR EDIT_ETCH Allegro hangs with when doing spread between voids: |/ r H7 j6 N8 U/ `
1070007 ALLEGRO_EDITOR PLOTTING Export IPF omits drill figure characters for backdrill holes
: z8 Y" F) Y; }4 T6 r Y& p O1071722 SIP_RF DIEEXPORT Virtuoso SiP Architect not writing out pins to the .dra needed for LVS flow
& D" v* M x/ V0 r1072067 APD EXTRACT When expoting using Extracta oblong pads with anyangle are abnormal2 y! N" V4 Q3 }. [+ Y, N
1072791 ALLEGRO_EDITOR DATABASE Database check cannot fix error and keep report the same issues cause artwork cannot export.
& G! v# ^, P- d! v6 W- `1072806 CIS EXPLORE_DATABASE Query tab in CIS explorer doesn't show searh fields in 16.6% l& y/ ]5 M" ]1 P. l
1072843 ALLEGRO_EDITOR PLACEMENT The move command that was present in the right mouse pop up menu during manual placement is missing in 16.5
: o+ {7 W' u- X4 S1072904 SIP_FLOW SIP_LAYOUT Probe pins not being mirrored in Die Editor correctly in Chip Down mode.
$ A ~2 O' K x; v# X" u$ n1073237 SIG_INTEGRITY GEOMETRY_EXTRACT Some nets has no result at Bus Simulation and Comprehensive simulation. W1 h6 g* y9 ]# W+ H+ i
1073445 ALLEGRO_EDITOR GRAPHICS 'infinite cursor graphics fail -ghost copies as you move cursor
& }2 y2 ~5 J Y( Q2 x8 b t1073464 SCM SCHGEN Schgen never completes.
# K6 V& b% h2 w/ u1073587 SIP_LAYOUT OTHER axlSpreadsheetSetWorksheet command clears the cells in memory0 K& i2 c3 F( d5 B4 C6 I3 m& l
1073745 CONCEPT_HDL CORE Import design fails, [) y" G: U: A0 v9 D
1073852 ALLEGRO_EDITOR INTERACTIV While doing a Copy Via use the last 'Copy Origin'$ E6 @" G$ S* ]3 T6 S0 @5 J* q
1074279 ADW DSN_MIGRATION Design Migration fails purge if there are cells with BODY_TYPE! K4 P0 z# I. ]' I
1074791 CONCEPT_HDL HDLDIRECT User gets port exists in schematic but not on symbol message even though the port does not exist( r' ~& P- E( ^
1075135 ALLEGRO_EDITOR DRAFTING Ability to edit dimension text block in Instance Parameter7 n. V0 M* y7 I$ E) V. j3 T
1075151 ALLEGRO_EDITOR SHAPE Cannot change global shape parameter back to thermal width oversize after having used fixed thermal
( ^$ V# P1 t1 e; {* |0 x1075256 ALLEGRO_EDITOR OTHER Import > IPF in 16.5 is dropping data.
E8 R( N( \# e* U, t5 ` C1075853 ALLEGRO_EDITOR REPORTS please add "PART_NAME" at Extract UI# Q2 _) I* N( c2 P: o8 h* Y; C
1075934 ALLEGRO_EDITOR DRAFTING Able to Changing Dimension Text Block
y7 m+ f! X9 _- V# Y4 W% I2 J1075955 CAPTURE SCHEMATIC_EDITOR ZOOM in 16.6 using key "I" on keyboard in not centered on mouse pointer
+ `/ h, h) H- x( [# z4 H# W1075964 ALLEGRO_EDITOR SHAPE Shape voiding is not consistent in conjunction with odd angle and arc traces
9 s) V- A1 @- V- i% ?3 M0 x N* H1076086 SIP_LAYOUT IMPORT_DATA missing wirebond after import SPD2
4 ^$ G2 L2 f4 J: V2 q: `- Z; r, Y5 b" x1076202 ALLEGRO_EDITOR EDIT_ETCH Allegro add connect causing crash after Hotfix
4 }# n" K# c% [3 [1 @# w1076205 CAPTURE PRINT/PLOT/OUTPU : Printing of User Assigned RefDes8 q( p) T2 v3 u" Z& H/ v k* A
1076536 ALLEGRO_EDITOR DRC_CONSTR Embedded component which protrude out toward Top do not create DRC with Place Keepout on Top
l' P1 k- _! \ F- i* \$ \1076538 CONCEPT_HDL CORE Property visibility changes in attribute form not updated in schematic canvas.$ a' a V1 k) J+ B
1076655 APD DXF_IF Dxf does not get offset value if die symbol padstack has offset value! F4 T7 ~3 o4 B7 s" p
1076846 ALLEGRO_EDITOR EDIT_ETCH Grid snapping broken after slide in 16.67 i5 t0 {1 U8 ?
1076891 ALLEGRO_EDITOR INTERACTIV Symbol rotation not displayed correctly when defined as a funckey
( r0 N$ Q& h# G7 y1076909 ALLEGRO_EDITOR DRC_CONSTR Allegro crashes while placing modules from database
/ X: e3 Z3 o8 t# U9 B& \* q1077084 CAPTURE NETGROUPS Crash on selecting bus when Enable Global ITC is unset
: c% I6 S# ~5 ^4 m& E" ]/ l1 D1077169 APD SHAPE Shape > Check is producing bogus results.
- b: Z. }2 d2 v1 J1077572 ALLEGRO_EDITOR DATABASE Mechanical symbol created with 16.6 cannot be placed on board.
, W1 B1 S/ ^* X$ ~. r1077879 ALLEGRO_EDITOR SKILL Allegro Skill axlDBCreateFilmRec fails when 15th argument missing "draw hole only" for the first tim
, w+ C3 t7 m! Q& @$ v1078380 SCM OTHER Custom template works in Windows but not Linux
& Y, z& y+ C. E! k( t* X9 n1078497 ALLEGRO_EDITOR INTERFACES Import DXF does not seem to work correctly.# v8 c E& k+ n
1078682 ALLEGRO_EDITOR DRC_CONSTR Unaccetable slowness with Slide5 L5 K7 B8 Q% e9 \# C
1079082 ALLEGRO_EDITOR PLACEMENT Swap components, gives error SPMHGE-616, when symbols instead of components are selected for swapping
& S! _( E7 ]9 z+ N" y7 n, n1079533 ALLEGRO_EDITOR PLACEMENT Swapping components in 16.6 results in Error "E-(SPMHGE-616): Symbol and layer embedding requirements do not match"' v2 F1 L) j3 q7 }/ @5 y( i
1079937 CAPTURE SCHEMATIC_EDITOR ZOOM in 16.6 is non uniform on text
`8 V0 q1 T4 l. f9 D0 C1082582 ALLEGRO_EDITOR GRAPHICS Allegro hangs on a given testcase using the MMB zoom control
) n* ?# V# r% h% _" v! h \' }/ T+ H: _1082981 ALLEGRO_EDITOR SKILL Allegro crash while change the new symbol type as mechanical.7 j6 D. c* h7 I6 l4 C2 M
1083230 SIP_LAYOUT SHAPE Shape fill in 16.6 releaase not fillilng shapes as good as it did in the 16.5 release.% `- @0 o/ c. d' b
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发表于 2012-12-17 12:49
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发表于 2012-12-17 16:50
