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8 S# f+ \% L) n! o% g6 FDATE: 12-8-2011 HOTFIX VERSION: 041
8 D' J5 l- j+ q8 ]: C* T===================================================================================================================================
- n! r$ C+ f! H) A+ J$ ~# uCCRID PRODUCT PRODUCTLEVEL2 TITLE
* E8 }. r& t3 ?$ t& w===================================================================================================================================
1 H* ]* A) p8 }5 Q8 Z/ r875695 SIG_EXPLORER INTERACTIV Enforce Causality check box doesn't work." Z* [. \; B: _$ I" r
944006 ALLEGRO_EDITOR EDIT_ETCH Vias added to shapes behave differently9 f ~, H" ? u5 ~1 f; b) H) T
946293 CONCEPT_HDL ARCHIVER Archiver hangs if there is a whitespace at the end of the path of cref.dat P5 K$ ^6 I z# c( a' K8 ^- @
951919 ALLEGRO_EDITOR OTHER Exported package symbol soldermask and pastemask padstack locations not the same as original
' i7 O* F# }: s3 a2 ~3 F6 C952057 SCM PACKAGER Export Physical does not works correctly from SCM; j8 o6 C! y* Q7 F, [* F( u
953018 APD REPORTS Shape affects Package Report result.
0 B4 Q( B3 D) W K1 l4 q1 _; O953279 SIG_INTEGRITY LIBRARY mkdeviceindex is adding dml file listing in env file9 f) B; d# U- K* k% c) \
953827 ALLEGRO_EDITOR EDIT_ETCH Snake Breakout function crashed Allegro; G% o( s. ^7 D, e* d
953917 CONCEPT_HDL ARCHIVER archcore should handle errors correctly: t$ i5 {/ H% H& D% q# }7 L
953971 ALLEGRO_EDITOR MANUFACT NC Drill files not generated correctly when using the option "“separate files for plated/nonplatedholes”* G. y' V7 }3 b {* |0 x, j
954055 CONCEPT_HDL CREFER Crefer fails with UNC install path
# r7 s6 T3 h6 v$ ?' t1 Q# g954858 CAPTURE LIBRARY_EDITOR Closed polyline used in pin shape is not appearing while using custom pin in part.
! d( J; @, K( a: ?7 k3 ^0 X9 J955029 CONCEPT_HDL CORE custom text font size not recognized in symbol view; v" t+ y- u/ V( N
955133 SIG_INTEGRITY FIELD_SOLVERS The Field solver creates the differential trace model which is reversed T(D1) and T(D2) of bottom side.) ~: o2 }" H2 _ ~2 T2 _2 m& t
955299 ALLEGRO_EDITOR DRC_CONSTR drc text to smd pin does not work any more on this database in 16.3 S039
/ x& O! \5 V- _9 a& Q955338 CONCEPT_HDL CHECKPLUS Need to change PART_NAME+ `8 w+ e4 a2 N0 O5 m9 y
956751 ALLEGRO_EDITOR ARTWORK Import Gerber command does not work correctly
: f \* U& V4 k) ]) g7 L; }8 U- x958252 ALLEGRO_EDITOR TESTPREP Resequence testprep with the option - Delete probes too close crashes the design
8 u5 g9 X C, p+ z958945 CONCEPT_HDL CHECKPLUS Checkplus from 16.3 is not running with our "Allegro Design Entry HDL XL (16.5 licenses)- s1 o/ h3 N: c, v) q
( z* n0 a0 S/ ~: f m, X5 ZDATE: 10-21-2011 HOTFIX VERSION: 040( K( o( c8 ~4 U% i
===================================================================================================================================
# T+ f+ Y: L% J. mCCRID PRODUCT PRODUCTLEVEL2 TITLE$ k+ l8 \/ a5 P8 }! [0 N
===================================================================================================================================
. y5 T0 [2 O( V735439 PCB_LIBRARIAN CORE PDV Moving line-dot pinshapes by arrow keys breaks the pinshape _+ y$ r/ N, O
935438 CONCEPT_HDL COPY_PROJECT Copy Project changes read-only hierarchical block permissions
. @8 \8 ]5 t% x V% g935836 SCM SCHGEN ASA crashes when generating Flat Document Schematic
0 I: M% w. k* x937165 SCM SCHGEN Can't generate Schematic
1 Q2 X6 j+ O. U) F: m9 _# M/ V941426 CONCEPT_HDL COPY_PROJECT Copy Project fails - Updating opf view This can't happen!' q( ?: S3 N9 ]& k
941814 CONCEPT_HDL CREFER CreferHDL crashes during ScheGen
- t0 C" c; w7 ^; V942522 CAPTURE GEN_BOM Export in excel check mark doesn't invoked BOM in Excel
8 I9 D w4 N( X- A943032 SCM OTHER ASA is not passing the correct reuse_module name to Allegro PCB layout.
. D2 Q, B: W5 I y946350 F2B DESIGNVARI Variant Editor rename function removes all components6 G, b& G! F, S+ x
946419 SIG_INTEGRITY SIMULATION Cannot select component on BoardModel for controller in bus setup form
) d) z" e( j2 B( B9 V3 Z0 V, D947789 ALLEGRO_EDITOR MENTOR mbs2brd crashes during translation on the attached design.( o$ z, d3 I: t
9 _ u6 E$ T8 s5 C6 A
DATE: 10-6-2011 HOTFIX VERSION: 039% o& \$ ^$ [) n1 g
===================================================================================================================================
# U5 z" e- g5 w% j- b4 V! TCCRID PRODUCT PRODUCTLEVEL2 TITLE* O6 A$ h& A8 f( Y# Q1 x
===================================================================================================================================0 @0 c+ @- |, [
841096 APD WIREBOND Function required which to check wire not in die pad center.
* l$ V/ o1 y7 C) a5 a2 N9 [912942 APD WIREBOND constraint driven wire bonding
& D, E$ W" P# n, l, D" T917887 PCB_LIBRARIAN VERIFICATION Part should not be released if the alt_symbols has errors7 q& Q: X# {9 }6 H- t2 ]' h* d
923315 SIG_INTEGRITY GEOMETRY_EXTRACT crosstalk simulation fails with TMP popup failure2 m0 s/ q# z$ H; \5 p! H
927950 APD DATABASE My customer name their layout cross section subclass name as “wire” in Die type.
5 s0 u% u4 f6 B" B( k8 |( P929348 F2B BOM Warning 007: Invalid output file path name0 H/ S+ ]: ?7 `3 q, l
930783 CONCEPT_HDL CORE Painting with groups with default colors& m3 ?* B6 I: K6 s3 i6 p
932091 CONCEPT_HDL CORE Prop attached to SIG_NAME property( F/ I5 l9 l0 `. q) D) R6 P
932871 APD GRAPHICS could not see cursor as infinite
- c# Z; ~; s0 ^4 R5 K933356 CONCEPT_HDL CORE Net prop display size become 0 if it was attached to SIG_NAME prop.% {' }9 d. u5 C2 w/ C1 v6 A
933532 ALLEGRO_EDITOR COLOR Bad color assign and initialisation during creation of new subclass! h; Y" t% B1 R5 o9 t m
934008 ALLEGRO_EDITOR REFRESH refresh symbol updates symbol text to some unexpected values
" d, u; o: n) [6 s( x6 z3 c934533 F2B DESIGNVARI The Variant Editor errors are not written to the variants.lst file
! u9 o: S/ a/ G1 O$ h935911 CONCEPT_HDL CONSTRAINT_MGR Mapping of constraints fails after importing layout constraints3 I8 O; V. E2 ~# V4 m5 d6 q5 v
936098 ALLEGRO_EDITOR SKILL axlDBCreateCloseShape does not work correctly.6 I2 q* B6 X b8 i' \4 V1 c) I
936794 CONCEPT_HDL CORE Unable to select Allegro Design Entry HDL XL
% f0 A3 c5 G& B2 E! `937087 CIS DESIGN_VARIANT Upreved design becomes very slow in Variant view mode. DELEET THE DESIGN AFTER RESOLVING THE ISSUE
1 p! m% S5 B6 H6 q) X937173 CAPTURE OTHER Wrong license information "UNLICENSED" in Capture >> Help >> About
+ d$ o; U. Z! a7 g: Q937290 APD PLATING_BAR Plating Bar checks does not recognize connection made through etchback through shape./ z8 l- _7 n& ]; y# @% a
937411 ALLEGRO_EDITOR DATABASE downrev_library reading from one directory and writing to another hangs the command.
+ u g- D9 H0 B3 Q5 }938143 ALLEGRO_EDITOR CREATE_SYM Why is this Extra Property 'ECSET_MAPPING_ERROR; j% d" t& o, S i+ x
938281 SIP_RF OTHER export_chips creating bad data when symbol is split and contains V- V+ pins
0 g4 I& Q4 l% g. m$ f939918 PSPICE PROBE Print > Preview for output file causes Pspice crash." }# W' y7 t* W# A9 L
940217 CONCEPT_HDL COMP_BROWSER UCB reports 'No Symbol found for the part'
4 d7 m9 h1 ~5 p/ c9 |' P3 r
5 Z, @8 v% B* ]. o: }+ v. nDATE: 09-21-2011 HOTFIX VERSION: 038+ T! Y! q% o2 N7 @
===================================================================================================================================5 ~" e5 @' Z4 _. e
CCRID PRODUCT PRODUCTLEVEL2 TITLE' ~$ U" e8 g8 Y# S* ?7 l, C
===================================================================================================================================- E( [% R5 }$ N# V
924448 F2B DESIGNVARI Design does not complete variant annotation
& B# j- r1 ]) K& W2 U N2 z9 C S927104 F2B DESIGNVARI Tools > Annotate variants crashes when there are ASCII characters in the property values$ |/ V6 n; |% [. r
928738 PSPICE PROBE Y-axis grid settings for multiple plots
. R+ ~7 v1 ~# p$ L, D/ q% M929284 CONCEPT_HDL ARCHIVER archive does not create a zip file
% f1 k7 e6 v5 N930063 ALLEGRO_EDITOR TESTPREP Test prep crash Allego when it can not create pin escape1 U- Z A' x' ~7 w
930180 CIS LINK_DATABASE_PA Visible property position on schematic get reset on "link database part" operation
& G- O8 j1 D* p2 u3 @* G5 O930355 SIP_LAYOUT WIREBOND about "wirebond add nonstandard" command
$ |( W" ~+ U# K( H! X& ?5 z+ @5 T$ y' ~930894 CAPTURE TCL_INTERFACE PDF export doesn't creates property file if some symbols are used in page name/folder name/ H0 X- L. s- b) O
930978 ALLEGRO_EDITOR SCHEM_FTB 3rd party netin error - Pin is connected to net <netname> not reconnected no longer happens/ [- ~" h5 u ^' N7 s S
931248 ALLEGRO_EDITOR DRC_CONSTR Match Group was removed if member nets became xnets.
1 n Y) h( F# o0 F, H6 O* k- R2 T931274 ALLEGRO_EDITOR DRC_CONSTR Negative Plane Islands waived DRCs reappear after performing update DRC.( \* V$ j8 n; k
932639 SIG_INTEGRITY OTHER Add Connect command hangs for about 14 seconds and then returns./ K7 J f& B$ Q4 Q6 F$ z4 n
933145 F2B PACKAGERXL Add Subdesign list is truncated in Force SubDesign Design Name pulldown' w$ k- I! I# F5 Z2 s/ L
8 f d% I( m5 S' S0 tDATE: 09-9-2011 HOTFIX VERSION: 037
6 L) ?; U3 k5 A' J* i===================================================================================================================================. [# v) i K' R: M9 t- F l
CCRID PRODUCT PRODUCTLEVEL2 TITLE7 ^* u( ~/ f4 R" ?+ K* R$ S/ e
===================================================================================================================================* O! n" p- j& r1 T7 E) n
734687 PCB_LIBRARIAN IMPORT_CSV PDV Generation of entity view fails after CSV Import
: E4 g0 Z7 j$ s# @( j% k734718 PCB_LIBRARIAN IMPORT_CSV PDV Import CSV corrupts parts and generates duplicate $PN on some pins
- |* Q& L% N7 r0 l820131 CONCEPT_HDL OTHER Moving symbols to other page will make Allegro components unplaced because logical_path changed.* [' `# z( t% Y b
868712 SCM UI Why can't I modify CAP associated component? L6 }0 n# X t; Z- P: R
920327 CONSTRAINT_MGR ANALYSIS The TotalEtchLength predicate in Constraint Manager does not work for a netclass with a bus.
# F$ @, Q5 Y8 i! ?( v, V922066 CONSTRAINT_MGR ANALYSIS Custom measurement Actual not being cleared when layout changes.6 C) p. Z7 U' m1 P8 _
925338 CONCEPT_HDL CORE This application has requested the Runtime to terminate it in an unusual way
0 u# u, |) l) r7 z/ Y925530 SIG_INTEGRITY OTHER Why the single line impedance value for Top and Bottom layers are different for this design?6 Q: {2 q& o' j) i& G, L
925976 ALLEGRO_EDITOR MENTOR mbs2brd fails to import data
9 r7 V7 C: K8 w3 n2 j' w9 T5 n926503 CAPTURE GENERAL Memory leak Capture/Pspice
3 H! ]9 Y/ P* O, ]; E) D926887 CONSTRAINT_MGR CONCEPT_HDL Pin pairs lost after Export Physical. a# ] R$ I: k4 j( M
927637 SCM CONSTRAINT_MGR ASA crashes on change root and also performance is too slow.
: ~ B& K. J2 n0 o$ F% o3 f k928286 CONSTRAINT_MGR INTERACTIV The value of pin-dealy has gone with long match group name.7 F$ w3 |6 T+ X# v) J, Z
928483 ALLEGRO_EDITOR DRC_CONSTR Running Update DRC removes Via List DRC Error when via is actually not in the list
5 C f) I0 T- y$ y e929174 ALLEGRO_EDITOR OTHER Display mesure get different result between 16.5 and 16.3
; [, m, s' ?- x! M929656 ALLEGRO_EDITOR PADS_IN PADS translation fails with Microsoft Visual C++ Runtime Library error' d* i$ p; m+ e3 b- s
+ F, v+ u6 t6 d" z# ~DATE: 08-26-2011 HOTFIX VERSION: 036( `/ r4 v: c" {1 n# @1 K$ }# T5 M
===================================================================================================================================
, k3 ]- Z; W0 c, w, u. H) w& B I' HCCRID PRODUCT PRODUCTLEVEL2 TITLE
/ u1 N* n/ C0 j1 `/ ~===================================================================================================================================
0 ?+ d" h& [9 [4 U+ o; a$ m0 k891079 CONCEPT_HDL CORE DEHDL crashes with large number of commands in Winodws mode
1 m# W2 A8 v4 f909595 APD LOGIC Inconsistency between export die text out and show element after pin swap- J) C( h! F: }1 c
914870 MODEL_INTEGRIT OTHER mergedml fails to merger 2 DML files from the model integrity
9 }+ _* n' y7 P8 U* L) I6 ~916321 CAPTURE GEN_BOM letter limitation in include file
9 r8 L( N0 |4 ?2 k917967 ALLEGRO_EDITOR REFRESH Update symbol resets refdes location for bottom side components only.
_+ j+ L4 Q. K8 X+ Q. M2 A919976 APD DATABASE Update Padstack to design crashed APD.
- z* a1 v' S. Q. |922519 ALLEGRO_EDITOR SKILL add_bviaarray command fails for some clines but not all
( X; S, D* l: U3 U9 t: f923910 CIS PART_MANAGER Copy & Paste operation from Part Manager copies properties only to first section of the part.
- R; p0 I8 t$ ]/ d( u5 U X$ u, ]924458 SCM OTHER Project > Export > Schematics crashes
+ Q9 [* b2 ], a. w! p924621 ALLEGRO_EDITOR SHAPE Dynamic shapes are disappearing upon updating them to smooth.
D! x4 g/ m3 _: O0 i: a, a925193 SIG_INTEGRITY FIELD_SOLVERS Diffential Impedance (DiffZ0) values computed in the layer stack-up is incorrect
" @) S' j+ {7 e @# [2 [! |) _926443 CONCEPT_HDL CONSTRAINT_MGR In new 16.3 "035" ISR Concept2cm will crash with error.
0 Z ^( z* V# k$ o& t" k- q8 F- d+ w. o, C
DATE: 08-12-2011 HOTFIX VERSION: 035
4 Z- B/ U) q3 J- \* x/ |. e===================================================================================================================================
( O# N# x; d3 q5 E6 GCCRID PRODUCT PRODUCTLEVEL2 TITLE* C; T9 \7 c: w* v- f7 x0 K
===================================================================================================================================- U% }& A" K8 `5 B
861956 CAPTURE IMPORT/EXPORT V16.3 is not respecting if the net names were written in LOWER CASE or UPPER CASE in EXPORT FPGA.
; x e6 ?" N- b8 i: i, k: o868216 PSPICE MODELEDITOR Encryption of subckt names, internal nodes, comments
2 t; ^5 s& d0 m$ ]4 e9 K4 l1 }2 {870247 PSPICE SIMULATOR Encrypt a model and simulate it, info about inside nodes being dumped in the probe file: Z. E @% f2 p w
874010 SIG_INTEGRITY OTHER PCB SI crashes when the Xnet is extracted with VARIANT_TO_IGNORE property.
& O" u# \$ q4 o" E9 d2 O882567 SIG_INTEGRITY OTHER PCB SI crash if boolean type prop was specified to VARIANT env.( G) _& U; w; r0 H; W& o9 D
895902 RF_PCB OTHER Alphanumerical allegro pin numbers are unusable in ADS 2009 Update 1
l. o i- w& x- g% B# @895919 RF_PCB OTHER Round trip Allegro to ADS to Allegro requirement4 V% n$ f+ U4 o& a$ d
903102 ALLEGRO_EDITOR OTHER Zcopy shape command for cline seems not to work correctly.
' _/ k4 @# Y" k# [8 o; u4 Q2 i905533 ALLEGRO_EDITOR INTERACTIV Pin numbers for components on BOTTOM Side are moved in Preselect mode,when the BOTTOM layer is invisible- O Q# e1 B' F3 L3 Q9 b. \
905562 SIG_INTEGRITY SIGWAVE Noise margin seems not to be measured correctly with Eye Measure function.
, Y7 M1 ^9 ?2 ]( i: O5 m905777 SIG_INTEGRITY SIMULATION User gets popup message that halts an analysis until it is acknowledged0 N* t7 I8 `+ u w# l" a
915630 PCB_LIBRARIAN OTHER Error when running SI Model Interface Comparison using IBIS models
3 m( ?8 X) s9 ]7 q% `, s# W! p915755 CONCEPT_HDL CONSTRAINT_MGR Cannot view net in SigXP
2 U; a i% S; `( Y916462 ALLEGRO_EDITOR DATABASE Edit>Split_plane>create hangs Allgro PCB Editor; o3 G2 X L9 t+ N
916495 ALLEGRO_EDITOR INTERACTIV Pick selects components from invisible (Off ) layer
I. m' ~' Y. a9 f; D. ~/ f917434 APD OTHER Stream out GDSII has more pads in output data.
# H- t: |6 p* B s; V918187 CONSTRAINT_MGR OTHER Missing acGetTotalEtchLength predicate.5 ^! l: ?. P+ D& f4 J4 [5 t
918576 CAPTURE DRC Incorrect DRC is reported for visible power pins which are connected to power symbol7 j5 R% o. U( h3 Y4 C
919343 ALLEGRO_EDITOR PLACEMENT Place Manual is crashing the board file
" A7 g1 M# p3 @! X& o919481 CONCEPT_HDL CHECKPLUS CheckPlus isGlobal function is not working; P; u" Y7 {4 H$ x9 Q
920712 ALLEGRO_EDITOR ARTWORK Program has encountered a problem ... error when creating artwork! s: b, t X& A9 R( c- f2 @' m
' S5 i8 g7 N: |( {- E3 gDATE: 07-29-2011 HOTFIX VERSION: 0349 \6 @, U3 }- v, g& w9 p2 U$ ]
===================================================================================================================================* |5 W2 y' _& y$ D8 V/ h
CCRID PRODUCT PRODUCTLEVEL2 TITLE
7 {( u) d- y! I- f# n2 j q===================================================================================================================================
5 L" h6 t, Z$ \4 O6 P4 H, q* K882677 EMI RULE_CHECK bypass_plane_split fail if BYPASS_XXXX_EFFECT_DISTANCE
' p, m; q6 T6 o9 r897196 CIS LINK_DATABASE_PA Schematic Contents are not shown in CIS window while link Dbase part for parts placed from library3 [4 M+ h2 Z' q9 o4 r" ]
902066 ALLEGRO_EDITOR DRC_CONSTR Shape in Region not follow the constrains
% o5 S3 s9 K, U( g: ~903719 ALLEGRO_EDITOR INTERACTIV Nets highlighted by netclass cannot be selected on the canvas to dehilight9 E3 A* `( g/ {" R: x- X. R
903898 PCB_LIBRARIAN GRAPHICAL_EDITOR PDV move symbol graphics and Undo causes corruption in graphics: K0 j6 i9 T* g: \) e E
904287 ALLEGRO_EDITOR ARTWORK some cline with arc is missed, when creating artwork.) V( A& Y1 b( u$ |7 B2 A: Z3 D, ]
905796 CONCEPT_HDL CONSTRAINT_MGR Fujitsu CM issue inaccurate concept2cm diff pair issues
6 `! ]7 }2 [' y# a6 {6 m: ]907885 SIG_INTEGRITY OTHER Matchgroup targets lost when importing netlist to Allegro layout in HF31
( V! I" D, B) @- x7 Y908057 CONCEPT_HDL CORE DE HDL crash with the cut and paste of a signal name
& L: V6 L9 N4 w0 ~1 ]+ l2 Q6 V908060 CONCEPT_HDL CORE CTRL+LMB Option not working correctly in 16.3
# q" `7 J7 g& H0 a6 K$ T908680 SIG_INTEGRITY OTHER Extra prop delay due to resistance
' j+ G/ Z. `) A! b3 s: L908874 CONCEPT_HDL CORE Part Manager - No Part Found error when using CCR# 775788 feature9 J6 ^2 G6 c1 l! K4 Z6 t; i$ P
909635 SIP_LAYOUT DIE_STACK_EDITOR Add Interposer crashes in SiP Layout8 `2 _/ X- _" Z5 T7 `7 p
910713 F2B DESIGNVARI Variant Editor crashes when you click web link under “ hysical Part Filter” window.
* Y0 Y: r0 w- ?, H4 F5 {910936 F2B PACKAGERXL ConceptHDL subdesign net name is inconsistent
/ F, S, p& Y* Q911415 ALLEGRO_EDITOR COLOR assigned color cannot be removed
# Y) G6 W, O& S3 O& N3 F912343 APD OTHER APD crash on trying to modify the padstack/ B7 G+ ^# T/ n, O
912384 PCB_LIBRARIAN CORE PDV Symbol Editor often freezes when moving groups objects by arrow keys
: T7 @' |" b% R; b912459 F2B BOM BOMHDL crashes before getting to a menu; n& C" U1 ^2 l' i( f3 _% y
912853 APD OTHER Fillets lost when open in 16.3.
8 O; z; H" x( _. h913359 APD MANUFACTURING Package Report shows incorrect data
& `1 n f0 Z M4 @+ @913521 ALLEGRO_EDITOR SCHEM_FTB Netrev error “(40) Object not found in database” for a part which is packaged correctly in FE# b1 s+ [$ C, i- I. R
913586 ALLEGRO_EDITOR ARTWORK Cannot create the drill figures in this design.- j, O, |8 Q3 \3 R6 b1 `
914009 ALLEGRO_EDITOR DRC_CONSTR Diff impedance worksheet showing almost zero impedance for differential pair in attached testcase.
) h' U6 t$ }; ^914558 ALLEGRO_EDITOR ARTWORK Gerber6x00 output creates unpainted niche in a shape3 x& h! ?+ [- j6 r* m
915742 CONCEPT_HDL HDLDIRECT I get a newgenasym error and crash when trying to save the symbol! H+ ~# b, v' F5 r- ]* x9 }
916469 ALLEGRO_EDITOR REPORTS One Unrouted pin does not show in Unconnected Pins Report) s* V8 p( f% F i H: P- h
6 n% z: V7 g, j K3 Q% f) N5 fDATE: 07-15-2011 HOTFIX VERSION: 033
" ]. m/ G5 C3 m2 j' ^ M4 |===================================================================================================================================
% x: k9 t$ X7 c5 `CCRID PRODUCT PRODUCTLEVEL2 TITLE& I7 L3 n4 L% x( l
===================================================================================================================================
6 N( G C, `6 k3 C5 }/ Z! E% _1 X746562 CONCEPT_HDL CORE Deleting attribute causes other property value to move/change
/ O7 G. j) J& `902349 CAPTURE LIBRARY Capture crashes while closing library
( R& w- A5 `! K7 F& b3 I903171 PSPICE NETLISTER Why Capture is treating hierarchical power ports as floting nets in complex heirarchy designs?/ |5 s9 p) C5 ]$ a M+ |/ f" J
903713 ALLEGRO_EDITOR PARTITION Placement Replication do not work fine in the Design Partition
& L q1 V( |7 b; K4 e- A905337 CONCEPT_HDL CORE ConceptHDL crashes after Import Design process.8 d! a7 R7 |" A6 l/ j# y6 K2 e
906153 ALLEGRO_EDITOR SCRIPTS Unable to run allegro script in batch mode on the attached board.
9 b$ Q7 w% l9 j( S906517 PSPICE PROBE PSpice new cursor window shows incorrect result.: \9 H: {: F" B* o" s6 h9 w8 G
906627 ADW COMPONENT_BROWSE ppt options are not read if ucb is launched from FM. works fine if launched from dehdl.
! }. m% Y0 R, G% P906750 ALLEGRO_EDITOR PARTITION Importing design partition removes the testpoint reference designation
4 |7 J( W8 H) T906874 PSPICE NETLISTER Error less than 2 connections for unconnected hierarchical pin
4 z& L6 \7 b5 k! |+ h- y+ T907095 F2B OTHER Part Manager does not show Error as Undefined when directive ptf_mismatch_exclude_inj_prop is used
$ ]' f' A: s# p) B908000 SIG_INTEGRITY OTHER Inconsistence z-axis delay reported on Tpoint when define at via location.
% H R7 U6 T; ?: r v908595 APD 3D_VIEWER Cadence Design 3D viewer" screen pops up and is all black because the colors have all converted to b$ L0 J. M8 f% W2 o) |
908849 CAPTURE ANNOTATE Getting crash while annotating the attached design
) S/ X4 u5 I; O5 ?5 E* Y7 [909760 SIP_LAYOUT MANUFACTURING Create bond finger solder mask doesn't follow the mask opening as defined in the padstack
* J) D3 \6 d2 i' s/ ]+ T909861 F2B PACKAGERXL NetAssembler broken within the latest 16.30.031
. [$ ~" ]* m* y$ G
. u X- B- b0 C% `6 |) ODATE: 06-22-2011 HOTFIX VERSION: 0324 c7 n; K5 z! o3 b2 p; H
===================================================================================================================================
' l- G% z) P! L6 kCCRID PRODUCT PRODUCTLEVEL2 TITLE7 x2 H+ ?3 ?& g3 X# `
===================================================================================================================================
$ `5 k. O: _" c; c774270 F2B PACKAGERXL Require to ignore space in Pattern setting to prevent duplicated Refdes.
3 \. l4 j& T$ M- M* }# _833542 CONCEPT_HDL CORE PDF publisher font is NOT WYSIWIG with respect to what seen in DE HDL
7 v% n* J/ c, v3 j4 i893544 ALLEGRO_EDITOR INTERFACES IPC-D-356A netlist issue with BB vias.: \) Q M$ q9 Z2 @0 h& n2 p
893765 ALLEGRO_EDITOR PARTITION Mail command not sending out email on Linux platforms.2 q. N! T; b6 Y& H6 _
895933 APD DATABASE Update Symbol shifts the center of the Dynamic Fillet and creating DRCs
" h8 X Q* ~" C* Y897484 SCM CONSTRAINT_MGR No match found for 'fileops.txt' in the search path' T2 |& k% d; ]2 d0 K" _; a
899556 ALLEGRO_EDITOR ARTWORK Import artwork seems not to work correctly.
5 @" f3 i$ P' N; _8 c% [902959 CONCEPT_HDL HDLDIRECT HDLDirect Error while saving design
; m! g6 g+ h" L903680 CONSTRAINT_MGR ECS_APPLY Constraint Manager not passing all hiearchical member objects to a custom measurement.0 S- G& h0 {& f2 Y2 I; Z
904403 ALLEGRO_EDITOR DATABASE Allegro crashes when refreshing module
; b- C1 T$ _/ ]: c) w9 h# f904771 ALLEGRO_EDITOR MANUFACT Pin Number display issue.! a) ]1 m$ @& c9 ? `% @/ f: T1 j+ D
905144 CONSTRAINT_MGR ECS_APPLY Min Line Spacing is larger than Primary or Neck Gap less(-) Tolerance but No Warning in CM
7 |2 H) `+ t- ~2 G3 j b4 U, M" B3 q905273 ALLEGRO_EDITOR MANUFACT Drill legend creates more tables than nclegend creates tapes
0 X/ k4 A8 M1 H! N905314 F2B PACKAGERXL Import physical causes csb corruption1 x* v! @4 e. a) A5 T( z5 F
# s% U! z: _# c. F0 L0 u. ?
DATE: 05-28-2011 HOTFIX VERSION: 0314 q! @/ e2 ]- W( N! j% v6 M$ K
===================================================================================================================================
2 T$ P9 T: N. p! h# O. e4 BCCRID PRODUCT PRODUCTLEVEL2 TITLE6 Z1 e) g5 {! _, z( y
===================================================================================================================================( ^+ Q; o2 T+ P
606959 ADW COMPONENT_BROWSE Key properties with blank values are not getting read in shooping cart
' d" {0 X4 _9 F/ R644122 SIP_LAYOUT OTHER SiP Layout - xsection - ERROR Adjacent conductive layers are not allowed, but these are diestack layers not conductor" }$ F% G3 ^( a H9 `
799014 CONCEPT_HDL CONSTRAINT_MGR concept2cm errors not shown in export physical after hier_write
. g, h9 z# G& g7 a; }4 K866830 SCM REPORTS Multiple lines added as separator between title block and report header instead of single line
1 m" P1 M% [" ~6 e866833 SCM REPORTS Extra indentation is left in the left side of the report when the Line Numbers are set to OFF
9 l, j" h8 u+ ~6 X; q% w868618 SCM IMPORTS Block re-import does not update the docsch and sch view
3 O& R3 o$ z( @869971 SCM OTHER Lower level hierarchical block schematics missing $LOCATION values6 u) ]; r: e* H3 M2 v) C
877091 CAPTURE SCHEMATICS DSN file size becomes very large after placing picture and not change after deleting it: R+ f+ _1 m @! B' p2 U
879361 SCM UI SCM crashes when opening project$ A( Q: N9 B s p8 b
879496 CONCEPT_HDL OTHER Customer wants to have “the tabulation” key as separator in HDL BOM.
' H0 _1 O6 R( P# s" f+ A0 q, T883760 PCB_LIBRARIAN METADATA Incorrectly formatted revision.dat file in the metadata folder4 t5 z7 ~5 n& G
885391 SIG_INTEGRITY SIMULATION RLGC data sampling algorithm and w-element interpolation.
. P1 q S5 G- d( S. y4 Q886007 CONCEPT_HDL CORE All the read only pages are called PAGE1 in our hierarchical design
* n5 X$ b3 C: ^( ~889426 CONCEPT_HDL CHECKPLUS CheckPlus does not find single node net
) l/ O L( j( B892375 ALLEGRO_EDITOR PLACEMENT Place Replicate Update disband other groups, irrespective Fixed property added or not.
5 ~9 `% Y1 x2 M" ?892541 SIG_EXPLORER OTHER Export/Import layerstack through the technology file is changing the layer thickness
A/ r( ?+ x( a& ?893743 APD EDIT_ETCH Route behavior when spanning pads not as expected.
& m: c6 m; X2 f& Q894499 SIG_INTEGRITY LIBRARY Tool crashes when moving a cline or selecting the Info icon with OpenGL on./ d1 n" _) B- a3 v
894582 APD SHAPE When making a dynamic xhatch Via shapes surrounding are abnormal.( R5 K9 f" W, W+ e2 I/ }$ y) M! D
895542 SIP_LAYOUT WIREBOND SIP design crashing when moving bond finger using blur mode BLUR_BONDFINGER_PRESRV_CON( z( ~0 Y1 A1 G! {. S
895591 ALLEGRO_EDITOR PCAD_IN Importing PCAD file fails to get to the point where we can map layers
- I' G* ?; R- M, B( k9 \895757 APD ARTWORK Import Gerber command could not be imported Gerber data
" p* P& g4 B% _4 X! r: W6 q895964 CONCEPT_HDL CHECKPLUS The CheckPlus command “getFileSubstrings” is not working correctly4 {( k, e. v5 K+ ~
896302 CAPTURE LIBRARY Pin spacing option in Generate Part from spreadsheet5 R1 E' E+ h1 {2 a# M: B
896428 SCM UI Changed Ref Des value not maintained in DEHDL block when part is replaced
9 y9 F- K" \+ \5 ?% `9 f897362 CONSTRAINT_MGR TDD Unable to create Region Class in Constraint Manager
& b/ c% D* A6 _. z897654 CAPTURE EE_INTERSHEET_RE Capture crashes on adding intersheet refernces in abbreviated format on attached design.* e/ S9 g2 d# Q& o m1 d
898941 ALLEGRO_EDITOR REFRESH update symbol moves refdes location of component placed on bottom side' K* D' E7 w: A; f1 E
899344 RF_PCB BE_IFF_EXPORT dlibx2iff does not provide the component boundary drawing6 n0 B M4 i" g% \' p. Q2 r7 m7 S
900175 CONCEPT_HDL CONSTRAINT_MGR Few Xnets are lost from Match Group after packaging and importing the netlist to board file.
5 c3 I; J1 T R900481 CONCEPT_HDL CORE Genview creates a larger symbol without taking the no. of pin in consideration
; ~- M' j) j2 x+ e9 g& d900813 ALLEGRO_EDITOR DRC_CONSTR With rotated pads, pad (pin - via) soldermask spacing DRC is unreasonable.
1 C- ?: ]/ I4 ]% j3 O2 Q5 J* M900905 PSPICE STABILITY Simsrvr crash and RPC Server unavailable error while running simulation.0 A' H# D( e6 \7 D4 U5 e
901909 APD EXPORT_DATA The "package_pin_delay_length.rpt" with Z-axis delay turned on seems wrong. _4 D/ G" y l( L! Q8 y. g
902133 CIS OTHER The visible part property value are being shown very distant from part graphics on schematic g9 l% h; C3 Z a: I3 b7 Q" T
902166 SPECCTRA ROUTE Specctra crashes when reading in "bestsave.w" file
& Z, S' E# ~. L' e902177 CONSTRAINT_MGR CONCEPT_HDL Option to view the layer thickness in CM worksheet through worksheet customization: E' l- X$ Q' |. B) h& n4 j" p0 l
902463 ALLEGRO_EDITOR INTERACTIV APD crashes when we click ( show element ) on certain components3 k ], Z$ Y7 l/ z, F+ ?" @
902909 APD WIREBOND die to die wirebond crash
6 o6 p( I2 H$ a8 |1 r: @902933 ALLEGRO_EDITOR PADS_IN Pads_in fails while reading PADS ASCII file body
) q, q5 z {( {; {. F4 b# @% [
, R( m0 i9 C3 l9 `& b) ?' ZDATE: 05-14-2011 HOTFIX VERSION: 030% K5 ]0 i& V. V5 ~, R
===================================================================================================================================6 Y( V3 g, |" c& M1 a
CCRID PRODUCT PRODUCTLEVEL2 TITLE5 [$ N3 S* h0 t4 V- }; w1 F; y- n' W
===================================================================================================================================' J( T, |/ x! E
738247 CONCEPT_HDL HDLDIRECT Generate View hangs
" ?. b; T1 C9 `2 @ D& N* \) C803147 CIS LINK_DATABASE_PA Link DB part should not change RefDes of multi package part
4 \% `' k* \' {/ ?5 V6 s837640 CIS GEN_BOM date format of CIS BOM has broken macros of 16.2 in 16.3 version" _. T. N* ?. E' ]; H7 W0 M
838763 CAPTURE GENERAL Deadlock situation is reached while opening BOM reports ("<something>.BOM" cannot be opened)
( U) q0 D, E, w+ m& x3 j( R9 r858245 CAPTURE IMPORT/EXPORT PCAD import does not work in 16.3! ?) D: e: G' d. o N% s7 @( E
860905 SCM UI Part cannot be replaced after it's added
, b2 _4 X) A( b. p2 o9 F6 c9 w) p+ A869528 CAPTURE SCHEMATIC_EDITOR Refdes increment on copying part is not with respect to occurence value.0 M5 w) I1 n, `3 D9 ]$ S5 \/ ~
873402 SIP_LAYOUT LOGIC pin swap for co-design die in SiP
& S# O4 P9 _# G877994 CONCEPT_HDL CONSTRAINT_MGR Assigning ESpice model to active component with Class
) N: { c/ g$ ]9 @; H- O883164 ALLEGRO_EDITOR INTERACTIV Vias marked fanout moves away from position when moving component7 n: k( y: `, C! s; E) K
887442 APD SHAPE Copper pour of Dynamic shapes on Top layer which contains many existing signal traces fails.0 t b8 Y! j i. V4 |7 l
887477 CAPTURE NETLIST_OTHER Other netlist is missing some nets and components after refdes changes in the design
& l& l' [9 E4 o* H" a, g887578 SCM AUTO_UI Component Replace pops-up the DSPANE-204 Message
' H1 `8 v8 y) {887926 SIG_INTEGRITY GEOMETRY_EXTRACT Field solution failed if diff trace on bottom doesn't have reference plane.! A" \% R2 ~$ T
888414 SIG_EXPLORER OTHER View Trace Parameter display the thickness of dielectric incorrectly.
, Q8 ]/ O. }0 M7 s2 g5 p+ ^888600 CONCEPT_HDL CREFER Cross References not added to Schegen schematic
1 P, f6 I! d' L7 b9 T( S* m888804 ALLEGRO_EDITOR OTHER Fillet will become static shape after import from partition board.
) T& n, o5 H: s: h( V888945 CONCEPT_HDL OTHER unplaced component after placing module
" y& J$ R/ ?" h: U! m889365 SIG_INTEGRITY GEOMETRY_EXTRACT top/bottom trace impedances extracted to sigxp are wrong in 16.3
% C7 V* R+ c4 Y; E L889404 ALLEGRO_EDITOR OTHER Incorrect pad size for Top conductor padstack written to column 59-62.
. l/ I3 B9 j% H0 q889636 ALLEGRO_EDITOR MANUFACT Incorrect spelling of "Visibility" in "Film Control" tab in the Artwork Control Form
4 Q1 V, N% W8 b& n891235 F2B PACKAGERXL Packager crashes without creating a pxl.log file
7 ?. }3 V! t2 ?891856 ALLEGRO_EDITOR EDIT_ETCH crash when sliding diff pairs, m. { f8 t5 w- ~8 L, K( F( q" y3 a
892455 ALLEGRO_EDITOR SYMBOL Why the overlapping pins are not reported with DRC?! |1 _3 q8 N, G" d2 i$ q6 ?, _. _
892766 APD WIREBOND Excuting Finger moving cannot push aside finger to move with together by shove all mode
' I! Z Q7 l. g7 ^+ x892907 ALLEGRO_EDITOR DRC_CONSTR DRC not reported for etch_turn_under_pin violations! \# M; [( Q7 O- R) O
892991 APD BGA_GENERATOR BGA Text In Wizard creating two refdes text at the same location.
1 b, ?; L5 f1 E% X& v" \! N5 a893295 APD WIREBOND Why move wirebond command does not shove wirebonds? This result in drcs.
% Z9 z/ l3 A, @' U) K0 i2 v$ I) Z: U& J# q( G
DATE: 04-22-2011 HOTFIX VERSION: 029
8 O" N3 Q1 T! W===================================================================================================================================
+ \, \8 \6 j3 Z% S; x) XCCRID PRODUCT PRODUCTLEVEL2 TITLE" G& k3 A& b" V X
===================================================================================================================================# w$ k7 L1 y) }: J
789198 CAPTURE PROPERTY_EDITOR Newly added user property to a symbol can not be moved on the schematic page.1 j6 j5 ?' p- D: F
812501 CAPTURE NETLIST_OTHER Extension of PADS netlist is .NET in V16.3. It should be .ASC.0 ?# f6 F7 V- d. u: V
842161 CIS GEN_BOM CIS standard BOM taking long time O& s1 _* r4 z$ r* _
844125 CAPTURE NETLISTS Normal and convert view placed in same design don't get netlisted due to duplicate power pin names.
# z0 H- c' j% |' |9 l847688 CAPTURE PROPERTY_EDITOR Property Editor changes selection on Display" d8 w) \5 P( M4 X+ T# S3 ?
851044 CAPTURE GEN_BOM "Export BOM report to Excel" does not appear in the Standard Bill of Material Window.2 u& j" h4 h. A' G0 C) ~ P
862785 CAPTURE NETLISTS RINF netlist with net attributes generetaed by capture 16.3 is not getting loaded in CADSTAR tool
/ M/ O% C- X/ Z7 d1 P868118 CAPTURE NETLIST_ALLEGRO Differential pairs not getting netlisted in hierarchical design.
; G5 X- Z; E( A1 y5 H: d' i880219 CIS GEN_BOM Standard CIS BOM does not viewed properly if underscore presents in Part_Number property: b: j. D M5 o6 H
881792 ALLEGRO_EDITOR SHAPE Cannot Delete the Islands on the shape. No Error reported.: q5 v+ A: H4 c! i
882128 SPECCTRA HIGHSPEED Difference in length report between Allegro and SPECCTRA1 K, a: k& g3 \3 D& W
883224 SIG_INTEGRITY SIMULATION crash while reflection simulation from Constraint Manager
$ g6 ~; l4 F* t% g2 O! k883291 SIG_INTEGRITY OTHER Z-axis delay causes incorrect actual values for delay/ B! C0 U- i7 f; J2 L9 h' ?
883971 APD EDIT_ETCH APD crashed when I tried to add cline in (-6674.79 -7506.74) via.# b/ O% s( g' x% M, r
884061 CAPTURE SCHEMATIC_EDITOR multi-line text zoom doesn't work correctly0 Z; D& J0 ^0 o8 o
884181 ADW DBEDITOR Parts get released anyway without any errors flagged.1 K" L+ K% W; z* d( [# z
885019 CAPTURE GEN_BOM Create BOM causes Capture crash with include file, M2 q7 s0 q$ g; X. ?3 A5 R8 y3 \
886437 ALLEGRO_EDITOR SHAPE Change of behavior of NET_SHORT between 16.2 and 16.3
4 s9 C7 X' {/ Z) \) g1 Q1 d6 U887190 ALLEGRO_EDITOR PADS_IN getting parse error during PADS to Allegro Import
; h; ]% E/ v$ Q; n; V: K7 k6 R887348 ALLEGRO_EDITOR MENTOR mbs2brd translator crashing without any error message in attached testcase -v16.3s027% @- C) f% v' O( \
9 d- g% `5 v4 r; S6 QDATE: 04-8-2011 HOTFIX VERSION: 028" [" k* W0 P( H1 w! F9 N9 Z
===================================================================================================================================0 W1 a% n6 r8 e# k2 w! F( k) ]
CCRID PRODUCT PRODUCTLEVEL2 TITLE+ e: K! Y" a* u* X! e4 {9 _
===================================================================================================================================' W. a( d6 N2 D' P# C2 F# }
704398 CONCEPT_HDL CORE In Windows mode basic shortcuts do not work when in German language, j& x# K2 U( V' }/ X7 d
771137 ADW LRM LRM reports 'Injected Mismatch' for a value based on capitalization of ptf value
2 o: w2 N; [, W872547 CONCEPT_HDL CORE Document schematic - Published PDF is missing Bookmarks, |5 r" \, b% j
875001 CONSTRAINT_MGR OTHER Click on the Constraint Manager selected net filter icons crash software.
4 u, ^) J' l s) C9 H z3 f875039 CONSTRAINT_MGR ANALYSIS RPD margin is not calculated in 16.3! y& z% Y. V; n4 y
876275 CONCEPT_HDL CONSTRAINT_MGR Constraint Manager not retaining target net
" r; Q9 U3 u6 Q; g877912 APD DRC_CONSTRAINTS Shape to Shape DRC seems to be behaving inconsistenly above 90 um spacing on mcm database.. l% [8 X7 ?, w. I; [. y( M# I3 ]6 x/ M
878022 CONCEPT_HDL CONSTRAINT_MGR NO_XNET_CONNECTION is not working unless defined on last discrete before receiver) u: V9 W4 ^, l; `) T
878519 SIG_EXPLORER OTHER View Trace Parameter - stripline trace model display incorrect distance to the reference plane5 Q, ]+ l2 |0 n) j
879529 CAPTURE NETLISTS Misleading bus/pin ERROR [NET0081] message from PSpice netlist
* l6 L* o4 D6 Z' O881455 ALLEGRO_EDITOR INTERFACES Some Drill Figures missing while Exporting DXF# L& H$ q* }3 J( c4 ^, T9 j
881711 ALLEGRO_EDITOR SCHEM_FTB Spacing constraints(Net Class) from schematic are not transferring correctly to the layout
* O" K1 l& A2 `, s882277 ALLEGRO_EDITOR DRC_CONSTR Get Bogus (false) "Thru Pin to shape spacing" DRC for Oval slotted pads." ^5 g( h' M* A% b1 q4 J) j
882408 SCM SCHGEN Export physical fails due to netlisting error with the ASA exported schematic
& w. o) Y O5 v" u7 {- }4 j882796 APD OTHER GDS stream import results in a set of bumps misplaced... possibly rotated 90 degrees M$ M. U& R5 U; }" i5 i! {4 v
0 X; D* U% o! p5 P9 B1 PDATE: 03-25-2011 HOTFIX VERSION: 027
1 s* V5 ~( E5 m/ R===================================================================================================================================
: U; d# n" ^# N' [8 [CCRID PRODUCT PRODUCTLEVEL2 TITLE: x, {* i7 }4 r& C9 M
===================================================================================================================================" }+ ]# Z2 ^2 a
820901 EMI SETUP Request EMC system.conf file that can be read from CDS_SITE.' I4 l) C; m. {# \5 ~
861999 ALLEGRO_EDITOR DRC_CONSTR DRC hang after padeditdb: v# O% _9 |! b
862463 CONCEPT_HDL RF_LAYOUT_DRIVEN Rotating and Mirroring RF components in DE-HDL requires RFFLIPMODE property to be correctly updated
% P0 D2 x. a3 w. ^7 K1 B867223 ALLEGRO_EDITOR SHAPE Shape fill disappears when Negative shape is converted to Positive in Cross Section
1 b7 _/ \/ P$ h9 S8 Q- t868733 CONCEPT_HDL ARCHIVER ASA Archiver not saving the entire design.
6 J9 Z2 Z5 E; G- _' Q/ e871548 ALLEGRO_EDITOR MENTOR Shapes missing after mbs2brd translation8 X* {" Q- g |; C0 G! d- w
872003 SIG_EXPLORER SIMULATION TDR simulation results were different between 15.7 and 16.3.
7 l4 k _- q- E: x4 P* v) u2 D872464 CONCEPT_HDL CORE DEHDL script works in SPB16.2 but not in SPB16.3! F; M6 J0 U4 n0 u( B2 G6 L
873772 SCM CONSTRAINT_MGR Importing a block results in subblocks coming in without properties% B' L2 E5 D4 v1 _+ I! p5 K3 d% @
874335 SPECCTRA ROUTE Route Custom crashes SPECCTRA after routing for some time during "Running Route Phase".
]% g, J |) A% e5 U874989 CAPTURE SCHEMATICS Schematics jumps to another page after a mouse click
% `6 I0 G, ~( b, G875161 CAPTURE NETLISTS Creating Allegro netlist hangs Capture T0 [ F$ m' {/ J$ w! H8 u4 v
875411 ALLEGRO_EDITOR NC NC drill produces Error processing extract . Program terminated. d) _3 U0 p8 a
876004 ALLEGRO_EDITOR SHAPE Unused pad suppression problem in Allegro v16.3 since S020~S0243 B: k% {+ U9 C# J' A L" P6 V; S
876045 ALLEGRO_EDITOR SHAPE Oval hole drills do not void shape with hole shape drc when the regular pad is smaller than hole+ l& }) W" a3 n* P, T3 A
876168 SPECCTRA_MENT_ IMPORT option to have a switch to prevent merging of plane layers during mbs2sp
6 `! x l2 a- e S4 ~9 _8 t876210 ALLEGRO_EDITOR SHAPE When updating shapes to Smooth the tool will hang.
; [+ |8 s) J; ~, C; l# l) r876284 ALLEGRO_EDITOR DATABASE Executing SKILL file crashes Allegro8 X0 G. K8 e9 C! b1 i9 s/ l
877057 ALLEGRO_EDITOR MENTOR Footprints are shifted when importing from boardstation0 F6 @# ^: B; Q4 p h1 K2 ?' S
877549 SIP_LAYOUT WIREBOND Wirebonds not moving correctly when on an Interposer smaller than the die.' a4 p [4 [5 _8 [# G: i
877862 APD WIREBOND APD crashed when add Wirebond without any dump and cannot record script.
- p9 D+ R4 w. Q5 C$ a. ~7 ?878199 CIS DERIVE_NEW_DB_PA Change in Regional Setting causing problem in derive database
0 {9 N. _/ k4 L878216 APD OTHER stream_in - Stream file scan failed
6 F* w/ `2 r1 ^) R& i3 @878400 APD WIREBOND unable to add a wire bonding on few die pad8 Z! t7 [# }1 X1 v- a$ s- `
4 u3 X5 @0 Y7 X! t, |1 cDATE: 03-11-2011 HOTFIX VERSION: 0261 [0 H* v' a5 d( o0 m) l4 o
===================================================================================================================================
6 H9 j9 ^4 E! `9 s. E- ACCRID PRODUCT PRODUCTLEVEL2 TITLE8 \5 H# \) A! Y/ {4 o# g$ A2 y9 }# D
=================================================================================================================================== z5 [5 A- A, s* j% ?! f/ H
851882 SCM SCHGEN Multiple issues with the ASA generated schematic in preserve mode while using square bracket
$ u/ M/ H+ s5 y% d852063 ALLEGRO_EDITOR EDIT_ETCH What is being displayed in the HUD when a percentage is specified as a tolerance?! b& C" C, N) S+ h1 u5 T7 W
854502 ALLEGRO_EDITOR DRC_CONSTR DRC not detected until DBDoctor is executed. Status form and sum dwg report are incorrect. H: O- }; [8 Q) G; U8 E* @ n" z$ e, v
856797 EMI RULE_CHECK Arc segments were detected as warning by bypass_plane_split.
. `7 n) J, J4 ]0 }. i- N d859213 PCB_LIBRARIAN CORE $LOCATION size in PDV and DEHDL differ$ L6 q1 x8 V& L) H0 `. [
860772 ADW PCBCACHE Save Shopping Cart (pcbcache) is crashing component browser
0 ~. I9 B0 r+ V& X5 z862259 SIG_INTEGRITY FIELD_SOLVERS EMS2D run twice during View Topology.
8 J. _* ]: |* Z! G( ]865158 ALLEGRO_EDITOR SHAPE Shapes are not voided with Dynamic Shape Fill modes with Regions
" J ~) }' r+ q865295 PCB_LIBRARIAN CORE Part Developer crashs with symbols having Japanese notes
( ^5 O: \, Z, z% s. f866095 PCB_LIBRARIAN EXPORT_OTHER Export DE HDL part to Capture Part Crashed) G% q R& j/ D" W' |
866835 SCM UI User arguments not used over project arguments for new tool) F( e9 _3 [) V# q2 |7 L
867102 CAPTURE LIBRARY Incorrect pin number gets assigned to pin if a PDF is opened before writng the pin number.
& R9 o1 ~( `+ g; g868092 CAPTURE GEN_BOM Capture BOM in V16.3 is different than that of V16.2 for attached test case.2 ~* @8 z; A: L) h) J/ d
868517 ALLEGRO_EDITOR ARTWORK A pinhole was made in the artwork file.
, p7 _0 c% j4 v868646 ALLEGRO_EDITOR SCHEM_FTB Change in the PIN_GROUP at the chips level not propagated to the board file does not allow the swap0 K7 O3 D- L0 x' v* C4 d6 }1 E% v
868844 PCB_LIBRARIAN CORE BUBBLE_GROUP with no value causes problematic symbol, D! n0 H9 Y$ _ u; ^7 M: t$ V
869326 CIS DESIGN_VARIANT View Variant is not showing part as Do Not Stuff
; ]6 G/ O7 H! m4 q p ~6 S869547 ALLEGRO_EDITOR SCHEM_FTB Error while parsing the alternate symbol% ]+ i) }2 n% ]) u% v$ d8 m, q
869931 SIG_INTEGRITY OTHER DML Library Management rewrites library longer then 512 characters into multiple lines.
" _. f! k2 V S# s3 f8 M869960 F2B PACKAGERXL PART_NAME property added to Export Packageable schematic parts5 b$ f( B) a. M4 \# x
870392 APD EDIT_ETCH Route > Slide not performing as expected in 16.3
/ {' P, @5 I/ ?; r6 E: E870704 ALLEGRO_EDITOR PARTITION 2nd import of parttiotion unplace components in master+ z$ Z" P0 c/ [% Y9 X6 ~
871177 CAPTURE LIBRARY Keyboard shortcut for closing the Place Part window
( f1 m2 C, l- \) T/ j871552 PSPICE SIMULATOR Pspice tool crash# V4 y t% B# c9 c) {5 b0 c+ @7 \
871643 ALLEGRO_EDITOR INTERFACES IDF in batch and GUI for dra files fails to calculate extents correctly
{: i6 b, Z. z( ?( A. r) W$ \871968 ALLEGRO_EDITOR COLOR After using Clear All Nets, Color Dialog box needs to be reopened for adding custom colors.. ]3 @( K; r3 F, i( C
872352 APD WIREBOND Move Guide paths crashed APD.# k9 l5 X! `& J) d: l& T9 q
872380 CONCEPT_HDL COMP_BROWSER DEHDL crash when editing the ppt_optionset.dat file from Part Manager.
6 A' N& O7 n3 _: ?% _872450 APD WIREBOND Wire to die edge angle remains highlighted in red for wire bond status window in v16.33 ]; v: F9 A) ]) H
872787 APD WIREBOND Some Unused Wire profiles be purged but still existing in Bond Wire Profile of Color Visibility?/ [* D8 |% Z" `! }6 u6 B
873217 ALLEGRO_EDITOR TESTPREP Testpoint generation not working correctly
) c: \1 F/ y0 M$ [1 ^ M873500 APD REPORTS Total Plating value is 0/ N) T) }# @/ s; {
873505 APD MANUFACTURING fillet size changed when recreate Plating Bar. R' K$ m |& o5 g a
873600 APD OTHER When attempting to Display Pin Names the tool takes a very long time.( K4 @$ `- z2 i- s
874341 ALLEGRO_EDITOR OTHER "Gloss>Convert corner to arc" command made an unnecessary circular arc.7 R' n7 c! }, H9 ]# W G
1 U( t9 A N6 [DATE: 02-26-2011 HOTFIX VERSION: 025
$ f: U0 K! }/ J% V5 Y===================================================================================================================================
9 l Q2 C8 q1 B" e- [6 v- RCCRID PRODUCT PRODUCTLEVEL2 TITLE. N' T. K& Q$ V, l6 V: k7 J( T
===================================================================================================================================8 K4 |: e0 U6 _. K" [
746063 CIS OTHER CIS Query Does not display initial search results
# `8 f; s2 s) e779588 ALLEGRO_EDITOR PLACEMENT Symbol outline not rotated with component.( K' U5 j0 [# M. i; C
805616 ALLEGRO_EDITOR ARTWORK Allegro produces warning about database extents exceed film size
9 D. o$ c+ {$ O" E843145 CONCEPT_HDL CORE Cannot copy grayed out properties in the Attributes form to the buffer9 {8 X! T' v( b) j* M* e
845607 ALLEGRO_EDITOR EDIT_ETCH Sliding with arc gridless enabled leaves extra segments behind and 45 degree segment.
* E9 q' N e3 i6 P! q* E850428 SIG_EXPLORER SIMULATION SigXP failed to simulate the topology with designlink.
0 L6 l! _ K6 s% Z% b853665 SPECCTRA CHECK Scheduling violations reported incorrectly.
$ b3 f$ V- i6 O$ n. K% u855534 CONSTRAINT_MGR OTHER formula result does not update when length changed8 M% F ?. \5 y6 L) `
855793 CONCEPT_HDL CORE Rename Pin on Block is not working in DE HDL with HF 21
O' Q8 v" k$ j. f856306 ALLEGRO_EDITOR INTERACTIV Modifying pad instance corrupts db- ~$ Z7 I8 z! O5 E7 p
859437 SIG_INTEGRITY GUI Log Scale setting of EMS2D was cleared by re-open design.$ U. J3 e3 M! I6 ^1 n4 `
859850 SIG_INTEGRITY GEOMETRY_EXTRACT Allegro freeze during topology extraction with EMS2D.% d! v1 k( ^6 `6 ]* C: x
860366 CAPTURE CONNECTIVITY Netlist is different in V16.3 than in V16.23 B* t+ p8 V# B8 P0 j
860809 F2B BOM Bomhdl failed to create the design view check for existance of the packaged directory2 C7 v9 N- h* S
861027 CONSTRAINT_MGR CONCEPT_HDL Unable to synchronize the constraints
! {9 r# {! S- q$ |* M+ @* r$ @862137 SIP_LAYOUT OTHER SPB 16.3 SiP Logic - Derive assignment is unable to resolve connectivity of shapes
4 |& s6 c# @4 s' |8 }862980 ALLEGRO_EDITOR EDIT_ETCH When sliding a via the potential DRC behaviour is inconsistent.) r+ M: U2 k" y7 i) r! f) r7 R% c
863400 SPIF OTHER SPIF does not translate the oblong pads correctly E, @7 ^3 e4 i, S9 L
864363 APD REPORTS The Wirebond report is failing because there are Non-standard Bond wires present.
9 a& w+ ^# h1 T% r+ f864621 ALLEGRO_EDITOR DATABASE Database corrupted after adding layers in Cross Section and trying to save the board file.
, g' `. _% H4 H0 H% b% g865875 ALLEGRO_EDITOR MENTOR mbs2brd translator results in broken/unrouted nets even though the BoardStation design is fully routed% A* e+ U8 f; D" k2 d, e
866202 CONSTRAINT_MGR OTHER Worksheet File import fails with error message due to character limit
: A8 |2 }* M+ b) g" T866726 CONCEPT_HDL CREFER TOC (table of content) not generated in schcref_1 schematic (CREFER flattened output).
" y; L5 K7 |. [867238 CONSTRAINT_MGR INTERACTIV Split Xnet for diff pair crashes PCB editor1 B+ W9 R2 Y+ g/ C2 O
867696 SIP_LAYOUT DIE_STACK_EDITOR When doing an Info on this design it will crash.
6 O+ q8 b! e( ~. q+ W5 c) r867742 ALLEGRO_EDITOR DATABASE Thermal Pad view for shapefillet on Negative layer" F7 {& N9 b' \
867842 CAPTURE PROJECT_MANAGER Capture crash with 'Open File Location"- F6 ~+ G `, u- a6 p9 Y
868306 CAPTURE CONNECTIVITY mirror vertically removes junction creates extra nets6 o5 n4 X7 k3 `- M. w
869758 CAPTURE GENERATE_PART Generate Part option "Copy schematic to library" does not copy schematic page attributes7 r6 B+ C! s; J& w' y6 h6 {$ w
869941 ALLEGRO_EDITOR PADS_IN PADS_IN unable to import Power PCB 2005.0 file in 16.3 but works with 16.2
9 T3 j# z: p; o6 c+ v2 O870301 SIP_LAYOUT SHOW_ELEM When selecting Info and then a rectangle shape, the tool will crash.: C; b2 D$ b' r+ L# l( U, d
8 g: V4 W4 K$ a% }3 P6 V, ]DATE: 02-11-2011 HOTFIX VERSION: 0246 o8 x" E8 e- `3 S) D3 `
===================================================================================================================================# z0 a9 C/ o' W7 K# \- |
CCRID PRODUCT PRODUCTLEVEL2 TITLE
5 R* ?0 f* h7 i; y0 a& A7 j===================================================================================================================================; J y$ z$ O/ t7 w* u; `
858051 ALLEGRO_EDITOR OTHER Allegro's Help>About... System Info... doesn't work on Win7
* y; S1 _; a7 B o1 Z862703 ALLEGRO_EDITOR DATABASE crash when doing a save_as+ Q8 s* O! E, l: J0 k+ A% h
866288 ALLEGRO_EDITOR NC Drill customization table won’t let you add characters in lower case5 b0 h" [' q# R+ D7 p P
866310 ALLEGRO_EDITOR DRC_CONSTR Testprep doesn't create a DRC for Testpoint > Component6 X7 @: y" O, ^5 c: d
866652 ALLEGRO_EDITOR SCHEM_FTB Allegro Spacing net class not updated with new logic
. P8 K8 M9 ]* k) j! Q/ v9 C) D2 ]* k' X% ~! p! v' a" v
DATE: 01-28-2011 HOTFIX VERSION: 023) c, q/ g* C6 v- J8 R; O
===================================================================================================================================
0 W1 c, C# L9 p8 OCCRID PRODUCT PRODUCTLEVEL2 TITLE
) v2 m7 g8 c6 l% c* r! L* L+ b6 n===================================================================================================================================
1 {3 N- }) k% I; V! z739067 SIG_INTEGRITY SIMULATION about modal delay of diff pair net
: K# t6 \; U1 M' `- s! J0 Y7 d# S4 z742237 CIS FOOTPRINT_VIEW 3D Footprint view in CIS Explorer
' q1 K4 S/ h" k t6 i. h762702 CONCEPT_HDL CORE Unable to change color settings" S1 B6 e, T7 U* }- ~; u% } Z' A$ o
800333 CONCEPT_HDL CORE Text change cursor not working on Solaris and Linux
- M3 h: Q, W# P; B4 I' v837479 CONSTRAINT_MGR DATABASE Import dcf with custom column cuases a problem
. K* |8 Q) j! `+ X# v4 T3 v: x846679 ALLEGRO_EDITOR SHAPE Through Pin can not be voided correctly in dynamic shape.: m+ y. ~& R5 |/ `, q
852255 CONCEPT_HDL COMP_BROWSER DEHDL crashes when adding part from cat file0 D0 l; e8 B8 T& D; p
855553 ALLEGRO_EDITOR DRC_CONSTR Multithreaded DRC shows different DRC counts
+ {9 M; E" Q9 L856459 SIG_INTEGRITY GEOMETRY_EXTRACT No waveform was output if users set the Via type to Analytical type
9 o( }% ]( r. }8 u857030 SIG_INTEGRITY OTHER Inconsistency when signal model has "legal" spaces within it.
6 K7 g1 R. Y ?" K5 l! t857120 APD WIREBOND Enhancement for Redistribute Fingers.
$ i1 H" i5 |# B0 x+ [+ ]. j857165 SIG_INTEGRITY OTHER Model Name Changed Warning appears every time after Export Physical
7 ^' ]" c( v) g2 |- w857237 ALLEGRO_EDITOR SCHEM_FTB UserDefined mapping mode
- ? C- y* K$ H% r1 L) a/ A1 k2 d857650 ALLEGRO_EDITOR DRC_CONSTR Hole to line DRC unavailable on inner layers for mechanical pin with no regular pad definition.% f* y$ c1 g* k
858046 MODEL_INTEGRIT TRANSLATION Ibis2signoise fails translation when the unit of Pin section is "ohms".
$ F- t! a; F9 v" \3 p1 q, @858154 GRE DETAIL Net not following the plan during Plan Topological
R+ _. a3 w$ O858192 SIP_LAYOUT SHAPE Program crashes when attempting to add polygon shape.& C3 q- X w0 I0 e
858307 CIS DESIGN_VARIANT Homogenous part not showing correct DNI on schematic
% \1 Y8 ?% V# D& N! M) a858624 ALLEGRO_EDITOR PAD_EDITOR "Save Padstack to 16.2" command is needed in 16.3 pad_designer.+ b1 ^# D8 Z0 G
858814 ALLEGRO_EDITOR MODULES place module not placing figures present in mdd4 B, a6 ^. @5 P! m
859514 APD IMPORT_DATA Die Text-in cannot change unnamed Begin Layer to selected pad layer in step 4
$ U. f0 K m- D% V& v9 d859640 ALLEGRO_EDITOR PLOTTING Shape based pads not output as polygon in IPF
3 B1 E4 j3 b: w# S: O859680 ALLEGRO_EDITOR DRC_CONSTR Multithreaded DRC shows different DRC counts! P6 E& U! j/ T: ]
860069 ALLEGRO_EDITOR OTHER Import Logic hangs then crashes and displays Netrev warnings. |" w9 O) P9 s' i/ i- l# H
860535 APD DXF_IF a2dxf got an error message
1 ~8 {1 E4 B1 H. x860860 CONCEPT_HDL COMP_BROWSER Component Browser freezes9 e" h# w% M* e9 q( \4 j
861295 CONSTRAINT_MGR ECS_APPLY Diff pair PCSet value overrides ECSet values in constraint manager spreadsheet.
/ B& u' z! l: e3 R$ u! z862279 SPIF OTHER running 'Allegro PCB Router' Crashes
* e5 ]$ y: N! D, n$ ~# e0 H0 M7 d- M8 s; [7 H
DATE: 01-14-2011 HOTFIX VERSION: 022
$ j7 P! Z) e2 ?===================================================================================================================================7 ]7 [2 v% S: | ~6 U
CCRID PRODUCT PRODUCTLEVEL2 TITLE0 j8 x5 v, \ z6 @1 N8 z) W
===================================================================================================================================
7 d8 l$ V2 p3 ^372240 CAPTURE SCHEMATIC_EDITOR Allow component move with connectivity change should be checked by default
) `" t( _! p% d' g# z1 {! i769139 SIP_LAYOUT DRC_CONSTRAINTS Wire to Bond finger rule in the CM needs profile to profile constraint capability
. ^" N1 B- L% [& n/ h772299 ALLEGRO_EDITOR GRAPHICS Via doesn't get highlighted properly with OpenGL disabled0 d$ z% i$ l: Z- M3 r: `
830519 ALLEGRO_EDITOR GRAPHICS Disabling openGL causes highlihting problems.
: C2 a, g0 V. k M% S2 T833981 RF_PCB FE_IFF_IMPORT DE HDL Import IFF unit conversion and unit display in RF schematic* }2 ~# v+ B8 _8 p- m
835698 RF_PCB FE_IFF_IMPORT DE HDL Import IFF to assign simple sig_names like RF001 RF002 etc
8 L! |& v, k% p* `- o840094 RF_PCB OTHER dlibx2iff does not translate complex polygon pad3 M. D. b/ v. B) y6 I+ F+ Z0 L# w
844504 SIG_EXPLORER INTERACTIV EMI Regulation setting of the board is not reflected correctly when the net is extracted into SigXP
# Y8 B& v8 f. K4 j846210 PDN_ANALYSIS PCB_STATICIRDROP IR Drop mesh is not correct.2 o3 e% B1 p, Z3 h0 G! U8 o
846228 SIG_INTEGRITY OTHER ZAll and Wirebond calculation in the Prop Delay formula( U7 r; e5 e$ D6 d7 V# t
846259 CONSTRAINT_MGR CONCEPT_HDL Why dont I see the P1_8V_DIG net in CM ?
/ a% b, Q: H# Z847278 CAPTURE TCL_INTERFACE TCL/TK PDF Export Change Page Size% b2 J; h, _0 M2 a& m
847942 SIG_EXPLORER OTHER The solder resist layer was not included in Interconnect Model of SigXP.4 @" T5 q$ Y3 o- {# N1 U
848181 PSPICE DEHDL Model association for concept symbols with a chips view doesnt work! W) J- o! u3 ~; H$ B* ~" t
849707 ALLEGRO_EDITOR MANUFACT Thieving creates unwanted thermal reliefs in this design.; ^2 s2 @8 U' I9 H) U
851070 CONSTRAINT_MGR CONCEPT_HDL The Match Groups are not visible in the CM) t$ }0 ~' r5 ]2 l# f1 W
851171 F2B PACKAGERXL Design will not package with exclude_cdsNotOnSym
/ G/ x% j5 B' v: R/ w851290 APD PADSTACK_EDITOR APD/SiP crashes when the user defined mask layer is edited with padeditdb.
6 Q, X: V9 W. Q6 h) T: s% Q N851477 SPECCTRA ROUTE Allegro Router runs out of memory during route passes
1 B3 k7 a( s9 f! N; i. S* A; e851658 APD EDIT_ETCH bunceback behavior while slideing cline4 ^% w# E: u' v8 K; I1 v
851725 ALLEGRO_EDITOR DATABASE Number of DRC is not consistent on each DRC update./ `6 |/ a- P# L. K! S2 k# S8 R
851789 ALLEGRO_EDITOR SKILL Skill axlAirGap for Via & Text causes Allegro to crash
( }" h" t, u$ J. c1 P8 b852325 ALLEGRO_EDITOR DATABASE Perf advisor doesn't check high pincount devices for RATSNEST_SCHEDULE+ O1 L; A8 S' \; E% T' H( L5 x
852360 SIG_INTEGRITY OTHER Appling toplogy template to a diff pair object reports UserDefined in CM; L2 z. j x/ c* `* W% S( ?$ z
852395 ALLEGRO_EDITOR DRC_CONSTR Same net via spacing broken drc shows up to date
- ^+ x1 m$ N: V+ F+ O852764 ALLEGRO_EDITOR SKILL axlHttp beeps and gives error E - http 425 V1 W; e7 b8 O% J7 B& X6 _5 |
852787 CAPTURE ANNOTATE Tool is crashing during annotation if Ref Control is set
6 b; O9 J9 f9 `1 c" |9 _+ @- y853110 ALLEGRO_EDITOR ARTWORK Allegro Crash on selecting Mfg > Artwork if any Parameter syntax is wrong in art_param.txt8 }+ {- E6 x a8 {
854031 ALLEGRO_EDITOR MANUFACT The stream out data xxx.scf seems to be incorrect.6 s" U, a( o" P% n4 D8 `, J+ x
854246 ALLEGRO_EDITOR MANUFACT Stream out data of Oblong pad is strange.
8 @2 v( X: H6 L% ~. N2 Y& O854293 APD OTHER dynamic fillets were disappeared when open in 16.3.' _4 L4 \9 h% m. C
854356 ALLEGRO_EDITOR OTHER Fillet adding doesn’t check same net spacing rule in both static and dynamic mode.& g$ O8 t/ |5 a
855101 ALLEGRO_EDITOR OTHER Drill figures now smaller than expected
. k# J! g1 Q" K$ }8 r2 b. i6 {855124 APD PLOTTING The "load plot" command did not import Drill symbols(Figure) and Characters in APD.
6 k5 b8 o: w7 B5 N3 v! {855348 ALLEGRO_EDITOR EDIT_ETCH Differential Pairs do not slide to correct geometry
9 ]) A: L, l* {2 W2 ]* }856220 ALLEGRO_EDITOR INTERFACES Export DXF in the 16.3 S021 build rotates some pin locations
7 O' c# ^/ K: Z* ^# l5 r4 @' L2 X856256 SIP_LAYOUT WIREBOND When editing a single Wirebond all wirebonds attached to the finger get highlighted.6 n ^ q4 F! m& z' c
856674 ALLEGRO_EDITOR AUTOVOID drill hole to shape autovoiding clearence is wrong for Same Net Spacing4 f. b$ A5 ~: }4 ?# ^. c- i
! C1 l& C- O5 c8 q7 k4 Z: _" {& |
DATE: 12-10-2010 HOTFIX VERSION: 021% i4 _# `4 q; E1 t
===================================================================================================================================
4 @" M! e3 _1 l! a# iCCRID PRODUCT PRODUCTLEVEL2 TITLE
7 e6 U8 Y. `- j===================================================================================================================================
5 I7 N' m7 f; \7 G+ |708992 ALLEGRO_EDITOR SCHEM_FTB Design Differences fails with Error #5343 m" X: R! U( a0 W5 X6 Y6 i* X3 ]: `
748982 CIS FOOTPRINT_VIEW Respective pin number from schematic does not get highlighted on 3-D footprint viewer.: X0 X: K6 F! w1 t
775788 CONCEPT_HDL COMP_BROWSER Component Browser search is too slow
5 m5 Z; R7 P8 C# |* a. I( r802152 PCB_LIBRARIAN IMPORT_EXPORT cap2cond design translator is also looking for Capture feature string in license - this is break from 16.2% r/ m/ u+ ]. l) }5 A0 q1 G
803910 ALLEGRO_EDITOR GRAPHICS Request Rat like display for REFDES text to component.# P8 \* ^/ E H. q) m6 _9 ?5 r
823599 SCM REPORTS Ability to generate DEHDL style BOM report
# @% |; U0 x6 Q8 {$ ^5 i) J( H826558 CONCEPT_HDL LWB-HDL Module definitions for cells is not included in the simulation verilog netlsit on LINUX
/ ~" p s9 u/ b& g# V828689 CONSTRAINT_MGR OTHER formula constraint lost when Constraint Manager closed/ Q: E; L8 ~+ ~0 r, V
831192 SIG_INTEGRITY GUI Cannot close Analysis Preferences window.
2 ~6 Q a& v; a' y" s9 g831229 ALLEGRO_EDITOR INTERACTIV When mirroring sym PLACE_BOUND shape does not mirror til placed
7 @* C/ T3 r x# u! d832315 ALLEGRO_EDITOR SCHEM_FTB ECO.txt file should not list net names if schematic and board files are synchronized./ u7 d4 m; t: u" o+ G y* W
832644 ALLEGRO_EDITOR DRC_CONSTR DRC error disappears when the size of Constraint region is changed.+ |; p& y# w' d3 y
833061 MODEL_INTEGRIT TRANSLATION Model Integrity IBIS2DML fails to convert data correctly for pre-emphasis using Driver Schedule
) Q i N! b2 Q0 ]# {833487 SIG_INTEGRITY GEOMETRY_EXTRACT Probe sim failed if VARIANT_TO_IGNORE was set.8 I2 C8 G# z% x9 j3 m$ v
833922 CONCEPT_HDL CORE Move pin on blocksymbol using Block -> Move Pin command change the Pinname textsize
0 q3 h# H' f8 T1 g5 J834103 ALLEGRO_EDITOR DRC_CONSTR dynamic diff phase highlight not showing4 J+ K, R! g# n) k
834868 SIG_EXPLORER OTHER View Trace Param crash if sweep param was set for loss tangent.
9 B# y* d w; S) A3 w835006 CONCEPT_HDL OTHER Locked BACKGROUND directive is changed in DEHDL session
& P' U+ E# T9 Q' k835326 APD SPECCTRA_IF Specctra does not open from APD using Allegro Package Designer XL (Legacy) license: [: ?$ S; \- h. F% G
835622 CONCEPT_HDL CORE DE-HDL crashes when selecting wire having global sig_name in opened block schematic4 o7 Q( X) A4 e
836962 CONSTRAINT_MGR ANALYSIS Simulation will crash6 _" j' e) O7 C. i; Z6 Y
837216 CONSTRAINT_MGR OTHER Custom measurement Rslt lines being duplicated in a different worksheet.
& J; z$ F7 ^8 C3 l7 L+ o837322 CAPTURE LIBRARY Library is not getting freed even when user has closed it.
4 I8 ]& r3 e0 T839517 CAPTURE MACRO Macros (for place part) created on 16.2 version works differently on 16.3! E! T5 ^, ~7 r; \* w" {; ?
839749 ALLEGRO_EDITOR MANUFACT Drill entries are repeated in .drl files
, P F3 k) u* [/ ]840738 ALLEGRO_EDITOR ARTWORK Shape symbol in padstack moves when Artwork is generated - Break again after fix in 16.06 s7 ]( ?- k! G) Y
841176 CAPTURE ANNOTATE Homogenous parts are not getting packaged correctly in annotation in 16.3
1 E+ L) \$ }' Y& }) ^841355 SIG_EXPLORER OTHER Trace model parameter does not update when linear Range are entered.7 [1 q; U5 W) p# C! I
841730 CONSTRAINT_MGR OTHER Allegro Crashes while working with MGs in CM T8 L( M, `- Y& O) B) l
841759 F2B BOM BOM creates an incomplete output when design packages without errors7 K3 V; D( \7 @: Z8 } |7 Y3 Y
841928 CONCEPT_HDL CHECKPLUS CheckPlus fails when pin name contains _N in the middle of the pin name
- y u2 [& c3 u l8 `/ A( p841991 ALLEGRO_EDITOR PLOTTING Offset of text and line on importing a plt file
) a$ k- M/ X/ X5 ?( U: `842204 ALLEGRO_EDITOR DRC_CONSTR Arc creates false DRC on edge of Constraint Area
6 s! }) k6 e) I2 H8 T2 u843114 SPECCTRA ROUTE Specctra rules file taking very long time to load9 y9 r* I: o# r9 k. U/ H9 D
843254 CONCEPT_HDL CONSTRAINT_MGR Unable to invoke CM from DEHDL CM Crashes with an error Olecs.exe The application has quite unexpectedly/ ~$ _" s# Y' Z$ b! z7 e/ S2 z0 \- U
843518 F2B DESIGNVARI Variant with FAIL_OPEN. w$ a, j- ]( r5 p7 k" z- F7 Z
843933 ALLEGRO_EDITOR DRC_CONSTR Cancelling drcupdate will either hang or crash Allegro3 j& m- {) q! t6 v# G% X& }- d% g! d
844074 APD SPECCTRA_IF Export Router fails with memory errors.
5 o* g" s7 m# Z7 \& J4 L844246 ALLEGRO_EDITOR SHAPE Long Thermal_Relief connecting to XHatch shape
n: ^& b; v1 w- ]# b4 I844355 CONCEPT_HDL COMP_BROWSER User seeing CDS_NA appear when placing component
$ m I) Y, E& F3 x+ ?' |' }* c844381 ALLEGRO_EDITOR SCHEM_FTB 3rd party netin - Pin is connected to net <netname> not reconnected.
' {& Y- u' c, b+ \8 k& t, E844662 SIG_INTEGRITY OTHER Cannot uncheck options in analysis preferences.
; ]" R& n; e& s& E' k844796 SIG_INTEGRITY OTHER Get an error E- Illegal model name. Cannot add model RE_RES_0402-16570580,when doing Auto Setup during Model assignment
2 v# [* ^4 B4 G: q" Y7 v i! ^846172 APD OTHER Cannot generate the dxf file from this database
`- q, X7 |9 a# @7 M846270 SPECCTRA GUI SIGNAL_15 layer missing from the color pallete in Specctra* Q! g6 l3 t! P! t1 B
846352 ALLEGRO_EDITOR DRC_CONSTR Route connect does not select the pin-pair width for routing.4 S- u. Z$ D3 M- B9 `
846420 F2B DESIGNSYNC Design Sync failes due to FUNC_VIEW_FILE missing messages
1 |3 C; B1 C/ d5 s846918 ALLEGRO_EDITOR PADS_IN Pads_in crashes when importing ASCII file, Runtime Error
) W$ I7 S2 t: L+ Q! t# u1 `847079 ALLEGRO_EDITOR DATABASE Allegro Crash while trying to unlock the board file
! |6 \6 H. P! `7 h5 b$ d7 D8 }7 k848143 F2B DDBPI Adding part crashes DEHDL/ N# L( @2 w7 l" {, |: g
848415 CAPTURE STABILITY Crash on Mirror Horizontally1 N- i9 K6 _! m/ a
8 k0 \9 l$ _5 I: u, y; k. I6 f2 M
DATE: 11-11-2010 HOTFIX VERSION: 020- l2 t t/ a( `2 d4 F4 g
===================================================================================================================================0 Y% Q- {9 A. X, `- F
CCRID PRODUCT PRODUCTLEVEL2 TITLE5 |0 d+ q# V! v0 N/ \* v
===================================================================================================================================2 O8 `( I! c) r8 d b- q5 D
501606 CAPTURE OTHER Descend Hierachy does not open first page
8 B. M' X/ I, z0 K5 k7 U+ E* r) X764482 SPECCTRA CHECK Allegro router same net checking different then PCB Editor.
6 I, O1 B3 y% `2 a: @809055 APD EDIT_ETCH Shove Preferred changes trace widths of shoved traces during routing
6 J1 @" J& Q8 q3 `816920 ALLEGRO_EDITOR PLACEMENT Update symbols causing Allegro to crash- x( s2 ^" d& M( x6 N. f6 q: D
826762 SIG_EXPLORER OTHER The rotation of element are different between pre 16.2 and 16.3.3 v* K) V! J3 n' K
827769 CIS FOOTPRINT_VIEW 3D footrpint viewer doesn't shows circular geometry on footprints5 M y& B/ e* I; i
828830 F2B DDBPI LRM does not update Parts which have a ALT_SYMBOLS value Added
5 v% \( F9 W) u) G830319 SIG_INTEGRITY SIGWAVE Sigwave load errors out with "Requested resource was not available" after large bus simulation
/ x% z7 K3 u8 J3 g830359 CAPTURE GENERAL Crash on link Database Part
, ^" L: I" x: Q- J; R. o830627 ALLEGRO_EDITOR DRC_CONSTR Incorrect thru pin to shape SPACING error
6 o( N/ D" E& r. Y' D+ v& ~( ]830716 CAPTURE PRINT/PLOT/OUTPU Capture crashes while printing a Capture CIS Standard BoM with ISR s0017.7 \% Q* j4 B4 ^ p) D' Z( M
830791 SIP_LAYOUT LEFDEF_IF Improve the LEF Library Manager to import passivation layers& F( s M8 J; Z h
831210 CAPTURE OTHER Users get an error message everytime While running Update Cache with V16.3 and V16.2 with latest ISR
2 }/ }+ S* B7 u) N& k' b) B; E831231 PSPICE SCHEMATICS pspice com wrapper error
1 T0 f4 r5 B' p' o, h; I7 B" t831692 ALLEGRO_EDITOR PLACEMENT Application becomes sluggish to nonresponsive when trying to place mechanical symbol
9 i$ E0 A3 }( O, u831704 CONCEPT_HDL CORE ASA stuck in an error condition. R$ I3 M. p( M! f; Z* [
833116 PCB_LIBRARIAN IMPORT_EXPORT Getting LMF-02018 Error while Importing Capture Parts
K( [7 v& N. ?5 D p833433 ALLEGRO_EDITOR TECHFILE techfile in/out round-off a value of Conductivity(Xsection). S8 D$ v" y0 H# m$ B/ \
833921 ALLEGRO_EDITOR ARTWORK Gerber filled lines stick out from filled area on Fillets
; c7 d9 e8 J" C833950 ALLEGRO_EDITOR ARTWORK Artwork process create recrementitious circle for AutoSilk data.. n7 |- A1 k2 ]& m
833975 SIP_LAYOUT DATABASE pad not on subclass5 c" g; l6 e, p3 O8 s
834152 APD EDIT_ETCH Route Slide of a Diff_pair section moves all of the cline instead of just the segment that you want.
/ R$ v* U, Z; a) @! q) d& [834861 APD OTHER package integrity runs for hours. results in no more room in database
1 e7 G! D# g7 f7 m835367 CONCEPT_HDL SECTION Packager-XL reverses the pin numbers of connectors# Z6 I$ f$ s4 Z$ C' d7 [- D
837805 ALLEGRO_EDITOR EDIT_ETCH Add Connect crashes Allegro when routing from a cline (not on a net) through a region.
& X* K9 ~: Y+ N% m) Z838057 CONCEPT_HDL CHECKPLUS CheckPlus crashes with long parameter.2 [4 P' s9 w0 {3 i2 ^" W
838356 SPIF OTHER File > Export > Router Crashes Allegro and dsn file creation stops
' M' }# U* e+ ]/ x' C838521 APD MANUFACTURING When creating pbar some clines are gone.
) I( ~, S' Q( F; w Q838766 ALLEGRO_EDITOR EDIT_ETCH Sliding with arcs making sharp corners instead of arcs.8 m0 Z. l+ h$ ]* b, d) k
838830 SIP_LAYOUT ASSY_RULE_CHECK Assembly rule check flagging a DRC for item not near edge border( j4 x4 P# D/ Y6 v' V
838836 ALLEGRO_EDITOR SKILL Pb to check license with skill core function4 n6 I9 l% Q, F5 l
839218 APD 3D_VIEWER 3D view of this mcm file is not getting rendered and the 3D GUI screen shows up blank in APD
+ e* A4 n& }) @( \* i" f7 F e839362 ALLEGRO_EDITOR EDIT_ETCH trying to slide a bbVia crashes Allegro* }0 m) Q0 b$ H
839984 ALLEGRO_EDITOR ARTWORK Some pinholes were made in the artwork file.
' K- m# i8 E) ?1 [+ I0 p840016 CONSTRAINT_MGR INTERACTIV Cannot manually create pin pair for unspec pins of Xnet.
4 \2 H8 p) [! Q. {. n840455 ALLEGRO_EDITOR INTERFACES IDF exported/imported from symbol have no drill information for pad.
3 B0 |" w2 Y9 n: @* n; L9 P$ h; z841431 CAPTURE NETLIST_ALLEGRO Upgrading from Capture V16.2 to V16.3 some nets get shorted on the schematic page.: w3 [2 o7 y1 S9 Q, L6 g) T
7 D- F. y- n d, x
DATE: 10-20-2010 HOTFIX VERSION: 019$ R! \9 T9 q1 R
===================================================================================================================================, U. y; N7 i1 T& p" w
CCRID PRODUCT PRODUCTLEVEL2 TITLE/ e) r! ^9 ]3 B4 `
===================================================================================================================================
1 e# B: _ i2 ~5 t) s9 `717365 SCM SCHGEN Option for Schematic Block to have the defined Sheet symbol/Page Border0 i% v% c2 d( h" }( P) P
751477 ADW COMPONENT_BROWSE UCB in DB mode does not read local worklib for block symbols( m1 m# U: V0 x8 q Q3 _5 o
792545 APD PADSTACK_EDITOR Can not rename user defined Mask Layer in APD/SiP.9 x) J& i! m( \! K
813436 SCM OTHER Option to have a directive in the cpm file to distinguish an SCM project from a DE HDL Project2 j$ Q! |0 i4 z# w/ j) k8 i; R* C; w
820640 SIG_EXPLORER OTHER SigXP Crash after doing Transform For Constraint Manager
+ p) P, M, k' D S! n" d824527 CAPTURE PRINT/PLOT/OUTPU Part ref-des resets when trying to take variant print from Part Manager6 f$ K; Q h; L
824688 SIG_INTEGRITY GEOMETRY_EXTRACT PCB-SI crashes when running more than 2 simulations
) ?5 q, h3 l, c0 q W826571 CONSTRAINT_MGR OTHER Import of .dcf crashes in 16.2 but not 16.3$ T% p, ?2 g k, ]; H; i8 z* L0 X
826626 CONSTRAINT_MGR OTHER Creating a Netclass from a custom worksheet breaks the Netclass object upon the next invocation of Constraint Manager.
8 c9 P2 {0 k/ X, H! ]5 D826799 SIG_EXPLORER SETUP_ADV can not close Analysis Preferences form when Advanced Setting button is opened and closed once
/ G. {- I7 v* k3 y1 D B: j827375 ALLEGRO_EDITOR DATABASE Need to check why Net class assigned on the Net are not visible in CM
& y! `; p( A! G0 S( p& w0 I* |( C' E827521 CONSTRAINT_MGR OTHER Allegro crashes when trying to open Constraint Manager.
& v0 E: c, \- U3 i827713 SIG_EXPLORER INTERACTIV Cannot move object by click and drag after RMB>Note.2 H5 C2 R) O: s- F5 X
828803 CIS UPDATE_PART_STAT Crash on update part status from Part Manager+ }* Z9 D% X: s/ T/ \# `% O$ U
829005 SIG_INTEGRITY FIELD_SOLVERS SigXP crash when RMB click on the Trace Model with EMS2D.! w$ D: f& r% u, {' v
829008 SIG_INTEGRITY FIELD_SOLVERS SigXP crash when RMB click on the Trace Model with BEM2D.
; Z D5 H, t0 u7 p' O; w829233 CONSTRAINT_MGR UI_FORMS Physical Csets applied on a diffpair is not followed while routing, though visible in CM.
" f0 I1 B; V; A9 I3 B" ]829340 CAPTURE LIBRARY_EDITOR propertries are shifting after being placed1 e8 [7 N+ u' A+ @' p* H5 s
829747 SIP_LAYOUT DIE_EDITOR Move pin incremental coordinate. o6 v, C1 R# s( n
829991 SIP_LAYOUT OTHER The "axlAddAutoAssignNetAlgorithm" function is missing from the Allegro SKILL documentation.6 j6 C8 x5 k2 E% s3 F
830509 APD ARTWORK The measured airgap aren't between features in the design aren't consistent in Import > Artwork.
7 Y' m; g R" x7 A$ i3 ]830809 ALLEGRO_EDITOR TESTPREP In the testprep report the Pin type is getting appended with net name5 s6 {% v9 p- Z2 g5 P
830907 SIP_LAYOUT DIE_GENERATOR SiP will crash when adding a Standard DIE using the Die Generator.
0 l& o+ I0 U+ L9 _& S831176 ALLEGRO_EDITOR MANUFACT Testprep Resequence crashes this design.- p5 n4 ~* Y! i; u! Y& |
831199 SIG_EXPLORER OTHER error in _sxUtilGetAllegroPart message was displayed.
, P; O! T3 P) I0 n* u. s+ t+ m831610 ALLEGRO_EDITOR EDIT_ETCH Sliding with Diagonal Entry (45 Degree) is sliding the the adjacent vertical segment when Constraint region is present
# }: p" D! t0 T5 f2 w* @831946 ALLEGRO_EDITOR OTHER Cannot re-open Command Browser if it was closed by Undo.
4 e6 ` L& U! b0 P* U6 Y2 j831998 ALLEGRO_EDITOR SHAPE Allegro crash when user execute shape vertex add command.
4 [, `5 M# B5 p! x3 P6 d832059 APD SHAPE Shape does not keep Shape-Via(w/ Fillet) spacing.
, U6 h! a- H9 w& h4 G1 G832169 ALLEGRO_EDITOR EDIT_ETCH Sliding with Diagonal Entry (45 Degree) is sliding the the adjacent vertical segment when Constraint region is present5 {& t5 i* f4 b0 O4 } s
832197 ALLEGRO_EDITOR EDIT_ETCH Sliding diffpair slides adjacent segment
& R2 Y7 P8 L/ R6 e7 c T- k8 G$ w; t832613 ALLEGRO_EDITOR EDIT_ETCH Adding microvia and bbvia crashes allegro at location where overlapping shapes exist on other layer& Z2 _! z+ o) x
832922 ALLEGRO_EDITOR PARTITION Import partition board crashes Allegro.
' Z+ P% S" z8 l; \4 X0 X833127 ALLEGRO_EDITOR SYMBOL With 'unused pads suppression' the padstack (clearance) does not get rotated in the internal layer; J/ Q3 ?7 L* s6 q% Q
833251 ALLEGRO_EDITOR SCHEM_FTB Power planes on Layer E3 and E18 change to dummy net after Refresh Module.
& K' D* E" [( B1 n833586 ALLEGRO_EDITOR PLACEMENT Allegro crashes while placing jumper& J* b9 T, s9 ^+ l7 T% }; v
" e( s4 E/ ] T$ j& a1 Z
DATE: 10-7-2010 HOTFIX VERSION: 018
: g0 T0 b% n- K" y+ W- J% p" N===================================================================================================================================
7 s9 E( |- f. R% dCCRID PRODUCT PRODUCTLEVEL2 TITLE1 n* W2 x- m/ Q5 W
===================================================================================================================================' f, Q! Z% {; R2 Y* b
398114 ALLEGRO_EDITOR INTERACTIV Need to differentiate between tracks and shapes on an etch layer.: }/ D; B; |7 T/ v# U, |* ?$ F
530659 ALLEGRO_EDITOR UI_FORMS Allegro Place Manually and Update Symbols GUI missing checkboxes on Windows Vista: Z: a* v" t" C* B6 o
770576 ALLEGRO_EDITOR INTERACTIV Design Partition - Place replication not working correctly
4 T: O8 k8 O2 x# X777925 CAPTURE OTHER Capture crash immediately after invoking- J8 |& U8 T5 ^3 T% l3 z
807089 FLOORPLANNER INTERACTIV Logic > Net Logic hangs tool in Linux
$ _" p# q$ i: t4 p5 I/ W809118 CAPTURE NETLISTS ENH to compare two schematic Capture designs( [1 @2 }, V. f5 X Q
812046 CAPTURE NETLIST_ALLEGRO Design not getting netlisted in V16.3 due to illegal characters in pin nmaes
5 H3 E) S O$ e" _" I b, \2 r814607 SIP_LAYOUT IO_PLANNER update genfeed to add options to dumbp all chips files from design
) M7 _2 r5 V; ^# s7 ^1 X: J814750 ALLEGRO_EDITOR DRC_CONSTR BBvia and Microvia overlap DRC issue
]# L& d) f: C, y, E815621 SCM OTHER Enhance time shown in session log to support DST- D8 d! l; N o- \6 H
815681 CONCEPT_HDL CORE The TOC symbol shows multiple entries for the pages8 ~3 K# \/ i& t1 T
817380 ALLEGRO_EDITOR DRC_CONSTR Incorrect or bogus line to line DRC errors are appearing between the nets of a diffpair+ }4 T- y6 P$ f
817881 APD ETCH_BACK Create Etch Back Mask failed# t, j6 i, V v- `" R% F
820771 ALLEGRO_EDITOR PLOTTING axlLayerPrioritySet does not provide the same capability than the 15.7 Color Priority system1 h) Z2 t& \* U& s
820773 ALLEGRO_EDITOR INTERFACES Import 3rd Party Logic $SCHEDULE removes visible ratsnest from database when using T-Points
& o# G: s" @; u% `1 s! e' E820792 ALLEGRO_EDITOR INTERFACES Import $Schedule command is returning illegal loop error for pin-pair based rules
7 B1 E& S, T' ~5 n821133 ALLEGRO_EDITOR MANUFACT Output artwork for pad data that are suppressed unconnected pads with Gerber 6x00 format3 }7 b0 \/ t. H0 `; H7 D; ]
821504 MODEL_INTEGRIT TRANSLATION dmlcheck failed when .dml translated from .mod was opened by MI.0 B" P# M" M+ J S* V* L
821827 ALLEGRO_EDITOR EDIT_ETCH Allegro Crash on routing Diff Pairs7 J6 I9 ]+ [7 C, w! j9 b9 B
821836 CONSTRAINT_MGR OTHER Why the min/max propagation delay analysis is failing for one of the pin pair in this design!
$ |. e; [$ b) z2 p* b822090 CONCEPT_HDL CONSTRAINT_MGR Crashed the Constriant Manager and SigXplorer from DE HDL
( h) P% `5 R# z822744 CONSTRAINT_MGR DATABASE Xnet lost after DCF file imported into Constraint Manager* C, v* d6 X$ t% [) I3 ?, R P( U
822827 PSPICE SIMULATOR Simsrvr crash upon running simulation6 B1 g- e$ u7 Q* V1 P# u6 x
822844 ALLEGRO_EDITOR SCHEM_FTB Constraints are not updated in the brd file when working with Library defined diff pairs% S3 }0 u4 s O7 v. Z
822942 F2B DESIGNVARI Variant view does not show DNI on functions
6 o* ^ A+ n4 _ }$ f/ R& K823177 SCM BROWSER PPT_OPTIONSET_PATH defined using environment variable is not recognized by ASA. z# t7 I/ G \! a8 _$ j4 c4 y4 T
823200 ALLEGRO_EDITOR OTHER Import Logic hangs when dynamic phase control set
1 b/ s+ G- w( @+ E5 k823589 CONCEPT_HDL CORE The operation could not be performed because no object on the drawing was selected
u# ~7 x+ X& b* D, ~4 a8 L823821 ALLEGRO_EDITOR MANUFACT Allegro crash when trying to Gloss - [/ C& p1 ?1 o* s+ d6 ?+ G& {2 [1 {
823833 CONCEPT_HDL CORE show vectors command3 G8 a7 V! b3 x/ G" o& D0 h4 M) q
824902 ALLEGRO_EDITOR DATABASE Lose connectivity when copied via and cline structure
/ ~( E) u! b% E4 t825289 ALLEGRO_EDITOR DRC_CONSTR duplicated drc and waive drc
T# ?+ A# p: U* D6 O825969 CAPTURE SCHEMATIC_EDITOR Refdes are getting reset after doing a replace cache/update cache for a generated pat+ E( [- M2 k/ o0 T5 A
826068 ALLEGRO_EDITOR MANUFACT Adding Thieving on the negative plane layer doesn't show up- [5 b$ R8 m9 l
826266 ALLEGRO_EDITOR DRAFTING Datum Dimensioning Crashing Allegro in Linux
+ N$ Y+ E8 M0 w' J/ s |8 c; U827032 SIP_LAYOUT ASSY_RULE_CHECK SiP Layout crashes when running Assembly Rules checks' ^5 J/ X% s5 k+ k
827494 CAPTURE GEN_BOM Include file is overwritten for the STD Capture BOM if .txt file used as include file
- k$ u5 ?2 M* y827575 CONCEPT_HDL CONSTRAINT_MGR PINUSE- x. v/ t/ p; T% W* `
827708 APD 3D_VIEWER 3D viewer assign black color for all layer
& K8 N4 }( c2 {% U7 _) V828263 APD DXF_IF When the DXF out is executed, offset of the padstack is not correct.# k2 Y; b2 X3 o2 G- V0 `
828788 ALLEGRO_EDITOR DRC_CONSTR Soldermask Waived DRCs reappear in 16.3 i' y9 }" p) x, L
829046 APD MANUFACTURING create plating bar makes net name changed to dummy net& ?0 P1 _0 h; m6 j9 @' J
829331 SIP_LAYOUT PLATING_BAR Create Plating Bar is deleting existing fillets.
; w* L# H3 ?, l4 K. v$ D9 M$ h( a829336 APD OTHER Request the ability to merge two nets together into a new net./ v* r* i0 ~% r
$ {+ g5 L" Z% gDATE: 09-23-2010 HOTFIX VERSION: 017
3 O; r2 W% I/ H7 l' S" P, v+ I===================================================================================================================================
8 N/ V/ @1 Z8 A+ N! B, C7 TCCRID PRODUCT PRODUCTLEVEL2 TITLE6 l( W7 C) ?# Z1 e l$ B
===================================================================================================================================
" Z* H j( ?- i/ c6 s+ D. V676210 CAPTURE PRINT/PLOT/OUTPU Enhancement for correlate lower level pages with H blockes in PDF
" A) [9 `% \, w) K& l& C736942 ALLEGRO_EDITOR INTERACTIV Autosave is not working with every application mode.
, ~. z( f' g4 e8 d. i746256 CAPTURE ANNOTATE Intersheet refernces change their position in V16.3 even on unchecking ‘reset position’.7 R- c' b- }: W* `, G( V# O
785417 CONCEPT_HDL COPY_PROJECT copyprojectui crashes with a Windows runtime error
2 P; t6 f# O1 r3 x. y3 B; d( T" d791549 PSPICE PROBE PSpice cursor does not remember value outside zoom area
* l8 ]6 W! _; o, a0 R/ ]802639 F2B DESIGNSYNC BOMHDL crashes if colon is used as a sub design suffix separator
1 L3 c7 [% @- h804475 CONCEPT_HDL OTHER RMB+MMW doesn't zoom in/out anymore with ISR012" ^- H/ w: t5 s
807025 PSPICE PROBE Loading dat file slower in 16.3 as compared to 16.2
3 v' W3 i% J! W# |7 F- U808550 CONCEPT_HDL OTHER On Linux Import design does not obey umask or setgid settings8 g3 s; o; J4 i6 x
810568 ALLEGRO_EDITOR PADS_IN Can PowerPCB 9.2 - Basic file be converted to Allegro?) ?& }- u' Q& a1 H
812089 CONCEPT_HDL OTHER The colors on the Options form dont seem to match the colors displayed on the schematic canvas
( Z- U1 V+ b" r# t812475 ALLEGRO_EDITOR INTERACTIV Saving .mdd always results in working directory6 B1 L% x/ G; d9 I
812836 CONSTRAINT_MGR DATABASE CM Custom Fomula -Handling of Pin_Delay is inconsistent in Analyze- F: V/ w& V' M: H. A
812994 SPECCTRA ROUTE Max_total_vias constraint not working correctly when wiring option is set to "starburst".; A; T6 s9 z; D' j0 D+ L
816561 CONCEPT_HDL CONSTRAINT_MGR OLECS.exe Runtime Error occures when attempting to launch SigXP from a net in CM
6 E7 E6 b4 _# n6 S816879 SIG_INTEGRITY SIGNOISE Program has encountered a problem and must exit in 16.3 S014(v16-3-85AT).
5 I% x* F5 n8 R3 _6 _817006 SCM UI SCM copy signal changes existing signal names
# n' n- e, X/ d; R7 U" W817896 APD ETCH_BACK Etch back - improper use model. U- A/ P: p* w9 h" U* o; T
818242 ALLEGRO_EDITOR SHAPE Thermal relief connections not orthoganal and creating acute angles.! L# H' E |, h
818429 ALLEGRO_EDITOR PLOTTING Pins created from shapes do not plot solid.0 j u1 I1 ` B, V1 s) m( S! z
818513 F2B BOM Alphanumeric BOM not placing REF DES in proper order
. y% P# u/ U- b# H1 b: p" O5 F) m818818 ALLEGRO_EDITOR INTERACTIV Place replication does not recognize mixed case characters in file path
1 H# n2 ]6 o8 G n1 z0 l' l818910 CAPTURE FPGA NC simulation flow is not working with 16.3 release
+ _+ ^' k- r6 V819108 SIP_LAYOUT DATABASE Wirebond profile constraints lost after saving and re-open sip# \1 ]) U! A% t
819151 SIP_LAYOUT ASSY_RULE_CHECK ADRC is showing X-D DRC markers on good Soldermask Shapes when doing a min. shape check., D/ A" C2 b- f2 E* U+ o$ r
819183 ALLEGRO_EDITOR MANUFACT NC Drill file generated for Backdrill layers show wrong Quantity of the drills
* u5 F+ x8 Y3 c& L) ~% g$ W819269 SPIF OTHER File > Export > Router Crashes Allegro and dsn file creation stops
; Z# r) E8 Q7 j& U819463 ALLEGRO_EDITOR DATABASE VIA has illegal connections.
f& u0 o8 g- r: n4 _8 v4 h5 d819842 ALLEGRO_EDITOR INTERFACES File Import Logic fails on syntax check when following documentation for $schedule command
+ F3 b) n/ ]9 l- |8 k. t# A+ Q820177 CONSTRAINT_MGR CONCEPT_HDL Net_class objects that are changed in CM at Front End are missing after Import Logic
) l6 w5 q4 w) B' d2 Q5 t820231 ALLEGRO_EDITOR DRC_CONSTR Allegro hangs when multi thread DRC is performed after updating padstacks9 R) z2 k+ r1 x/ ^/ j
820373 SIP_LAYOUT OTHER Update symbol flags the "edited pins" error but still updates the symbol and then crashes.
) `7 @6 C* q2 F- t. o# N820381 SIP_LAYOUT WIREBOND When opening a new design, with a design already open, the tool will use the first designs profile settiings B( L' W0 n3 P+ j
820634 CONSTRAINT_MGR OTHER Netrev fails without any useful message when importing ECO netlist; h' M9 G! S! S
820665 ALLEGRO_EDITOR REFRESH Qvupdate is not working in 16.3- r/ f. Z7 Y3 s$ R2 |7 ^$ h
820849 ALLEGRO_EDITOR MANUFACT NC Drill has wrong quantity and also a drill is missing
$ Q# r. I: ~ ^6 c. Z821154 CONSTRAINT_MGR CONCEPT_HDL DE-HDL CM Import Analysis Results fails without any feedback5 e7 z6 E* Q% ~% C
821195 CAPTURE OTHER Updating Cache generates errors including CAP0027 on Capture DE CIS with ISR s0014 and onwards.8 h8 Z& Y0 y2 N2 ~
821856 APD MANUFACTURING Create Bond finger Solder Mask issue
! }% g L" m4 |8 {4 |9 p821936 SIP_LAYOUT COLOR Can not clear custom color of bondwire profiles) `: T* R. T* J/ w x
822841 ALLEGRO_EDITOR ARTWORK An issue about Gerber6X00$ V3 V n9 P9 C7 z9 E* B
822842 SIG_INTEGRITY OTHER CM and Show element report different lengths
/ M. p* N+ \3 Z' T- u& k$ Y823559 SIP_LAYOUT BGA_EDITOR When doing an Edit > BGA the tool will shift the BGA's position when at 90 or 270 rotation.
4 Q0 Q; N# o# x+ b2 S" ~823688 SCM SCHGEN Schgen changing the physicals bus name in the preserve mode for some of the bus# o' u2 i, [8 ]' ]# Y4 k
823792 CIS OTHER Capture CIS performance over WAN for bulk operations are slow3 ]5 t5 @2 e, M) `
$ h5 K! M4 s6 n" a3 ~" S# RDATE: 09-10-2010 HOTFIX VERSION: 016
5 e$ [9 ^- _: ]( i===================================================================================================================================
$ I, `9 u5 u! D* T9 s/ o6 mCCRID PRODUCT PRODUCTLEVEL2 TITLE
( @! ]. g5 [9 P2 J===================================================================================================================================
* u1 r3 p# s7 L4 J& G8 _604662 VLS-L VIA When changing Rows/Columns values in Edit Via Properties form, different value are assigned.- ^7 _4 Y/ @% B& E$ U* Q: T
747191 PSPICE AA_SENS Pspice crashes when starting Advance Analysis" k7 e1 j5 G, @/ }/ `5 i# k* s0 ~
756103 CONCEPT_HDL ARCHIVER Archiver does not include all the Parts when design blocks are copied from one location to another
4 @* a4 x; W9 P8 ~ v# L( `! v0 O; \758487 APD 3D_VIEWER package substrate (BGA) outline should be on a separate layer, not on bottom conductor layer.0 o( [& ?7 B9 @% L' i
764417 APD EDIT_ETCH Routing with Diagonal entry (45 degree) to Constraint Regions does not work9 P/ ]0 L" \: Y# n* r$ n
766409 PSPICE PROBE Copy to Clipboard changes the label text colors& B; H4 L8 V. A2 r
784577 CONCEPT_HDL COMP_BROWSER SingleclickAdd 'true' places does not pick the correct version
! o% W' ^ L( o+ A784814 SIP_LAYOUT ASSY_RULE_CHECK accuracy of acute angle DRC
* J% P6 }* C, ~1 I* w792039 CONSTRAINT_MGR OTHER Doing a File->Import->Worksheet Customization from Constraint Manager will change the working directory.
% v0 g$ W; j6 j. M796517 CONCEPT_HDL COMP_BROWSER Component Browser showing wrong symbol
6 L! \* f P! N- `! k+ L4 ^801944 SCM UI SCM dropping terminators and pull-ups when renaming signals (copy - paste special)" _' x8 E, |& a7 \4 I2 A
804627 PSPICE PROBE Printet text labels have wrong location
% \4 H1 @9 H8 Q5 L% D1 W# Q# ^7 A7 `810479 FSP DESIGN_SETTINGS Not able to connect some peripheral signals to FPGA manually- m8 j$ L4 r3 ]* p- l# l4 J' b
810814 CONSTRAINT_MGR OTHER T-point does not create when import DCF file.
1 p0 J v$ W% w. c, [# K4 J811032 ALLEGRO_EDITOR EDIT_ETCH Enable enhanced pad entry to support pads as shapes; P' _- l/ e' d7 Q6 o! M
812643 SIP_FLOW CONSTRAINT_MGR Physical Constraint values disappear after entering constraint mode9 [/ _( w* u% U6 X# P
812835 CONSTRAINT_MGR INTERACTIV CM Custom Fomula - "Analyze" on the header of Actual does not analyze pinpairs
8 Y! L G! {8 l0 P; H813435 SIP_LAYOUT DIE_ABSTRACT_IF Invalid parameter passed to ICP utility API6 u) `! G$ F& ~* _. V: H
814060 CONCEPT_HDL CORE Read only library becomes writeable when updated: L8 u. |9 ^( [+ |1 `$ x7 X
814347 ALLEGRO_EDITOR ARTWORK It seems like not work ”detailed text checking” on 16.3.2 f; W$ f7 N l4 I! x' i
814451 ALLEGRO_EDITOR DATABASE Allegro get crash when run dbdoctor+ Q) N9 i" ]( N+ a
814496 CAPTURE ANNOTATE Lower level part refdes resets to ?( Y/ C, q) B( j
815150 SIP_RF OTHER sip layout export chips output is not correct/ M7 E2 p5 b5 E$ F
816034 ALLEGRO_EDITOR MANUFACT Backdrill Passes not work from bottom- O! d: V2 ^# L Z+ {0 p
816065 APD DATABASE Export Libraries with no library dependencies selected creates package symbol without pins.2 F! c+ e. F+ O& W( S
816426 ALLEGRO_EDITOR SHAPE Dynamic shape not updated when component is unplaced
; X2 @9 u* m; ?" K+ B: A4 R$ D816616 SCM SYSTEM_OBJECT codesign incorrectly maps primary and secondary codesign object
+ f: @8 d8 F P& i" c816686 ALLEGRO_EDITOR TESTPREP Probe Spacing rounds off 3 place decimal to 2 places
" N: i: G% R# J816917 SIG_INTEGRITY LIBRARY Issue for loading interconn.iml( c4 X) n( ?# n- X- j- r* \+ P% Z
816986 ALLEGRO_EDITOR MANUFACT Mfg>NC>Backdrill analysis with passes set at Bottom layer is automatically switching to top, hence failing!
2 B' [) f. `) k% r/ u. s: b817473 CAPTURE NETLIST_ALLEGRO Backslash (\) is considered as illegal character for netname but it was allow in SPB 16.30.010
* h; q4 s) B& Y8 Z817606 SIP_LAYOUT WIREBOND When moving Bondfingers the Via's are sliding too when they should not.
1 a) S0 w3 m; b, E& E3 _/ O0 H( H" w3 _$ R4 ~+ _% R! r
DATE: 08-27-2010 HOTFIX VERSION: 0156 W8 g: a- ?; d2 v0 O5 m
===================================================================================================================================
2 x# \( J' d6 Y; X: c9 P1 f% h- vCCRID PRODUCT PRODUCTLEVEL2 TITLE
+ W% D1 y4 B; P$ ?===================================================================================================================================
+ V8 s9 {# k" H3 |! p7 _- k664821 CAPTURE NETLIST_ALLEGRO Improve error messages when netlister finds illegal characters in the pin names1 r+ k! P( A( a% d. R. H. x
753867 PCB_LIBRARIAN GRAPHICAL_EDITOR PDV crash when graphics from one symbol to another
6 \& d# z3 T9 o! z777559 CAPTURE OTHER Why the Reference designators get lost in project with external references.
) R/ ^' P6 j+ |+ V777657 CAPTURE PROJECT_MANAGER Archive Project causing Capture to crash# S% _7 a+ S$ b! J% ^5 N
785748 SIG_INTEGRITY OTHER 16.3 SI model library path directives behave inconsistently if the ~pcbenv/env file is present
) q" v) ~$ y' x* ?+ I789529 ALLEGRO_EDITOR EDIT_ETCH Neck Gap changed to Primary Gap when executing Delay Tune command.
$ h- ]' z% b* i* {/ |4 G791853 SIP_LAYOUT EDIT_ETCH via slide clips to 45 angles near BGA1 h! d! }& n4 s$ H8 j
796604 MODEL_INTEGRIT TRANSLATION ibis2signoise replace V_fixture_min with V_fixture_max based on the value.6 y7 p6 K0 k* p& }5 H& f- V* I0 L
797657 CONSTRAINT_MGR CONCEPT_HDL constraints from the brd file are not passed on to the schematic.' u* m& |% t- W3 Z# B+ q0 U& i
802760 ALLEGRO_EDITOR NC nc route not generating the circle correctly
% z! L1 L; f% h9 Z" N. ^) [803572 MODEL_INTEGRIT TRANSLATION quad2signoise fail if MODEL name include backquote." T9 z; d3 \' c- B4 Q3 s9 X
803869 SIG_EXPLORER OTHER Trace parameters form does not update with correct stackup data9 ~& H& R& z3 y( ]
804070 ALLEGRO_EDITOR SKILL The skill setting objects not match to all items in CM.
2 a( y, f, ~3 Z D: m/ B805641 ALLEGRO_EDITOR COLOR Clear all nets fails to remove the custom color on the Color Dialog form" N) ]# I' I0 N
806115 PSPICE MODELEDITOR Cannot generate a Capture symbol from Model Editor because no Capture license.% n( o; Z4 |" z. t% `4 a' S
806196 CONSTRAINT_MGR OTHER Netrev fails with warnings.1 N( e& g0 U* m4 W2 J% B) {5 _
806864 CONSTRAINT_MGR CONCEPT_HDL "Selected nets/xnets only" option in CM connected to DE-HDL
0 A( J8 V1 ]- [" x# O4 z807960 ALLEGRO_EDITOR COLOR Click OK to Color Dialog box and Shadow Mode ON/OFF setting will be lost.! y1 s* b7 _0 o0 E) }
808155 F2B DESIGNVARI Variant Editor variant.lst and BOMCompare not the showing the same data, h0 L1 Y- _& t( X3 z: C: Y
808392 SIG_INTEGRITY OTHER Cross section impedence not calculating for SPB 16.3 with single license for OrCAD PCB Editor
4 g; ]5 c1 l* y) b: T808978 CAPTURE STABILITY Unable to Place > OLE object > Visio drawing file. Capture crashes as well
; b' `" C. K! T7 J$ f$ E809163 SCM PACKAGER scm crashing when running export physical& T& b) f x, B& s1 v4 Y
809526 ALLEGRO_EDITOR DRC_CONSTR multi-thread DRC hangs when replacing padstacks# G: l/ Z0 H: |8 v
809587 PCB_LIBRARIAN GRAPHICAL_EDITOR PDV crashes during Text Cut/Paste operation in Symbol Editor
4 R: @: ?* x, o/ ~; `809636 ALLEGRO_EDITOR DRC_CONSTR drc update reports incorrect DRC count when run after deleting unused region in constraint manager.
9 d; {* }0 B2 T809847 PCB_LIBRARIAN CORE "Auto add SWAP_INFO to chips" problem
5 ]/ N9 e6 x# D0 o) t7 C8 M2 h6 k810024 ALLEGRO_EDITOR SKILL axlGRPDrwText does not work for left justification
" ^2 H# i2 H1 T/ A3 E3 U0 j: q810530 ALLEGRO_EDITOR EDIT_ETCH Sliding vias on differential pair is not selecting both nets5 d( a0 g) } q8 ~
810860 ALLEGRO_EDITOR DRC_CONSTR Improve Update DRC efficiency6 |1 K4 y8 U' r+ c4 U; o2 q
811506 CIS ICA Using Capture V16.3 ISR0013 “Save Schematic Part” option is missing in "New Database Part Wizard".
0 N' _' ~8 X7 N( t812259 ALLEGRO_EDITOR SCHEM_FTB scm crashing when running export physical- AGAIN
0 J- a: u+ O) I: |! i2 [812269 APD WIREBOND Wire diameter and wire profile automatically is changed when executing wirebond add command; u% H9 s6 m, c) P
812597 PSPICE SIMULATOR Pspice crash.
. J) I6 Y7 Y7 j N/ i1 F/ c! x812655 SIP_LAYOUT IMPORT_DATA Importing Stream data multiple times into a .dra will have inconsistent results, each import is different.
" _( `9 r, j7 {/ p# X/ }. D C; @- u; h813253 ALLEGRO_EDITOR DRAFTING Datum Dimensioning Crashing Allegro
9 S; z) g0 U: R3 B# z) G813265 APD WIREBOND Wire Bond Report fails with wires present that were added with the "Add/Edit Non standard" option.
& m, j5 J0 P0 g
8 h9 i% `- j8 z' }2 ?DATE: 08-13-2010 HOTFIX VERSION: 014* a! O" d! V( N
===================================================================================================================================
7 b' y/ A ]# @5 ?7 M' BCCRID PRODUCT PRODUCTLEVEL2 TITLE- q. s5 V! e1 S: Z8 H3 v. B
===================================================================================================================================/ Z, S7 X" h( B7 q
792354 CONCEPT_HDL CONSTRAINT_MGR Viewing a second net in SigXP from Design Entry HDL constraint manager generates an error; A' G# L1 q3 C1 a; z
800336 GRE CORE GRE's Plan Spatial crashes Allegro.; \/ Z& p1 Q- n9 G, {& \) i
801116 SIP_LAYOUT WIREBOND Wirebond -> change characteristics with only wires selected should not modify connected fingers' placement at all.4 h( p& u2 D5 K5 f+ w
801463 ALLEGRO_EDITOR EDIT_ETCH The Allegro axlShoveItems SKILL function behaves differently in 16.3 than it does in 16.2.
: D& W. \3 Y& b! S% ?, v$ K803049 MODEL_INTEGRIT TRANSLATION quad2signoise cannot translate OpenDrain Model correctly.+ u" E' m2 U7 N2 x: O
803878 ALLEGRO_EDITOR DRC_CONSTR 'Via_At_Smd_Fit' not working correctly when the via fully covers the pin.
, [* B% d' K& W+ J804273 ALLEGRO_EDITOR DATABASE Running update DRC gives different number of DRC.4 f7 f7 z, M5 S# ?9 ]
804330 F2B PACKAGERXL Packager is changing the refdes in preserve mode for components in hierarchical block9 l* ]( c+ b7 Y1 S# R0 B# Q. R
805335 F2B PACKAGERXL Packager fails reporting empty location values when the location values do exist) T4 F, C* w F& E6 G6 V$ C& l V5 c
805676 ALLEGRO_EDITOR DRC_CONSTR Update DRC hangs while updating differential pair checks with dynamic
+ ?" u `7 d: y4 n, ]: N# Q! W805747 SIP_LAYOUT EXTRACT Extracta crashes with this testcase and command file.! |: m: h! f8 x
806028 ALLEGRO_EDITOR TESTPREP Allegro testprep parameters causes crash
% I7 m; s+ s: @$ g806120 PSPICE NETLISTER “Enable PSpice AA Support for legacy" option results to undefined errors' D, e4 k( m* f8 S: p- C
806182 ALLEGRO_EDITOR SKILL axlPolyFromDB will crash if object is a pin on an unplaced component
- r" ]/ \ @1 J5 h4 E807543 ALLEGRO_EDITOR DRC_CONSTR Via at SMD Thru DRC not working correctly in Solaris9 o6 v- I% c0 r* V' H4 X5 H
808047 SCM SETUP scm not loading all parts from pcb after running brd2asa
2 B5 O) M) u, s& J$ o! |808831 ALLEGRO_EDITOR DRAFTING "Oops" command(in dimension angular command) crashes Allegro.- K: A: q+ t; X- G. s* z% v6 d
* n8 ~. j( W. ?' L
DATE: 07-31-2010 HOTFIX VERSION: 013. ~% L3 `$ l+ G# G( D
===================================================================================================================================
4 q/ M" E7 G7 d, i0 x# X" Q1 hCCRID PRODUCT PRODUCTLEVEL2 TITLE
. P4 t- ^0 q$ G/ Q7 @===================================================================================================================================& G2 t: ~! ]: ] Y" A6 i4 m. T
576133 CAPTURE ANNOTATE Annotations in the design getting reset to ?& H8 B9 v* q7 c
688692 CONCEPT_HDL GLOBALCHANGE Global Change does not respond to RMB> Done
% L! [4 T' U' g' j4 E731045 CIS EXPLORER Double click in CIS explorer places two components
' s: y7 g% A/ D. s/ O763550 CONCEPT_HDL SKILL nconcepthdl in 16.3 no longer recognizes skill functions that worked in 16.2
) X, R! b# u; N4 m5 G# g764130 CONSTRAINT_MGR OTHER Export Excel from CM hangs/crashes Allegro on attached design
# s# D! `- C+ w4 ?* N% J+ w766750 ALLEGRO_EDITOR INTERACTIV Request to enable datatips when constraint manager is open and a command is active
9 o7 d& x% z/ b: o% `! ~# I774466 CAPTURE CORRUPT_DESIGN DSM0008 - Unable to open design in 16.3
: H$ N- {8 q6 U* b1 e1 q777862 CIS PLACE_DATABASE_P Absolute path in field Schematic_Path causing incorrect display property
5 r* W, {+ j- o1 v7 J5 z" F2 V782370 CONCEPT_HDL OTHER CreferHDL $XR hyperlinks do not work in PDF Publisher - they did in SPB16.21 Y( ^+ D5 m1 v3 i) L
783036 SIG_INTEGRITY SIGNOISE Problem for Waveform saving with -w option in signoise command.
8 `9 i3 G+ v; Y$ w+ \* D784205 CONCEPT_HDL CORE Schematic block generated from SCM needs to have DIFFERENTIAL_PAIR property on the ports
0 {" V5 `1 ^% L( J& P% U# z786387 CAPTURE OTHER Update cache does not update the parts on schematic) s- m) R; @/ U% a* q
786560 CAPTURE NETLISTS Sqare bracket [] is not allowed in PADS netlist.$ p5 x( R" h d u! H P$ y# P* |
786808 SIG_EXPLORER OTHER RMB > Via_Model_Name doesn't display the generation param of the via.
; e6 ?& ~+ ]! U+ q787414 CAPTURE PROPERTY_EDITOR Part value can’t be moved on schematic if a part has been copied to a new design and not saved yet.
" N6 ?" m% B m/ t. R) R: h791965 CONCEPT_HDL CORE group move should not snap to center of group
1 O9 s) z# E! a; N7 R792126 CAPTURE PROPERTY_EDITOR Attempt to change display for occ prop resets
% I% ?( t" V8 o794900 CAPTURE NETLISTS Attached design is not getting netlisted in V16.3. It works fine in V16.2# p# O' L) \/ P; W: W
795914 PSPICE SIMULATOR Getting RPC Server Unavailable Error
" \9 i) `2 N/ v9 @3 z795997 ALLEGRO_EDITOR TECHFILE crash when importing dcf file4 p: ^5 p- V2 u- ?' z9 [0 l. Y4 A
796124 CONCEPT_HDL CORE Messages overflow console
& N- C, _/ B0 I ]4 y( l796168 CONSTRAINT_MGR CONCEPT_HDL Create ECSet in DEHDL CM moves focus to DEHDL: k- f& V- c7 A+ n1 m% E/ d
796378 ALLEGRO_EDITOR PADS_IN Pads_in has error while translating PADS 2007 asc file
$ D! F: A5 g# ?5 P) ~5 P796658 APD OTHER Allegro can not import the property section of 3rd party netlist correctly.
* H. j" Y+ A! w8 g- p9 p4 v% v- g796926 CONSTRAINT_MGR OTHER Importing Custom Worksheet file does not overwrite the Description field.' d' s U3 s& h* H3 |! s# E
797387 SCM SCHGEN Increasing the grid units from 25 to 100 breaks the bus into bits on the generated schematic.- ?) l% a7 k3 k4 @2 U! `7 V
797529 SIP_LAYOUT IMPORT_DATA import BRD to SIP fails if database has partitions. even if only silkscreen and documentation exist: m J$ c% @8 [9 n4 x
797634 SIP_LAYOUT DIE_EDITOR rat control buttons in edit die mode are invisible until user selects an action5 E; a1 j$ f0 P7 y( B
797663 SIG_EXPLORER OTHER Current probe could not get from sigxp left symbol panel.
2 ]# D5 d, s3 ~6 b4 z# L798118 SCM REPORTS SCM report not resolved with CCR 697709' K$ j5 y8 |% x( Q! _+ P+ w, D
798464 ALLEGRO_EDITOR SKILL axlDetailLoad not filling shapes in 16.3 s10
! ~2 C) B% O, B: i9 v798980 ALLEGRO_EDITOR DATABASE Unable to open board file as it fails with a error message Found bad data pointer, run dbdoctor.+ k3 M7 n" D' x- V
799445 PSPICE MAG_DESIGNER Magnetic Parts Editor crashes while saving newly created Magnetic component
1 @' b# m4 O# V$ Q799539 CONCEPT_HDL COMP_BROWSER PPT Options settings lost when cancel done in PPT Options form
4 L e( W9 l2 F- J799957 CAPTURE CORRUPT_DESIGN Capture crashes while doing save as in 16.3
( @5 l N. A" ?" Q0 W7 u' d800280 SIP_LAYOUT WIREBOND Swappoing Dies in the die Stack will cause the bondfingers to move and create DRCs
( V: w# V& O- @0 h6 j800542 POWER_INTEGRIT SIMULATION Multi Node Simulation does show actuall waveform+ F# {! g+ ~5 s# E! u0 M
800695 CONCEPT_HDL CORE Genview changed behavior in 16.3 HF 11 breaking the design hierarchy
$ J1 n6 ?% K1 X, q800751 ALLEGRO_EDITOR DFA DFA placement does not understand package keepout3 \) u: e! W) W) l9 q8 y; d- y, p
801017 ALLEGRO_EDITOR REPORTS APD Crash when creating Unused BB Via Report8 ?% ^9 l6 t) t0 b3 H8 Y
801043 SIG_INTEGRITY OTHER SigNoise Case Update seems to check ActiveDesignLink value incorrectly.7 }' b5 E: P3 z) w; ~" a
801433 ALLEGRO_EDITOR MODULES selected figures do not end up in the module6 H+ l1 s( B2 X w, I) S* B
801705 ALLEGRO_EDITOR SYMBOL Shape symbol was specified with RegularPAD of the PAD stack become "Null".
( z- a" o5 k; l' @; ]802319 ALLEGRO_EDITOR SHAPE Shape status cannot be changed to smooth using suppress pads.& Y) Y) _* t, k+ D9 ~/ ~' h
802474 CONCEPT_HDL LWB-HDL Testbench generator not working in Linux2 r v1 ], I0 }, s
802887 ALLEGRO_EDITOR OTHER Adding the No_Shape_Connect property to via causes the application to crash.. z2 H5 Q6 P n) e/ S, }# c5 g
803393 SIP_LAYOUT DXF_IF Cannot generate a dxf file* z8 G/ l, d3 T
2 M9 U3 q( v. Q _9 [& z0 hDATE: 07-16-2010 HOTFIX VERSION: 012
* A* E5 W' n6 Y- _4 \3 @===================================================================================================================================9 ^$ P0 d5 l' J
CCRID PRODUCT PRODUCTLEVEL2 TITLE2 y' n9 i( X% }' t a# g2 D; o
===================================================================================================================================
: E4 n4 G9 a% s5 ?5 ~. `" s757157 CONCEPT_HDL CORE Zoom (using SHIFT + mouse wheel) to work such that the tool zooms based on cursor location
; u+ b, {" q: ]3 Y5 _' Y9 y766639 ALLEGRO_EDITOR EDIT_ETCH via structure disappearing after selecting place manual hide icon.; o; N) Y0 I* ^9 L4 C9 T
770910 PSPICE PROBE Printing from probe yields text label with too small size
$ S4 N9 K, A8 T1 r773603 SIG_INTEGRITY SIMULATION The characteristic of S-parameter model is different.8 [+ {1 f: Y1 N7 d+ X1 D' I
774363 CONCEPT_HDL CORE hier_write didn't report error.
' s2 `3 J) E2 v, i) m" f776991 CONCEPT_HDL CORE The Wire> Bus Name command does not use the Net Name font setting9 Z# e% R. Q' @/ [
781965 PSPICE PROBE Unable to add trace expression with small letters
, t% |/ R0 z9 z) E0 n/ z782847 SCM PACKAGER PKG-10002 - Cannot associate a logical part from chips.prt/ c; L6 \% }$ ^+ H( x5 O8 k$ t
783245 SIG_EXPLORER EXTRACTTOP extracting net with trace on plane layer giving unconnected topology
. l7 T8 H( m6 r785320 LAYOUT TRANSLATORS L2A translation fails with error "output directory is not writable".
( j( u; C# s6 c/ C4 [+ U785401 SIG_INTEGRITY OTHER The "View Geometry" or sigxsect command is not working in SQ 16.22 i9 m* k% u2 b7 N! Y2 @
785715 ALLEGRO_EDITOR PADS_IN PADS_IN fails to convert some components on Bottom Layer and adds two components at same location) r* Q. j+ R+ R2 z% w, D
785868 SIG_INTEGRITY OTHER Unable to generate Parallelism report as the report seems to have hung the SQ Session.
5 ?4 f' l( a6 L' ~" i+ J/ ^, x/ T9 v788523 CONCEPT_HDL CORE selecting QuickPick toolbar button should not reset canvas zoom
% _! P+ z) V) O8 h) L2 Q' ^789333 CONCEPT_HDL CORE Font colors not being used as set in the SITE .cpm file
1 p1 `$ C! b3 {5 g. i% c, h789348 ALLEGRO_EDITOR EDIT_ETCH Via Structures removed from database when switching to any App mode from Placement App mode
- {1 Z& Q. e$ t* ~1 b; a4 V789473 SIG_INTEGRITY OTHER Via delay is not included when t-point is at the via9 c. E: k* T# @6 @8 `
789744 ALLEGRO_EDITOR SHAPE Update Symbol with cline at symbol level do not connect clines properly' l/ n2 H) _1 M/ \) p+ A2 \
790170 F2B DESIGNVARI Function of Variant Editor and Annotate schematics
/ `! Q: @6 O* I790811 APD ARTWORK Some Void shifts by the artwork output.
4 Z: M! g5 k5 H, u/ G+ }* F+ N791371 ALLEGRO_EDITOR REPORTS Dangling line with cpoint not reported in the dangling lines report.
: o. ~8 n! t3 {1 J3 j: q* s791486 CAPTURE PLUGIN_INTFACE Unable to open a PSpice Project by double clicking the .opj file, if Capture is already open
. @( y, r2 Q4 V4 o791663 CIS RELATIONAL_DB Relational view doesn't appear when capture opens second time' L: I0 Q4 R" ~
791690 ALLEGRO_EDITOR EDIT_ETCH etch editing/routing in placement mode, allegro looks for all libraries adding delay in routing.% g+ W# V3 Q& @( u5 ^/ T1 C
791720 ALLEGRO_EDITOR DATABASE Color Net param file does not have some nets with special characters in the Net name." ]8 n- U0 ]5 Y+ E: j# u& V v% t$ f$ Q
791987 ALLEGRO_EDITOR PADS_IN PADS Translation fails with no error message" V- O. z6 H! {* w* g
792232 ALLEGRO_VIEWER OTHER Import parameters not bringing in plane colors in allegro viewer
6 ?, @! s$ a( ]" i# w# W0 N792559 ALLEGRO_EDITOR DATABASE Error when executing refresh symbol command' r0 V. s( ^' O q8 X
792923 ALLEGRO_EDITOR OTHER sted fails Can't open STED stroke file ~pcbenv/allegro.strokes
. X& `0 ]/ F) r793358 SPECCTRA PARSER When I try to invoke Allegro PCB Router it fails to invoke with errors.5 [9 h6 [+ T$ G
793605 CONSTRAINT_MGR OTHER Importing custom consmgr.wcf file crashes Allegro.0 b7 ]5 s; d3 V9 V
793955 ALLEGRO_EDITOR DRC_CONSTR add connect launch signoise even so electrical drc are all at off
( n, q* O5 a. w( H* }9 M6 t) D794748 LAYOUT TRANSLATORS import fails with message not valid Allegro subcls
7 z2 n! j4 V# T; B/ N5 [! g794775 ALLEGRO_EDITOR SCHEM_FTB Import logic runs forever or get a netrev error without any explanation
$ N" y: k0 H6 ]' Q7 @795261 CAPTURE NETLISTS Create netlist hangs in SPB16.3
' p' J8 h! }* A/ C795364 CONSTRAINT_MGR OTHER bookmarks are not getting saved in CM
" ~" s% j* r! u z0 _% ^" E- c795410 APD BGA_EDITOR Using the Edit > BGA tool I cannot get it to modify the pin numbering of a BGA9 A6 y! h% k/ y/ b
795501 PSPICE PROBE Unable to see the Multiple Mark-Labels in Probe
( Y8 R8 o6 w- W9 j8 A( R795761 ALLEGRO_EDITOR DRC_CONSTR Design is crashing while executing Tools > Update DRC; q% [5 {6 ?: M
795770 ALLEGRO_EDITOR DATABASE void moves when upreving from 15.7 to 16.3; A1 A5 a [: ]3 \" r
796026 CONCEPT_HDL CHECKPLUS CheckPlus reports text overlaps inccorectly on Linux
* m5 i" s+ o6 S. W; k, f; s796092 MODEL_INTEGRIT TRANSLATION ibis2signoise crash if Submodel section exist next to Component section.
$ T, Q9 O b# |6 }) ^796361 SIG_EXPLORER OTHER When dml file is loaded "Illegal format in device file" is outputted.0 V2 c# Q& \# o
796366 CONCEPT_HDL CORE UI windows in DEHDL are scattered8 ?1 z! g* L* n
796590 APD DRC_CONSTRAINTS CM Hole Spacing rule always set to 1905 in a new design.
# S9 R( t7 z. D& Q0 C796858 ALLEGRO_EDITOR DATABASE Deleting layers that has only vias moves etch from other layer on it and prevents the layer from being deleted.
6 W* v/ _# S; D% K" Q3 I6 @; B( h. b: z+ I# p6 G
DATE: 06-25-2010 HOTFIX VERSION: 011
( j5 E7 W) m3 X' S1 ?. i===================================================================================================================================
1 b2 W% q+ z2 `4 t$ UCCRID PRODUCT PRODUCTLEVEL2 TITLE
3 w0 n. q7 \' y0 Y' P===================================================================================================================================
2 G: F) Z" _! M$ x2 M644128 ALLEGRO_EDITOR MANUFACT Enhance Backdrill for HDI Buried Vias0 Q5 M3 _3 P* \$ V
743746 ALLEGRO_EDITOR MANUFACT Sub-laminate back drilling -Arbitrary from-to layer drill capability needed
4 }- Q- X, K+ t8 z773066 CAPTURE EDIF PinSwap information written in EDIF does not back to Capture schematic o" H g8 ]5 N9 G
775690 CAPTURE STABILITY Design is not properly translated in 16.3
8 t7 p Q& {/ Y d2 U* ]. K2 U782854 ALLEGRO_EDITOR COLOR Component Keep Out for the Top & Bottom layers not showin in the Color Dialog box, only ALL shows.
7 d9 O2 F# y$ Q$ k, x784439 SIG_INTEGRITY OTHER CM of 16.2 recognizes the differential pair nets as Xnet.# @) c( \2 B/ ^
785135 CONCEPT_HDL CONSTRAINT_MGR Applying an ECSet to a diff pair crashes Constraint Manager
. L) n- @- |% @5 b* s* c785179 SCM OTHER Changing a differential interface signal to local corrupts the con file and ASA is not able to load% ~; Y/ D5 E6 Y, G0 z, s" R
785332 SIP_LAYOUT LEFDEF_IF unable to def in to sip layout
1 b: s% I8 X$ Y785423 SCM SCHGEN Schematic having incorrect connectivity
8 u$ L ~3 [( _( ?" v1 r, |; T786858 SIG_INTEGRITY SIGWAVE want to select license at launching sigwave
$ d3 l% S/ s/ i" I4 X+ I" U3 n786871 ALLEGRO_EDITOR SHAPE Allegro dynamic shape not updating) a6 U3 |5 \9 S
786957 CAPTURE MACRO If an off page connector is renamed using macro the net name attached to it is not getting changed
) i% X0 Q" {6 i( L787003 CONCEPT_HDL CONSTRAINT_MGR olecs crash in CM when rename librray defined diffpairs on this design.+ a0 I; ?% p" Y3 e$ e7 Y) R
787087 ALLEGRO_EDITOR DRC_CONSTR Diff pair Static Phase tolerance Error
3 _0 K# i$ p( C& I2 ]: g787174 ALLEGRO_EDITOR MANUFACT Reading filmsetup.txt file crashes Allegro
* N/ |. e# R, e/ e788521 ALLEGRO_EDITOR DRC_CONSTR There is a difference of DRC between SPB16.2 and SPB16.3.
" ?2 J) m) z6 |2 E5 p+ q788652 F2B DESIGNVARI Variant Editor cross highlights incorrectly to Concept) L1 G1 s- F1 O+ i8 x9 B/ @4 c
788658 CAPTURE NETLIST_OTHER OrIntegra.dll netlist has inconsistent behavior7 V# n( k" K' S1 ^, k) n) i
788718 ALLEGRO_EDITOR DATABASE Board crashes upon deleting Cline segments within BGA using Allegro PCB Design XL License.
, f3 C& s5 U4 e789206 ALLEGRO_EDITOR SYMBOL Merge shape option causes attached *.dra file to crash
, q" e& z( P. N789324 CONCEPT_HDL CHECKPLUS CheckPlus output producing wrong values9 q5 H$ c) X, E8 v
790049 SIP_LAYOUT EXPORT_DATA Offset wire tack points disables wire in AIF Output# g' e& G: U9 G
790503 ALLEGRO_EDITOR SHAPE Shape Void not correct
3 I/ R+ P8 L; M& ?$ F$ u3 {) i790567 SIP_LAYOUT TILING unable to run the ndw tile die generator2 L% p/ R- ^& D, Y2 r" r
790622 ALLEGRO_EDITOR SKILL line width of internal segments within hatched shapes not correct when created using SKILL
7 C7 b6 r4 a2 A; o791075 SIP_LAYOUT EXPORT_DATA The shape that connects Merged Bond Fingers is missing in the DXF output.: c5 C1 L" I$ C! M5 w4 N- u
3 _% U% {4 _3 I2 YDATE: 06-11-2010 HOTFIX VERSION: 010 ]6 B, ~0 ?6 V) O8 l: W
===================================================================================================================================. g8 j( u% C0 b3 Z- V
CCRID PRODUCT PRODUCTLEVEL2 TITLE
7 O& t, O0 q' t: b. h===================================================================================================================================
, Z8 n2 ?9 T. W! z, B3 W0 O701724 CONCEPT_HDL CORE Page Down (PgDn key) Key is unresponsive- p% ~! J9 \6 _ ^0 X0 P/ g
722773 ALLEGRO_EDITOR DATABASE How can i add DUMMY NETS to a Net Class ?* R0 e' Q* D1 w! @! r! k1 M
767874 ALLEGRO_EDITOR OTHER Component Geometry/Pin number not imported.. R. A, E1 P0 b, B
769644 ALLEGRO_EDITOR SCRIPTS Why Command line script in non graphical mode prints everything to the screen when working with Windows?. H2 ^3 n9 T5 [2 O
778086 SIG_INTEGRITY SIMULATION extracted net yields unrealistic resuts +/- 100v swings* ~! E% @" B9 c( a2 N% V
778915 ALLEGRO_EDITOR OTHER Export library dumps symbols with mechanical pins instead of connect pins N7 P$ J- {" y
779119 PSPICE ENVIRONMENT MC Analysis does not seem to honor Custom Distribution( S( |: G* z; @7 _
779161 ALLEGRO_EDITOR OTHER Getting error-"illegal arguments passed to a dba routine" when connecting CLine to via
3 t$ W& n$ x- V" Q; L/ Z+ E779335 SIG_INTEGRITY SIMULATION HSPICE sim from PCB SI caused netlist error.* K6 C/ U2 C1 r9 t; P1 \
780314 SCM UI ASA crashes on paste special.
8 ^0 Y9 l; t, G9 g$ ?2 {) m780345 CONCEPT_HDL CORE Pins look garbled when part is vertically mirrored
. n% d$ Z% ]- N8 D780811 ALLEGRO_EDITOR SKILL Request 1k limit of SKILL API be removed.
5 S8 b" s5 s8 d& S" {- y9 _# |781111 SIP_LAYOUT IMPORT_DATA Import Brd to SiP failed
! U$ R4 @% x3 v [7 H781259 CONSTRAINT_MGR TECHFILE Import tech file crashes Allegro, ^2 I8 z. U$ Q! O. b5 \' h8 w9 N
781287 ALLEGRO_EDITOR DATABASE dbdoctor removes tespoints from odd angle clines leaving V/L drc% o9 _" A8 V0 m9 }+ _
781331 ALLEGRO_EDITOR SCRIPTS Script executed by command redirection operators is giving different o/p for v16.01 and 16.3
- E3 c' P! w* _& r7 ]2 t; q781647 ALLEGRO_EDITOR MENTOR mbs2brd is defining extra additional testpoint that is not present in Mentor database: z5 U6 k) s) w/ F* L
781650 ALLEGRO_EDITOR DRC_CONSTR Update DRC hangs while updating differential pair checks with dynamic phase tolerance added from the logic import! d# z; [& H( s* p
781665 PSPICE DEHDL_NETLISTER Error simulating delay component
3 F/ u* V' j8 W! M9 P3 c( a781688 CONSTRAINT_MGR ANALYSIS Application hangs on Solaris when executing DRC update
( Z2 r0 b/ B7 s3 p. q781799 ALLEGRO_EDITOR OTHER Unexpected results when exporting and importing text parameters& P1 C" s/ ?8 u/ z) P
781922 ALLEGRO_EDITOR SHAPE Pin doesn't connect as a thermal.
, N9 |4 U( D. J2 @. `: P; y1 q5 A782124 CAPTURE PLUGIN_INTFACE Bias point display not getting updated for projects on network
2 t( [9 q# b, M+ b R7 x782415 SPIF OTHER File > Export > Router takes 5 hours to create a .dsn in windows....1.25 hours in Linux.
8 U( y( l: y! I! x8 K6 n9 T782566 ALLEGRO_EDITOR PLOTTING It seems like not work PLOT parameter "Auto Center" on tight paper size.
6 q' n$ B! g( X d782628 SCM NETLISTER Connection change not updated in the Verilog Netlist
1 {" U+ F6 s# U; _ c( U. f783059 ALLEGRO_EDITOR DRAFTING Create Detail with "filled pads disabled" doesn't work with irregular shape pad.: I- x, F3 c$ E9 Y1 s2 {
783142 SIP_LAYOUT IMPORT_DATA import bga text in on connector crashing sip layout
2 O# H: ]; o' f0 v" ~4 r783222 FLOWS PROJMGR Edit Physical and Spacing constraints. X2 j" n4 b" W8 Z1 ^4 C3 Z
783241 ALLEGRO_EDITOR PAD_EDITOR Pad Designer hangs when attempting to save to file.
1 u3 t# y: c, P783283 SCM IMPORTS scm crashing with import physical) l: o& ?% x9 s# R
783301 SIP_LAYOUT WIREBOND All Bondfingers not sliding along path.
5 G% |; [7 q1 S( p/ |5 c# J* x& l783496 ALLEGRO_EDITOR MODULES Problem of module placement.
; N, h3 M! o5 R# F+ E3 N4 H783813 SIP_LAYOUT BGA_GENERATOR Request to add new JEDEC BGA sizes to the BGA wizards standard JEDEC pulldown menu.% z2 ]1 t$ S, g; B8 W
784441 APD OTHER Users cannot delete layer even everything was deleted
2 ` g) a8 r B) b! B& C( T784639 ALLEGRO_EDITOR DATABASE both dbdoctor and allegro are crashing while opening this database
/ U& l& f2 G3 ~5 O/ X785100 CONCEPT_HDL CREFER Cross Referencer must not call Unix command on Windows platform" k/ y( i2 L; R
785385 ALLEGRO_EDITOR MANUFACT Allegro Crashes when using Datum Dim with Shapes.
9 a9 D/ o6 Y5 f( S2 h
3 q/ Q: R: M1 J1 \* v2 M3 g6 P' W$ ?DATE: 05-28-2010 HOTFIX VERSION: 009
6 c2 v, C8 _/ B===================================================================================================================================4 b# A8 ~" w' X4 l- k* e" s2 x, E. U
CCRID PRODUCT PRODUCTLEVEL2 TITLE
/ d3 C* I! E! j3 P4 i" K& [2 L2 D===================================================================================================================================
4 c# q! B+ r. P# `2 N758913 APD OTHER uncheck default check buttons through options/preferences+ ^3 F; A- M8 { F+ I2 ~/ r
763566 PCB_LIBRARIAN PTF_EDITOR The ptf command in batch mode always returns "abort"1 e5 E/ W3 w1 c
763662 ALLEGRO_EDITOR INTERACTIV Place replicate update creates numerous DRC on win platform
$ o p; v- u7 l' |- R6 u771088 CONCEPT_HDL COMP_BROWSER QuickPick adds incorrect property value when ppt optionset file is used! S. m+ F: |+ c# Y x3 K2 j3 g
772285 MODEL_INTEGRIT GUI Model contains recursive calls fater port rename reorder funtion is performed on it.
: U8 a0 @3 F v W774070 ALLEGRO_EDITOR DRC_CONSTR Allegro crash when sliding connections.+ i( S' P8 ^5 ?2 i
774880 ALLEGRO_EDITOR INTERACTIV Place replicate stops with No available buffer identifiers.* E' v- E. H- H* `* `
775443 APD EDIT_ETCH The routing of DIff Pairs when transitioning from a region needs to be smoother.
3 F1 | n5 M. m0 K776022 ALLEGRO_EDITOR INTERACTIV Allegro crashes when we use Ctrl+Click in Etch Edit mode for selecting a Cline Segment in Allegro PCB Design L
8 U0 G; w# Q6 v776151 ALLEGRO_EDITOR REPORTS Shape report incorrectly lists thermal connections for SMD,Via and Through all as Through.6 n9 N. e8 M ?; N q
776190 ALLEGRO_EDITOR INTERACTIV place replicate crash; select polygon zoom points" p6 D, g% J: E& J: ~
776284 PSPICE STABILITY 16.3 design crash while simulating the design" w* |$ g3 @7 ]& J* L
777556 SPECCTRA CHECK interlayer clearance output drc even so layers are separated by a power layer
9 N- b+ j' r6 E. E7 g& r3 ~777689 ALLEGRO_EDITOR SHAPE Shape do not void if Curved Fillets are used
, A- `- ^# M1 S4 V# S9 a2 w777698 CIS RELATIONAL_DB CIS 16.3 ISR s007 - Relational feature doesn't work2 \5 d8 |4 I: @) L& G. s
778042 CAPTURE PRINT/PLOT/OUTPU Some text are not searchable in Capture generated pdf
0 Y: M7 \) ~3 q8 O1 j778350 ALLEGRO_EDITOR SHAPE Multiple Drill on pad gets round void instead of rectangular
/ {; U9 h1 f: \/ C+ ?! v+ p778356 ALLEGRO_EDITOR SKILL Duplicate Vias with axlDBCreateModuleDef
# P+ E7 @( C9 v1 m4 I778782 ALLEGRO_EDITOR OTHER Display-measure and axlAirGap incorrectly report no air gap for multiple drill pin
B' l4 b0 h9 y B; A# L779146 ALLEGRO_EDITOR OTHER Moving component crashes Allegro0 ]% d+ ~% ^+ U' T" |8 l+ ?& w
780213 ALLEGRO_EDITOR DATABASE Design saved in GXL when opened in XL gives misleading message.
' R) z( t5 a1 g! Z: {+ R& L780773 ALLEGRO_EDITOR SHAPE No DRC displayed when Place Bounds are edge to edge
' H# ~5 K- s; f6 k
* H7 H! V4 h i% A' K- X; G4 u( s6 ~ HDATE: 05-14-2010 HOTFIX VERSION: 008( p! ] b: {, Q3 {
===================================================================================================================================
L( g4 \, {% H! GCCRID PRODUCT PRODUCTLEVEL2 TITLE
R% D+ p% N& K5 j3 n0 U. v/ y===================================================================================================================================
- W; w" K ~% ?; {4 z9 j z697699 CONCEPT_HDL HDLDIRECT SCM Verilog output contains the line “defparam <instance number>.SIZE
1 G3 E) I: d3 `0 V! x734169 ALLEGRO_EDITOR PLACEMENT Wildcard asterisk character giving "illegal char(s) in refdes entry." error in quickplace.
' R( v6 o. B! X9 K7 p738970 SIG_INTEGRITY GEOMETRY_EXTRACT power bus issue with SSN simulation when device is on bottom
9 Y3 J# R9 `5 h5 K9 q9 y5 _3 u6 l+ d744762 CONCEPT_HDL OTHER Connection dot sizes do not match on printout vs. screen
: S# T3 M; g9 H- }! M- s/ }750371 MODEL_INTEGRIT GUI Model name in physical view cann't match the model in right workspace
! |3 B1 N! V0 A$ r. W% q8 y5 p757024 CAPTURE STABILITY Capture crashes while exporting to EDIF0 u& S% m! A/ s& m1 I, D M
759094 CONSTRAINT_MGR INTERACTIV One member of a diff pair will show Analysis Failed when analyzing the design.
; n7 X8 ?6 w, [& n8 v/ N760178 ALLEGRO_EDITOR EXTRACT Crash Allegro when executing extracta command for big size design(size of .brd- j% k' u+ p% S% L
761391 SIG_EXPLORER OTHER Incorrect rise time
) _, }9 D* i9 Y: p762402 ALLEGRO_EDITOR MANUFACT When photoplot(RS274X) of MM unit was loaded, shape was broken.8 c0 e: i; y g4 u: ?
762783 SIG_EXPLORER INTERACTIV sigxp - coupled tline on stackup layer should show solved impedance
' m3 }. ^4 m; e+ ]9 z% }2 n- {763150 ALLEGRO_EDITOR OTHER Request - IPC356 output truncate the padstack size to fit into the columns 59-62 and 64-677 W# n- ^: h# W) I. m7 J8 t
763556 SIP_LAYOUT ASSY_RULE_CHECK Assembly Rules Checker is displaying an array of confusing DRC's on a Soldermask shape.8 d1 J8 r6 z' `4 u% M
764399 SPECCTRA ROUTE Manually routed trace in Allegro are ripped OFF after routing in SPECCTRA using Route > Route Editor.
8 C" H8 d0 Z5 n' p, O+ M9 }; c) X764475 SIG_EXPLORER INTERACTIV topologies from earlier versions cannot be opened in 16.2 on a machine
6 M G4 U$ Z. M' y7 Q765287 ALLEGRO_EDITOR PAD_EDITOR attempting to open padstack fails with - database has a non-recoverable corruption.
9 x9 b( k& ^4 A! [+ l( {' {; W# d766041 ALLEGRO_EDITOR OTHER Auto B/B via generator incorrectly defines some BB vias- S* I. Z8 V( P, |( m2 b; r
766153 ALLEGRO_EDITOR SKILL Allegro crashes when trying to extract padstack information
1 w9 @# J( t# [% a \: {, n766611 ALLEGRO_EDITOR EDIT_ETCH slide creates DRCs in ARK area& T! M1 D/ |* W% R: C, u
767041 CONCEPT_HDL CORE The tap command failed because the specified tap body CTAP is invalid# B' M# d8 U* B! R+ m# }4 D
767146 FLOWS PROJMGR Project manager open last open .cpm in 15.7 version not in 16.3" T% Q+ p; i( D+ I) ^# {3 M
767526 FLOWS PROJMGR Project Manager customization does not work
0 q. K9 D2 S' Y, \. W767671 APD DATABASE Crash creating cline with axlDBCreatePath() on this database.
# }8 S. C( N- J) x( }/ L767951 ALLEGRO_EDITOR DATABASE color net param file omits nets with bus brackets in the name' V0 X% J' ~" Z5 P- S3 g9 p4 n
768168 CONCEPT_HDL CORE Fontsize on instances changes when doing backannotation/ G" I5 J: W; ]
768207 CAPTURE STABILITY Capture crash while editing properties
( N1 g B* @. F3 l768734 CAPTURE PROPERTY_EDITOR Properties of title block are not getting editted through spread sheet./ a8 [! B# c! y. v0 b
768832 APD DRC_CONSTRAINTS Following Performance Advisor instructions results in much longer DRC check time.0 {) k) D( c, h4 H# S6 I j0 r
768990 F2B PACKAGERXL RFSIP architect 16.3 85Y Schematic to SiP fails due to softinclude in cds.lib file this problem does not occur on 16.29 z3 c4 N8 V& a
769097 SIG_INTEGRITY GEOMETRY_EXTRACT Sip Digital SI-Bus Simulation function will shut down auomatically when it is running1 N% W) X. u) |0 K9 J- H7 c
769235 SPIF OTHER need to be able to remove mbs_spif* properties added by mbs2brd6 x" M# f& F2 v* f+ {
769326 CONSTRAINT_MGR DATABASE Length by Layer crashing- R1 y! u: B. y4 U
769336 ALLEGRO_EDITOR TESTPREP testprep density - returns Unable to add the PROBE_DENSITY subclasses.
& ~+ l& P0 @. ?. k _$ o- l769458 ALLEGRO_EDITOR OTHER SMD Jumper has a problem about the connection point when using the Add Jumper! _5 q: z0 D- l& F2 z& Z9 D0 A) w) j
769845 ALLEGRO_EDITOR EDIT_ETCH Diffpair routing out affected by line to line spacing rule.! E% G1 Q* x- n* K
769934 SIP_LAYOUT WIREBOND Duplicate Finger Name.
$ E! X9 ]. g3 O) ~* y& n770006 ALLEGRO_EDITOR OTHER Ratsnest_schedule[Power_AND_Ground] can not show figure without move symbol.
# _' i: f k: H* o }, Y7 z- \770125 ALLEGRO_EDITOR DATABASE PCB SI GXL Via Labels grayed out on formand labels not visible on the canvas
* d0 f1 }1 a+ i) Z9 O( z H770212 ALLEGRO_EDITOR DRC_CONSTR Incorrect Etch Turn under SMD pad DRC error on this board% m0 s% |0 Q2 Q2 S$ G5 M2 B
770230 ALLEGRO_EDITOR ARTWORK Artwork fails to suppress unconnected pads on pins with the net_short property.3 h4 O/ c; p. a Q& X' Z
770233 ALLEGRO_EDITOR MANUFACT Fillets are not behaving as intended.& `' V% @. O) {& J, x
770442 SCM PACKAGER Error during Export Physical - The subdesign block instances ares not updated with reuse properties
+ D9 r2 ]; _' _$ B5 h; O770556 CONSTRAINT_MGR ANALYSIS PCB Editor's Constraint Manager not updating custom constraint cell.# m t$ _1 m8 I0 e
770861 ALLEGRO_EDITOR PADS_IN PADS translation fails with no error message" z$ P. [* {) U: X0 k5 ^3 O
770872 SIG_INTEGRITY OTHER Opening Orcad PCB Editor for this board takes Performance License as well: \2 G/ }/ Q) C/ ~# B$ l; r& ]/ L
771117 ALLEGRO_EDITOR DRC_CONSTR Allegro PCB Editor crashes on Update DRC-16.3/hotfix006
) {& s* K% q- [' x771181 ALLEGRO_EDITOR PLACEMENT Component deleted completely from board file after we Mirror and rotate them while moving them.
; \+ ~& v0 U/ `* \1 j! N: U0 @771256 ALLEGRO_EDITOR DRC_CONSTR Update DRC consumes system memory and crashes allegro after approx 30 minutes
, v |$ ~" k' D771423 ALLEGRO_EDITOR SHAPE Shapes - Update to Smooth - Low on available memory please exit the program.
8 R2 R( }+ \0 w* Y/ l771456 ALLEGRO_EDITOR EDIT_ETCH Allegro 16.3 crashes when using arrow keys
4 l7 V5 y! J+ e0 K, W c8 ]' y771719 PSPICE MODELEDITOR Can not generate a DEHDL symbol from Model Editor, because no Capture license.' ?' p# Q- ]: R( J: n
771765 ALLEGRO_EDITOR PADS_IN PADS translation fails to translate symbol/ x" P* k" Q4 Z% C9 W$ Z6 X
771766 ALLEGRO_EDITOR DRC_CONSTR Moving certain components takes a long time on this board database." e- Q/ A: ]; d' q; F8 x
771815 SIP_LAYOUT IO_PLANNER SiP OA co-design flow does not allow a save to the .sip file after modifications in IOP1 m9 t* s% Y" j9 k
773072 SIP_LAYOUT ASSY_RULE_CHECK wire to wire same profile
; h5 C0 ]& o/ E# R; Q* }773126 CONSTRAINT_MGR UI_FORMS Constraint Manager "Value Filtering" for Topology Schedule is missing TEMPLATE and "UserDefined") _% |& H. K" a* ]
773179 ALLEGRO_EDITOR PAD_EDITOR pad_designer crashed when attemting to delete internal name layer.
+ g) V" a$ U9 [4 k2 x5 c7 E773229 ALLEGRO_EDITOR OTHER Netrev never end importing netlist generated from Capture CIS
: o+ W! f: t$ V773329 ALLEGRO_EDITOR MANUFACT Allegro closes when performing a Linear dimensioning and then selecting the undo icon.1 }" Z9 t' Z) s' Q. @
773483 ALLEGRO_EDITOR MODULES place module problem& u0 m* @+ T h, |% ~
774036 ALLEGRO_EDITOR INTERACTIV Rats not shown after move->mirror command0 x" I: Y' Y4 v8 A
774170 ALLEGRO_EDITOR DATABASE DBDOCTOR fixes Error but it reappears and Artwork fails9 x& ]$ F% S% c- ?7 X
774602 SCM OTHER ASA crash while working with hierarchy! {) N9 B- X* }+ N
774643 CONCEPT_HDL CORE DEHDL crash on edit of attributes
3 E2 _, ?( T d" ?( n775201 ALLEGRO_EDITOR SKILL Color palette can only be changed one time using skill commands7 {% ?2 N' g' d- k2 u* _6 `
775815 SIP_LAYOUT WIREBOND Unused wire profile once purged using wire profile editor are still available in CM and Color dialog
$ s, K) r( G1 L# }4 l6 E9 b# K775826 SIP_LAYOUT WIREBOND Cannot change the Wire Profiles on the wirebonds in this design$ L2 c/ v9 Z, ~" f- |. E
775842 SIP_LAYOUT WIZARDS Die text in wizard is changing DIE location when origin set in DIE text file is other than 0, 0
4 T v3 \5 z* J9 }: }5 J7 K# O- _7 }* ^5 P" `' |/ e- p
DATE: 04-23-2010 HOTFIX VERSION: 007
8 O5 `7 b, |# |/ \0 `===================================================================================================================================( V0 h8 Q6 k. O5 s' {0 W \
CCRID PRODUCT PRODUCTLEVEL2 TITLE
: n9 D" I* m) b1 v+ h+ `===================================================================================================================================! m- g2 V+ a+ d4 s5 D c T/ r
721859 ALLEGRO_EDITOR OTHER update shape to smooth creates tmp file on remote file server working dir why?
! S2 J6 S, B `( k2 l740201 SPECCTRA_MENT_ IMPORT Wrong stackup order after translating from mbs2sp1 |6 M0 Y4 ~! Y: R% t* l
744797 SIP_LAYOUT OTHER Cannot Copy a connector (IO) symbol in APD and SiP tools: K' C% L O% B/ p
747831 CIS CONFIGURATION There is a delay of 5 to 10 mins in opening SQL database in V16.2 and V16.3. It is fine in V16.0.
- C; j& ~. I I8 q1 H( z f) w! g: l747848 CIS CONFIGURATION Unable to configure CIS with Oracle database due to Capture crash.2 [2 ?7 X6 C' D& S( b, U
751372 CAPTURE OTHER Copy / Paste Issue in capture 16.3
- Z+ c6 {" X% T& S' V& T" N$ u757434 ALLEGRO_EDITOR MODULES Allegro hangs the board file after creating Placement Replicate circuit.* l3 j# _- F3 v0 S+ `
759906 CIS PART_MANAGER Property copy from one to several parts doesn't work4 t8 F0 Z. g1 X' f
760154 PSPICE NETLISTER Model parameter (Tj) is not affecting Smoke Analysis result1 T& I- e# s" {- z* h; c
761177 CIS OTHER Error Message - Memory exhausted
1 ]/ H5 |5 l$ ^( X762602 CIS EXPLORE_DATABASE CIS doesn't open datasheet for parts if it is not stored at default Capture location.+ j8 o% ?. |2 c @ p! j
763677 APD EDIT_ETCH The "Via to Via Line Fattening" tool is inconsistent in which clines are changed.
$ v9 T; J$ g* f8 g% c/ a763715 CAPTURE NETLIST_OTHER A long pin name gets truncated upto 31 characters when the wirelist is created.
; J0 N4 x5 m: C R) W763878 CONSTRAINT_MGR DATABASE Why Pinpairs disappear after closing Constraint Manager?
) s0 o% {. F. Z1 B" N764020 CAPTURE NETLISTS Usernetl.dll has changed between 16.2 and 16.3
6 q( @/ R+ T9 g5 j- [' u) q6 O( u764101 APD EDIT_ETCH Perpendicular routing through a Region does not work when the region segment is drawn at an angle.3 I- q, f# ^+ v
764200 ALLEGRO_EDITOR DRC_CONSTR Via at smd fit drc on a via that is placed fully inside the padstack having custom pad
$ t' W+ ?2 e. Z. k& e, L- F! U764903 PSPICE ENVIRONMENT 'Run in Resume Mode' does not work in SPB 16.3
- N4 O0 Z& }; ~/ I765206 F2B PACKAGERXL Unable to feedback subsequent pin swaps from Allegro8 u( z) O9 U/ ]3 D! u- l' Z
765319 APD DRC_CONSTRAINTS Identical Constraints in Performance Advisor question# R7 x; ]' z+ X4 Z
765541 SIP_LAYOUT SHAPE Set via oversize value to 3 in dynamic shape instance parameters will make overlap shape.
4 a) T6 }6 m5 b9 g; `766147 APD EDIT_ETCH Resize/Respace Diff Pairs does not work on 45 and off angle
3 y" B4 n2 w' P2 u# L7 h766337 SIG_INTEGRITY GEOMETRY_EXTRACT Geometry of Via model Extracted from board file is not identical to Original Via geometry design
( j' y% F% A o7 }. y7 ^! o766443 ALLEGRO_EDITOR PADS_IN unable to translate PADS ascii to brd in 16.36 O* X7 U$ N1 A# C0 t" C3 I
766581 CIS CONFIGURATION In 16.3 capture.exe remains memory-resident after exit |6 Z, z9 {5 T# C2 V
767161 ALLEGRO_EDITOR SHAPE The behavior of Add Fillet command is different by Hotfix version.
G' {4 [" P! g& J' }767217 SIP_LAYOUT IMPORT_DATA The Die-Text In wizard and it is crashing on the "Finish" step.
8 j2 T O! N( { x767598 SIP_LAYOUT WIREBOND Can't wirebond SIP designs as it just hangs.* T9 `) p! v& T/ y6 ~) P
767832 ALLEGRO_EDITOR DRC_CONSTR Reducing Design Accuracy updates Physical Diffpair constraints wrongly
_4 A3 Q+ [5 q! `3 k768822 ALLEGRO_EDITOR SKILL axlSetParam return value is divided by 10 to the power of the design accuracy., r. n9 `' P( J! Z) ~) Z
769150 CIS PART_MANAGER Update All part Status on a group changes “Do Not Stuff” status to “Stuffed” in V61.3_ISR_5.
$ \* {7 i' U5 s# C( f) n
, m. H' L# Z0 h R& Z" O% i jDATE: 04-09-2010 HOTFIX VERSION: 006) J& K6 N' W0 M
===================================================================================================================================, o: M: ?" r5 d% ]3 {9 Y2 j
CCRID PRODUCT PRODUCTLEVEL2 TITLE2 ?# I% U8 q( p% i! \
===================================================================================================================================- I- w6 P! c% }, D
745241 CONSTRAINT_MGR TECHFILE Importing a tcf file automatically enables On-Line DRC., ~1 t% ~, A6 _( `! Y
752587 ALLEGRO_EDITOR PLACEMENT Uppercase File name(XX.mdd) for Placement replicate update on Linux.4 h( D" ?# A/ P6 ?9 e/ ]2 s, n
753626 CONCEPT_HDL CORE newgenasym error while saving the hierarchical block symbol
7 R8 [2 r3 w$ l' V753894 CAPTURE OTHER Case sensitive version control S/W
; P$ j& D) Z' g" o0 ^4 u754487 RF_PCB OTHER Various asymmetrical clearance problems uncovered - calculation issues?
7 w- Q# y( r' N4 D/ ~6 g758272 CONSTRAINT_MGR UI_FORMS Entering values on the Min/Max Propagation Delays worksheet hangs the application.
0 W% t8 T$ R; [0 ], }8 C# N758911 PSPICE PROBE Pspice crashes while exporting probe data using our sample project7 A0 x8 c# d$ x* ^
759871 CAPTURE PROPERTY_EDITOR Save option in Right Mouse Click on property editor of nets doesn't saves all the changes.
1 Q' a5 O# i3 Z% g* F) o7 N759890 SPECCTRA ROUTE Specctra autorouter ignoring prerouted nets
' [7 I0 y0 K K0 ~760067 ALLEGRO_EDITOR SHAPE Dynamic Shape not getting filled on board with odd angle placement and routing
! {) o2 p" w: Q760284 CONCEPT_HDL CORE Update Sheet Variables turns of the grid
7 i6 G, Q1 [" k& b760480 MODEL_INTEGRIT OTHER Message open clipboard failed when trying to open the rename/reorder dialog in Model Integrity4 L2 H0 I. a4 [/ D+ { |8 f: |
760667 ALLEGRO_EDITOR PADS_IN The pads_in.exe translate incorrect drill shape from PADS 2005 ascii database.; ^- [$ ~% K+ q V, C8 K4 l
760741 ALLEGRO_EDITOR MENTOR mbs2brd does not work in 16.3 but works in 16.2
+ X8 ~7 n2 T0 K. O760810 CONSTRAINT_MGR INTERACTIV Deleting Region Deletes NCCs
! z& c0 I% @! J) K4 f' C k761114 PSPICE PROBE Refresh issue in Display > Cursor window
2 C9 I8 w+ Y3 _; K+ d4 b) L& T761180 ALLEGRO_EDITOR DRC_CONSTR Via_at_smd not working for custom shaped padstacks.- }# s! Y. N; f8 @3 d
761305 SPIF OTHER Allegro crash when seleting any of the Route - PCB Router - submenu items.- }* h: u' F, q
761376 ALLEGRO_EDITOR PAD_EDITOR Wizard_Template_Path is not considered for symbol template look-up ?
; {4 l3 N6 d( x5 h. W761416 ALLEGRO_EDITOR DATABASE Allegro crash on chaning the subclass for group of clines
& P5 M: W3 j( ~8 k761492 ALLEGRO_EDITOR SKILL about axlTransformObject function
. ~+ q- @6 l$ q+ s761518 F2B PACKAGERXL about mismatch library path between cds.lib and actual4 I( Q! H. H' t
761737 ALLEGRO_EDITOR OTHER Running Dbdoctor after executing Skill is giving symbol fit error for the .dra file& c _- y' a) E$ L5 Y, Y
762155 ALLEGRO_EDITOR SYMBOL Updating a symbol changes the netname of the cline resulting in drcs.; k% s" E% Z( T* F; V1 q9 X2 s
762181 ALLEGRO_EDITOR OTHER Allegro netrev crashes for long device name in PST* files* m3 p- p! l+ \ @- N
762316 ALLEGRO_EDITOR MANUFACT Allegro disappears on Adding dimensions for the symbol file
( `) B$ p' z6 ~* }762792 ALLEGRO_EDITOR PADS_IN PADS_IN fails for SPB 16.39 j: i) u- v% m& H4 Y3 u A
763108 ALLEGRO_EDITOR SHAPE Z-copy shape create an error like VOID boundary may not cross itself( D3 j6 q9 l5 g- S# k
763134 SIG_INTEGRITY SIMULATION Bit 7 of a simulation is out of sync with rest of bus. It should be the same for all bus values.( `' C p2 |7 C
763149 CIS GEN_BOM CIS BOM in V16.3 is not correct if database has Quantity field and its value is 0.1 S9 Y- K, Z% ]: |0 Q; O; M9 z; B0 T: @
763296 ALLEGRO_EDITOR REFRESH The error was happened while doing the SUM
9 T) l* K$ [* m) p* T763303 ALLEGRO_EDITOR OTHER SMD Jumper has a problem while using the Add Jumper
6 n) q/ b( ?6 W) C6 _$ Y+ N763315 ALLEGRO_EDITOR PADS_IN pads_in got error message WARNING ERROR(SPMHDB-205)/ N/ `. ]' u/ `
763354 ALLEGRO_EDITOR PADS_IN Auto suppress redundant shape while using pads_in translator# }3 ?+ k4 w# R6 h
763428 ALLEGRO_EDITOR PADS_IN enhance pads_in.exe translate spacing and physical rule into Allegro.
, o( P9 p3 f5 e. O: d a763446 ALLEGRO_EDITOR REPORTS missing fillet is reporting pad without drill R; Z3 A R/ k% N1 x+ I
763448 ALLEGRO_EDITOR DRC_CONSTR Performance advisor shows Cset as unused nets when it is assigned to Diff pairs or xnets.
* `8 e0 H, \: \2 e763586 ALLEGRO_EDITOR DATABASE Allegro rounds off the value after decimal in CM
4 c* N( |8 U* Y( [9 a764077 CONCEPT_HDL CHECKPLUS The output predicate in the Graphical environment is not always returning the pin object for an output pin.
$ p/ n9 F% b% p* }6 J
5 P f D' I# P# ^2 z8 f) NDATE: 03-26-2010 HOTFIX VERSION: 005
0 {- ?4 Y4 a/ I3 I& E2 ~5 j===================================================================================================================================
) I1 D/ H/ T: d7 SCCRID PRODUCT PRODUCTLEVEL2 TITLE2 L1 S. f7 [: k: I# Z, A4 C4 i
===================================================================================================================================$ w4 Y; C, r# w
599819 SIP_LAYOUT 3D_VIEWER display soldermask by default in the 3d viewer
2 W) k- I, P7 G: j735992 CONCEPT_HDL CORE Create Test Schematic does not use the correct package type: g+ k% Z9 e; D0 P4 @ K2 e
743787 SIG_EXPLORER OTHER 16.3 SigXP crash if sigxp.run created by previous version exist.+ ^2 z# K) c6 e$ }) \% D1 S2 e
746320 CAPTURE NETLIST_ALLEGRO Remove Semi-colon from invalid pin-name check during netlisting. z$ _" c5 z3 q1 F
746444 ALLEGRO_EDITOR OTHER show element fails to display info on a via if it is in a module.
4 l8 L3 d' F. t) h746726 SIG_INTEGRITY SIGWAVE Save As and Open Dialogs open in last saved directory
1 i0 c a( A" n# a750080 CAPTURE NETLIST_ALLEGRO Improve error message ERROR(SPCODD-390)4 \% }8 Z/ r9 I4 o. P& q! V
750606 SIP_LAYOUT ASSY_RULE_CHECK Wire to BF same profile check) p) o. D( ^' ]( l
751492 CAPTURE FPGA Option to swap the pin-numbers rather than their locations in the Schematic after back-annotation
* `; e/ H4 u5 `& X2 e# f* b753834 CIS LINK_DATABASE_PA unable to link multiple database part. v+ e: [+ p/ }4 A3 l7 O
753990 F2B PACKAGERXL Delay in opening the subdesign tab in the Export Physical setup in SPB 16.38 \' M) E' ]% _) x$ f; w3 \ d
754328 LAYOUT TRANSLATORS L2A gives error Subclass name TOP not valid Allegro subcls with s029 hotfix4 x( b( X& s! H+ v& A" S$ c8 a
754434 CONSTRAINT_MGR OTHER allegro crashes when deleting matched group
; M: T. F! `; o& w: O755111 ALLEGRO_EDITOR INTERACTIV "ALT_SYMBOLS_HARD TRUE" property does not work when I mirrored symbol using move command in 16.3.
8 }1 e; B) c, Y. V R; o) j! b' i756131 PSPICE SIMULATOR Capture crashes while re-running simulation$ T* Y. V2 R( G1 M5 K" G1 m5 |
756148 PSPICE PROBE Zoom Area in Probe Window does not work for digital signal in SPB163
' z$ t+ `" l S$ a5 P: Y7 r, ~756169 SIG_EXPLORER OTHER Signal Explorer crashing due to sigsimcntl.dat
8 u# F& h6 w, A756176 PSPICE PROBE Trace color is wrongly interpreted in PSpice probe window.
1 c+ t" M, M, L N4 h9 T756224 SIG_INTEGRITY SIMULATION Simulation aborts reporting that VIA models have changed0 `% l8 j& n' G3 N+ d1 h+ @) z! i; }
756281 ALLEGRO_EDITOR OTHER Why *.sav file cannot be recovered from PCB Editor utilities?
- w( Z9 K6 r/ o' g8 n& m: J& X# ?4 q756673 SIP_LAYOUT ASSY_RULE_CHECK Running ADRC Metal to metal checks causes false X-D DRCs, cannot clear them and trying crashes the tool% N, I- w# }2 G3 J, R( @
756918 ALLEGRO_EDITOR OTHER Allegro angular dimensions working incorrect in 16.38 I6 R2 _0 d: u2 ~+ M C
756932 ALLEGRO_EDITOR CREATE_SYM Create symbol fails with error duplicate pin number
3 b7 e% Z1 h) s* v8 m/ T8 r756976 ALLEGRO_EDITOR SKILL axlChangeWidth always return nil in Allegro version 16.3) ]) N# j0 ^, F% \2 V4 R" f6 f$ n
757000 PSPICE NETLISTER Incorrect Hierarchical Format Netlist created
8 W* J( W+ `( s757406 APD OTHER Implement Segment over void features in APD L: [! P. I7 K) Y/ I4 k) R7 S
757624 SIG_EXPLORER OTHER Sigxp runtime error when simulation is run and exit without saving the topology
; c! p6 P( h0 B5 K5 h3 f: [/ h( C" k757820 ALLEGRO_EDITOR SHAPE Shape does not void to hole if there is no pad7 c2 P" o; p `: t# a
758009 ALLEGRO_EDITOR OTHER Export > Library (MECH_SYM) adds a new subclass NCROUTE_PATH, data moved from one subclass to another.! X/ }, n2 w% U4 A+ f
758022 CAPTURE DRC Capture crash while running DRC with “Run Physical Rules” checkbox.2 s# b+ @! c+ k9 u+ Y0 r
758190 ALLEGRO_EDITOR PAD_EDITOR PCB Editor crashing on pin move in this design# A# w# E! y) B+ C: d7 A# K
758374 F2B DESIGNVARI Problem with Mechanical part in Variant Editor
2 i+ J$ \/ I8 V- C) d/ l2 j9 ?! x758471 SIG_INTEGRITY OTHER Differential impedance does not change on changing the etch effect values.
4 G& k" O/ O2 r9 N: P758490 CIS CRYSTAL_REPORTS Different crystal report output in 16.3 than from 16.2
4 v2 C( i ~# d6 A' c: c( t758498 CAPTURE NETLISTS PCB Editor netlister hangs
; `; m! L4 ~( }+ _" Z758584 APD SHAPE Shape not voiding all elements. L" d$ ]6 ?8 D
758886 ALLEGRO_EDITOR REPORTS Total number of nets is wrong into Testprep Report9 y& D3 N! w2 Q$ I/ X; O$ Y
759146 ALLEGRO_EDITOR SKILL The title is not displayed in the form by the version.7 m7 m9 v+ t4 [7 `+ w
759339 ALLEGRO_EDITOR ARTWORK artwork output fails by SPB16.x.+ O/ G: W# D( N( \1 y+ U( \# i0 M
759591 ALLEGRO_EDITOR SKILL axlSetParam fails and does not round the value as indicated by the warning message! u K+ m. a! k" [) D& Q- U
759816 CONSTRAINT_MGR OTHER Allegro Hangs when double click on a Bus in CM
K: o h- E2 K$ D% Q759947 APD OTHER Need an a way to convert Lines into Clines
2 h. c) v, z4 N& ?760353 ALLEGRO_EDITOR MANUFACT Allegro crashes and creates a .sav file on running the silkscreen command from Manufacture > Silkscreen A$ q k) x- R. X
760432 ALLEGRO_EDITOR PARTITION Unable to remove fixed property after partition import( b% T; r' \1 d1 q9 ]
760638 ALLEGRO_EDITOR PADS_IN pads_in translator can not handle " PINPAIRGROUP ".3 F( u. |, n+ W$ u. l" {- q: |2 J
760734 ALLEGRO_EDITOR SHAPE Different therma contacts on rotated partsl
1 ]+ w) ?3 o7 g7 }761436 CAPTURE NETLIST_ALLEGRO SPCODD-53 Error when creating netlist with PACK_SHORT
, a& E+ }. T. d) _3 V, \
- E" D. u* \' H& ^DATE: 03-12-2010 HOTFIX VERSION: 004# n" |% ]3 U6 w4 j/ \! T) ]. z7 ]
===================================================================================================================================0 A' a' L5 C9 {& w m8 I6 v
CCRID PRODUCT PRODUCTLEVEL2 TITLE
7 {) B+ `4 a8 c/ P) p===================================================================================================================================$ J) Z: w) _# }( ^! z& I
689495 ALLEGRO_EDITOR DATABASE corrupt database
4 ~7 d/ P" s# K% W725944 SIG_INTEGRITY GEOMETRY_EXTRACT xtalk make allegro freeze and never give hands8 ^# w4 n; q- g9 H# B
732604 SIP_LAYOUT SHAPE Shape Issue - added shape will not clear around other elements.
; s+ v! c6 n, B$ |740106 PSPICE NETLISTER The "Enable PSpice AA Support for Legacy" option does not give the Desired Monte Carlo results" Q" z1 k, q: P& z7 T+ H
744259 SCM UI Signal order reversed when a Vectored Signal name is renamed in reverse V3 t, W8 f: z: X T# }
745554 SIG_INTEGRITY GEOMETRY_EXTRACT Time to get Xtalk simulation result in 16.2 is lower than acceptable by comparing the time in 15.75 Z) c6 I5 i$ I; a3 P4 j" d
745595 RF_PCB FE_IFF_IMPORT import iff RF_PCB give an empty block! m9 Z+ N" L# j, }9 z% A, v' `% x
747133 CAPTURE STABILITY ERROR [DSM0006] Unable to save
. A7 e( @+ c9 K( D747679 CAPTURE STABILITY Trying to Save the Design in 16.2 format gives DSM0006 Error and crashes Capture
+ s( C) d( |/ U# b" h% d750460 CIS FOOTPRINT_VIEW 3D footprint viewer doesn't shows the footprints+ q* I3 |+ @1 _1 Z6 P2 U1 ^$ {
750777 SIG_INTEGRITY OTHER Trace impedance showing wrong
9 C) c% r& n9 w* n751424 ALLEGRO_EDITOR DRC_CONSTR Unexpacted DRC for Shape to Route Keepout, [ t# `; I, ]1 ?/ Q' b x7 q, S' [
751897 SIP_LAYOUT SPECCTRA_IF Radial Router crashing SiP tool- W3 P6 r- T! {8 L
752029 SCM OTHER Cross probing not working between SCM and Allegro Editor in Linux Environment# ^$ e% r( w8 v& s. f
752450 APD PADSTACK_EDITOR APD crashes when selecting a User Definable Mask Layers./ M5 I% Q+ R5 a% [ l1 K! v
752581 PSPICE PROBE Pspice probe window crash9 B1 \- K8 X" H- C! ~/ T
752709 ALLEGRO_EDITOR PLOTTING Sheet content doesnot plots title block
3 J" ? T; I! ?* D6 p752908 ALLEGRO_EDITOR INTERFACES Output from Export > DXF shows one instance of a via on the wrong layer, N* h1 A' e( H. q) J6 ^
753226 ALLEGRO_EDITOR OTHER File > Change Editor doesn't shows the default Product Options
5 \8 g& {% ~) C. U1 c2 H' e1 r753622 ALLEGRO_EDITOR GRAPHICS Enahnce capture image command to default the save as location to working dir
- a" q; S9 X' p1 p- p' ]0 I2 j753773 APD WIREBOND Requesting the option to set the diameter of the default WB_TACKPOINT power ring pad.
2 x" u X: H# G+ }753778 APD IMPORT_DATA Import NA2 displays the design momentarily and then crashes
3 F' h$ J) V7 G9 p* \% U; B753866 SIG_INTEGRITY OTHER about Select by Polygon after move command _" ^5 e' r9 t: a; d4 Z; T. i
753958 CAPTURE OTHER Capture V16.3 is extremely slow while edting schematics of design placed on network drive via VPN.3 f8 W2 Q+ C5 a* j6 s; x m
754050 ALLEGRO_EDITOR UI_FORMS Why show element window disappears when scriptmode is set invisible
& e5 n1 i h+ W; g+ W" F754143 SIP_LAYOUT OTHER SiP Package Design Integrity - running Extra Cline segments generates report without Layer number
. d8 o& ^! G: P% E4 ]: w754327 ALLEGRO_EDITOR OTHER Rename Sub Class is not working as desired.7 M5 k! P! k; L, G- t* \
754364 ALLEGRO_EDITOR PLACEMENT Crash when applying placement replication
1 N2 N; M0 @) l; ?% [% U754462 ALLEGRO_EDITOR SHAPE Allegro circular dynamic shape fails to fill9 Y7 v7 N0 J8 G N& @+ ?
754819 ALLEGRO_EDITOR OTHER Create details shows wrong graphics for filled curves
; v/ u: E0 n: f2 ^+ H" \- d755176 ALLEGRO_EDITOR PADS_IN Pads translation succeeds in v16.2 but fails in v16.3 on this ASCII file
$ K, ^" Y8 l, h9 O. _+ h755256 ALLEGRO_EDITOR OTHER Attached script is crashing the designs in v16.3
8 M# ~6 |) i% g) Z {" v755610 CONCEPT_HDL CREFER Cref hyper links does not work for signals where number "0" used to define the zone for page border
* D" C9 W' C8 L+ N; w755787 ALLEGRO_EDITOR EDIT_ETCH crash using resize_respace_dp command$ @3 v5 j+ G# q8 i
755881 ALLEGRO_EDITOR DATABASE Swap component crashes application) o; w* k" o9 W
756092 CAPTURE PROPERTY_EDITOR property editor flickers and loops on value edits* e* c- b1 D0 f2 W; g* \
; L" S6 _# F/ c$ U9 n2 M6 q9 mDATE: 02-23-2010 HOTFIX VERSION: 003& T- i7 A: E+ T$ m' f! R
===================================================================================================================================
9 k1 \5 m9 h: p1 S1 g$ d& E( X% P3 lCCRID PRODUCT PRODUCTLEVEL2 TITLE5 g: H! z# [$ [/ V
===================================================================================================================================) r/ V0 e+ L q; t. D+ j0 `
263504 CONCEPT_HDL CHECKPLUS Checkplus fails to run if crefrpt exists in the design( }4 _/ K1 J6 x, \6 \
726836 ALLEGRO_EDITOR SKILL axlGeo2Str() and axlGeoEqual() return different results
, n9 H" V: H- a0 V730820 SIP_LAYOUT PADSTACK_EDITOR Changing the Via diameter will cause the SiP tool to crash
% F" y* r- B) h735193 CAPTURE FONTS Pin_names and Pin_numbers get convertred into darkened blocks in ‘Zoom to all’ view in V16.2.
, W( B# M$ p: i& ]737307 SIG_INTEGRITY GEOMETRY_EXTRACT differential pair extraction to sigxp fails to extract coupled sparam via models
3 o) s1 P4 S5 F; k, O3 s740936 ALLEGRO_EDITOR SYMBOL Confusing error message during Create Symbol* `' m8 ?! s. J$ R( I" A0 G
744191 ALLEGRO_EDITOR EDIT_ETCH Arc routing enhancement
7 W& z- p8 B4 q/ |1 y- R8 G( }744497 ALLEGRO_EDITOR INTERACTIV PCB Editor Crashes with Data Customization Feature
& S+ }% _& P1 u: }746572 ALLEGRO_EDITOR DATABASE Reoccuring error in attribute pointer to attribute invalid on dra.
* |2 K1 y+ {: `! ~$ O4 O746978 SIG_INTEGRITY SIGWAVE 2 licenses were used for SigXP and SigWave.9 N/ `+ H" W! S& _( F
747219 SIP_LAYOUT SHAPE Dynamic Filleting not working with odd angles9 Q* ?8 K6 q2 C9 k- g* z/ P
747593 ALLEGRO_EDITOR PADS_IN Some RULE_SETS cause the PADS translation to fail.! x; ]3 K' X# i9 b! R
747746 ALLEGRO_EDITOR OTHER Request for more detail in downrev.log file/ P$ z7 I1 D. `6 C+ j9 u
748033 GRE IFP_INTERACTIVE Enhancement in GRE where Show Element on Bundleshould show the total number of nets that are part of the bundle4 o/ |; G; x: I: \
748333 ALLEGRO_EDITOR OTHER place by schematic page number not showing pages correctly/ O& B2 Z T) ~& m. f
748375 ALLEGRO_EDITOR MANUFACT gloss - line smoothing causes crash
5 z7 y+ V0 r0 i7 A3 w; K/ a748818 ALLEGRO_EDITOR DRC_CONSTR Undesired DRCs shown in allegro 16.3 while moving component and the same are removed by update DRC4 ?. ]" q1 e& e8 D7 l+ k- W; P
748865 CONSTRAINT_MGR OTHER Allegro 16.3 slow to move component with CM open, b. r- T: |+ A
749009 APD WIREBOND a part of function of the finger alinement doesn't work: K) w4 J" f( h2 \
749162 SIG_EXPLORER INTERACTIV Unable to proceed after RMB > Preference > Cancel2 S3 A( s) a" m/ m2 p! G9 e( V$ a$ l
749307 ALLEGRO_EDITOR MENTOR mbs2brd fails with error VIF_Allegro_Write
7 c: F3 D2 \0 q6 M/ I749435 CIS DESIGN_VARIANT Cannot create variant part in 16.3- `- b4 r8 i/ X
749854 APD PADSTACK_EDITOR The value of user-defined mask layer is not retained in the design.
- b \8 ?# _7 {; Q6 s) j# b( |749891 ALLEGRO_EDITOR PARTITION Unable to delete existing partitions+ }9 p: C- K+ r) n/ P
749949 SIG_EXPLORER EXTRACTTOP A Topology extraction fails using APD and SiP series with the latest hotfix(SPB16.30.001).* x: J9 i0 h- e7 B
750008 CAPTURE NETLIST_ALLEGRO Netlist different in SPB 16.3 and after installing SPB 16.3 hotfix 1
9 K1 _+ ~- j/ y7 P, O5 f750591 ALLEGRO_EDITOR DATABASE Analyze diff pair object fails to display uncopled lenght values.
, n, a5 K1 z& O' n, f q" s750888 SPECCTRA ROUTE specctra is crashing while routing
7 [" R) O; c8 O0 M751204 F2B DESIGNVARI Design difference crashes while reading funcview: j) m0 e3 H; d. `& x
751398 ALLEGRO_EDITOR OTHER Allegro Crash when Edit is selected in Setup > Outline > Room outline
9 y. X& p/ l" o9 j751578 ALLEGRO_EDITOR PADS_IN pads_in hangs while conversion
! T% Z! r: y. ?% D& }+ g! ]- M; {+ P8 |: F
DATE: 02-09-2010 HOTFIX VERSION: 002
$ R5 L3 Z$ R6 S+ W===================================================================================================================================) k0 b2 @2 e# ^0 g% ?2 R$ _
CCRID PRODUCT PRODUCTLEVEL2 TITLE" _& Y- n& p) x1 O
===================================================================================================================================
: G- u1 Y, O( h527012 SIG_INTEGRITY IRDROP Severe Memory leak in IRDrop" @0 Z2 V( M' C! m: q( d% V
623678 PCB_LIBRARIAN CORE PDV freezes when changing grid
% N5 M+ C6 y" Q1 J0 X0 m672592 ALLEGRO_EDITOR SHAPE Shape does not void correctly untill a clearance oversize value is added
0 J/ K1 m m# m! p, U) _8 O688062 PCB_LIBRARIAN CORE PDV Strange characters appear when copying text into Bus Arrows ( Text symbols)
1 O" K1 Y! {% t9 @+ p1 L6 l6 c+ m710170 SIG_INTEGRITY IRDROP Run IR Drop even if all components on the net are not placed.
+ N6 c+ O) h+ `9 [7 `, v710174 SIG_INTEGRITY IRDROP Audit function for IR Drop.3 L# c* O! ~( _: e
726833 PSPICE DEHDL Modify the methodology for migrating 15.7 and 16.2 users of ConceptPSpice
8 I$ H C7 p( M730717 SCM UI Unable to delete a zero connection signal in SLP which has a pull-up3 l, ^6 }6 f* \9 S6 m
731017 ALLEGRO_EDITOR DRC_CONSTR DRC's show out of date when artwork is run
# _8 v# j, l; T; h4 n+ [& G732145 CONCEPT_HDL OTHER Incorrectly generated VHDL netlist; ?/ i3 l C) F% ^9 N9 q( B
740123 ALLEGRO_EDITOR GRAPHICS Capture Image command fillin missing from jrl and script files; q1 {9 @8 G7 w, [2 }3 b
740278 ALLEGRO_EDITOR OTHER Jumper fucntion for Single Side PCB Design0 q, a# f& l- e5 h0 E! f: }$ z
740656 ALLEGRO_EDITOR GRAPHICS Can we place custdatatips.cdt file on a site level for SPB16.3
$ d1 D9 T" L; t1 R5 B+ ~* N7 r741222 CONCEPT_HDL CORE Replace command (in Windows mode) causes crash" t5 D$ @3 b( ?0 L1 d
742389 ALLEGRO_EDITOR EDIT_ETCH Change or add message when using Countour route
' i# @0 A1 x; t& L9 ?6 r- ~743275 APD DATABASE With DRC enabled, this design seg faults in axldbid.c (solaris only). DRC update takes orders of magnitude longer on sun+ Z$ a2 E; h! l3 T/ S& a
743623 F2B PACKAGERXL Pxl error when using pack_ignore on reuse blocks- n/ s! x# k# N' O7 P
744348 F2B BOM PART_NAME column getting word wrapped inspite of sufficient space in the HTML BOM report.
9 d! Q7 {( \3 ?3 _/ A745062 CONSTRAINT_MGR OTHER import techfile does not add new layers in cross section; B1 x) z8 K0 Z' o
745148 ALLEGRO_EDITOR GRAPHICS Allegro ptf driven HEIGHT value not pushed into 3D Viewer9 h$ T3 H8 ?3 v; M9 @2 W4 w
745301 ALLEGRO_EDITOR DATABASE Allegro 16.3 crsh on moving component
0 a6 F& L' ] ~2 C" s9 B745518 ALLEGRO_EDITOR DRC_CONSTR DRCs not shown when "Enable Antipads as Route keepout is checked in"
9 i' n2 } y- l9 R6 U6 r745745 SIP_LAYOUT WIZARDS Die Text In changing the pin names on duplicates) s; ` f8 q. a
745785 CONSTRAINT_MGR UI_FORMS Unnecessary window opens when the cell in PCSet By layer worksheet was clicked.( R( D N* p x) c6 y0 J9 K8 o3 D
746002 CONCEPT_HDL CREFER Could not find pc.db in the root design* y0 `/ O5 G2 P) p+ } z8 F% j
746010 CONSTRAINT_MGR SCHEM_FTB Updating the brd file using the "Import Changes Only" option overwrites the modified constraints in! W, t3 o3 J4 r1 q, K
746080 CONSTRAINT_MGR OTHER Click Constraint Manager filter icons crash software
% ^- [) N; F2 X' f1 m0 ~746137 APD IMPORT_DATA Import > NA2 not transalating certain layers and padstack sizes/ L/ |, E8 Y2 x$ k# S2 _6 F" m
746370 ALLEGRO_EDITOR GRAPHICS Setting infinite_cursor_bug_nt variable flips mouse movement on flip design+ L1 L `3 Q3 z3 @3 W5 o. }# s3 h
746519 CONCEPT_HDL CHECKPLUS CheckPlus the if statement is not seeing the True condition or the output predicate is not returning the True condition., d q- _+ J* K) C4 @# U# C) s6 G
746546 PCB_LIBRARIAN VERIFICATION con2con choosing incorrect PART_NAME in PTF File during verification# Z# C1 _9 Y Z
746865 CONCEPT_HDL CORE Tool generated pspice net names in core concept design cause short with copy all.
( K4 z( A5 }3 @& I( f/ Z747636 SIP_RF OTHER RFSIP Layout RF Module Export chips & connectivity is not writing die attach method to chips file; P0 E' A1 D% T/ s
& o* Z: X8 y ~6 C1 j/ d
DATE: 01-31-2010 HOTFIX VERSION: 001
M+ G1 m W F" |1 g===================================================================================================================================* I3 f: v/ ], c
CCRID PRODUCT PRODUCTLEVEL2 TITLE, e, n; x3 B" F3 t/ r
===================================================================================================================================" _5 P t7 `' O+ a7 ?3 n3 Y
491042 CONCEPT_HDL SECTION Prevent PackagerXL from changing visibility on SEC attribute
( f. P/ I2 A( V. s496910 CAPTURE NETLIST_ALLEGRO Inconsistent netlist creation
5 Y1 ]' C) A0 t4 h, ~( X558783 PSPICE NETLISTER Why do Models with "awb*" prefix need wirte permissions to "*.ind" files?$ l$ a' I, Z: a* J
643241 CAPTURE SCHEMATIC_EDITOR OrCAD crashed while replacing cache
: `" G8 Z) @# w2 H/ D654292 ALLEGRO_EDITOR DATABASE Propagation Delay constraint behaves differently between 16.01 and 16.2
2 ^+ v( U4 d1 R) S662829 CONCEPT_HDL GLOBALCHANGE Global Update should honor property visibility settings in ppt_optionset1 Q8 y/ x4 R) O* ^' H3 S `- D
672718 SIP_LAYOUT EXPORT_DATA "Export>Symbol Spreadsheet" should export a .cvf not a .txt
0 o3 k; o0 O% D+ }+ l5 i676233 CAPTURE NETLIST_ALLEGRO Cross probing stops working if design name has dots
+ v6 K) ]# U! |; _! d$ f678739 CONCEPT_HDL CONSTRAINT_MGR Manually added targets in matchgroups lost when reopen CM S" ?' A: O0 J9 H/ f7 ]: r* Y% ~4 M! l
690618 F2B BOM Write protected template.bom fails to write callouts0 e1 [$ _) t1 o" D/ F5 r
700246 CIS LINK_DATABASE_PA Need option to update symbol always when linking part in CIS. s+ s8 x( G) C U& Z( M* @ o: N2 s
705393 CONCEPT_HDL CORE ConceptHDL crashes while switching to another hierarchy level under File > Plot Preview.
# p6 G8 S9 m" J9 w7 w5 z% j3 a. O+ y708634 ALLEGRO_EDITOR SHAPE Shapes getting incorrectly displayed in 16.20 N8 c6 H# Y, \% ] f3 z5 {
708950 CONCEPT_HDL CORE Tool crashes while trying to change the text on the schematic using a text editor.
j8 l6 v- x. o709823 ALLEGRO_EDITOR OTHER Arcs not converted properly when upgrading symbols& I$ r2 f8 x2 {" f/ A4 U: K
713964 F2B PACKAGERXL Net property Probe_Number is getting changed during the packaging run3 [$ l4 n# A+ _ b! N+ ^, c. K
718119 F2B BOM Exclude the callout file name from the template.bom file
& W) V" Y2 c/ V- [+ e- {" E. E718496 SIG_INTEGRITY SIGWAVE Frequency at smith chart.
0 D: q S2 m; p0 n721422 CONCEPT_HDL CHECKPLUS Checkplus fails if "\\" character is used in the parameter list
D; j4 t, M4 Z( y( J0 r721788 SCM OTHER SCM unresponsive while closing out a Block without Saving) h; ~) t9 w1 c6 z& Y7 V" l) n9 B
721801 CONCEPT_HDL CORE Save As crashes DE HDL if an existing page is selected in the design
( ?. v4 ]5 m9 r3 ?0 ~722653 F2B PACKAGERXL Packaging does not complete
" I3 x$ t6 ?/ x( u725285 CONCEPT_HDL CORE nconcepthdl does not work same as concepthdl for same script.
' E/ c0 C) \5 U B5 x' |3 _- Z# x+ H725719 CONCEPT_HDL CORE wire pettern of Publish PDF( C. {8 Q1 d- s$ a% S
727062 CONCEPT_HDL CREFER Custom properties not visible for TOC symbol in schref_1 view7 j5 ?6 P+ `7 b$ o2 |9 E
727194 CAPTURE CORRUPT_DESIGN Random Capture crash" U7 R' t- L. M1 s' V2 N9 f3 k O
727704 SCM PACKAGER ASA to PCB getting out of sync# r- k L6 k j Q2 C
728066 CAPTURE NETLIST_ALLEGRO Allegro PCB Edtior net cannot be generated if PACK_SHORT is used
2 j$ G7 j, |, s% Z729214 CONCEPT_HDL CORE SHOW_PNN_SIGNAME directive used with Windows Mode gives crash. i) L) J6 j0 I
730295 SIG_INTEGRITY OTHER Filled rectangle shapes not extracted properly9 E! J3 J6 ~6 s* E
731183 CIS QUERY_DATABASE CIS Query fails with ODBC Error for query (Price contains 29)* E9 h4 S. G: M4 f+ X( B l' l
732073 SIP_LAYOUT DXF_IF DXF_OUT generate an incorrect shape
) A7 f( h- c3 z5 G. @8 {; g732138 CONCEPT_HDL CORE Cannot change SI model assignments( u7 N$ j1 ~. Z2 i6 Y
732216 ADW DBEDITOR dbeditor crashes doing copy-as-new into lib folder that has partially completed chips.prt file# W+ \% v/ z. k+ S7 s) |
732249 SIG_INTEGRITY SIMULATION Probe sim with custom stimulus cause segmentation fault. Linux only.1 H9 G5 X; L$ V% c
732847 ALLEGRO_EDITOR DRC_CONSTR Manual Void uses Shape to Pin constraint to void Holes
% C9 R# Y6 z6 @/ z5 e- X1 X733261 FLOWS PROJMGR Project manager does not work with the Restricted User in client server environment, R- ] V" f# q$ i7 \* e
733773 CONCEPT_HDL OTHER Syntax issues in DEHDL; C: \3 ?( ^, U4 r1 \( m% O6 }
734260 APD COLOR Why subclasses still remain visible even after global visibility is turned off.
4 Q. g0 |' {$ `- A3 ?/ I+ ], K734419 CONCEPT_HDL CORE Concept crashes in windows mode when netname is deleted on schematics generated by ASA$ w( A' H/ `: C) c& l+ c3 r, J
734555 CONSTRAINT_MGR SCHEM_FTB Import Logic does not overwrite the Constraints
$ N @% i& s4 g; ~; w1 U735290 CONCEPT_HDL OTHER Concept's PDF Publisher has issues.
* G: d, |) j& A0 G: Y0 O735892 CONCEPT_HDL CORE "Component Modify" changes visiblilty of Key properties4 I' D3 |4 M, ]$ D+ d8 H$ J
735977 ALLEGRO_EDITOR MENTOR Mentor to Allegro translation fails without any error message
; |5 A/ Z' u; ~& [; b1 }736071 CONCEPT_HDL CORE Property visibility is not retained on the schematic instance when we modify the component on sch.
% f8 m- ^; Y5 ]' m# l736165 SIP_LAYOUT SCHEMATIC_FTB about error message of "schematic to layout"
5 n' ]$ v( |$ k3 C, r736167 CONCEPT_HDL CORE HDL crashes when I select BGA symbol in Component Browser, |' z1 w; [& M; l
736911 ALLEGRO_EDITOR SHAPE No DRC displayed when Place Bounds are edge to edge
- b9 z5 x8 T& \" C' C# x: n5 o/ \: u738035 ALLEGRO_EDITOR OTHER Measure function has different result between 15.7 and 16.2 version.
3 T$ E& H$ Q2 C, T! o5 ^738129 CONSTRAINT_MGR UI_FORMS Need Diffpair Constraints option in Analysis Modes Electrical Options with Performance license
K9 p+ n, U1 v/ n$ s; l738276 ALLEGRO_EDITOR PLACEMENT No feedback in console window when placing unfound components in Allgero 16.3# [- K" N1 K+ W$ a, Y7 m
738366 ALLEGRO_EDITOR GRAPHICS 3d viewer not showing some connectors with mutliple place bounds correctly
( A3 R& z% J! }, P( k8 X/ n) t738454 SIG_INTEGRITY FIELD_SOLVERS EMS2D extracts incorrect CPW to Trace spacing* i% I0 R5 j; q: Y! \* w3 C7 b
738578 ALLEGRO_EDITOR OTHER scriptmode +w doesnot work on Linux+ {% F1 B+ u/ j. B* R
738869 ALLEGRO_EDITOR OTHER Error msg when cds.lib contains missing SOFTINCLUDE a" X4 M7 J& }6 B, H( @
739116 EMI SIMULATION At EMI simulation on SigXP an extra Sigwave form is launched.
9 c! E: t w3 L3 E739225 ALLEGRO_EDITOR GRAPHICS Ability to lock the 'Hide Pallette' option
$ u8 s9 t0 n; S2 b) W: X739599 ALLEGRO_EDITOR DRC_CONSTR drc_errchk indic8 O, \; p3 h& S( A# F. J* F; C
739628 ALLEGRO_EDITOR SYMBOL Opening a symbol file is crashing allegro.% j7 r% u9 l5 `6 a5 J5 k
739653 ALLEGRO_EDITOR SHAPE Shape created in 15.X .dra changes geometry when uprev'd to 16.X
0 a2 r) V/ A" b/ p3 V$ K- ?739661 ALLEGRO_EDITOR OTHER Export netlist creates incorrect via_list syntax.; e, u* {% {8 ^2 k
739872 ALLEGRO_EDITOR SKILL Crash while performing axlExtractToFile in 16.3, U5 \, c! x0 C6 n( w0 \) D9 V
739934 SIG_INTEGRITY OTHER specctraquest crash on changing signal model! u e! G, u$ ~! P# T/ O
739937 MODEL_INTEGRIT PARSE zero valued estimated parasitics in ibis models' ~6 D$ x" Q" K8 l5 Y0 X
739942 ALLEGRO_EDITOR SHAPE zcopy xhatch shape creates oversize copy0 c1 X9 F- a3 }: i5 e* Y# s
740133 ALLEGRO_EDITOR DRC_CONSTR Same net DRC Update from Analysis Modes runs forever.
4 J7 b/ s, b d: ~9 a; m740281 ALLEGRO_EDITOR OTHER Jumper components where were placed in PCB disappeared
: }. ?4 r* K3 U% i. H9 P* u740309 SIP_LAYOUT DIE_EDITOR Moving a die pad in DIE EDITOR on G69A_U1 causes the die pads to rotate 90 degrees from the design.* ]$ c1 q2 o7 X8 O
740399 ALLEGRO_EDITOR COLOR Cannot automatically load custom color palette in 16.2+ L: a" p, s3 Z& D2 ~; c, s4 w
741210 ALLEGRO_EDITOR DATABASE Edit >Move; spin creates 'connect record not found' message8 f9 c8 M U3 N$ b: s* R" B, e, o
741307 ALLEGRO_EDITOR PADS_IN Shapes on some layers is not getting translated from PADS into Allegro
) @& q" q' S( g741313 ALLEGRO_EDITOR DRC_CONSTR Add connect slow in 16.3
# a0 S" c" C$ N0 _( x; l5 e* K$ h741778 ALLEGRO_EDITOR COLOR Color pallete in 16.3 is not expanding when maximize dialog8 h) B S$ M8 U0 T- h
741910 ALLEGRO_EDITOR PADS_IN unable to translate PADS ascii to brd
- K3 {" L! S, `! `741939 ALLEGRO_EDITOR PADS_IN PADS to Allegro Translation fails or hangs.% z8 [/ H' \0 r% Q2 L% i
741980 ALLEGRO_EDITOR PARTITION Import of parition does not import etch or vias.: A' O2 d) {' I$ C n
742676 ALLEGRO_EDITOR SKILL Tpoint cannot be moved by using skill.1 a& E2 Q8 C0 r: f; O+ R7 F
743161 ALLEGRO_EDITOR SCHEM_FTB Netrev crashing when importing netlist into board file.7 y8 b1 k! d* X3 x7 S5 e
743235 ALLEGRO_EDITOR PLACEMENT Allegro crashes when unmatching comp in placement replicate.
% N* r8 w) ~6 Z K0 W5 M9 @743243 CONSTRAINT_MGR TECHFILE Closing CM destroys tcf values when they are set to locked using fObjectNOTReadOnly4 E5 n4 F0 A( @* [; |
743301 SIP_LAYOUT DIE_EDITOR Edit die command creates two extra die pads
- T/ i3 ` r! L( L. U T743316 CONSTRAINT_MGR DATABASE With Allegro 16.3 Constraint manager takes to long to update5 ]$ _4 H# W8 W1 ~- [
743553 CONSTRAINT_MGR OTHER Net disappears if we cancel the line width edits in CM
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发表于 2012-1-11 21:45
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