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0 I9 |. t% }: D, m; H8 `% |DATE: 02-17-2012 HOTFIX VERSION: 016
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CCRID PRODUCT PRODUCTLEVEL2 TITLE% n; |# Y+ Y- _
===================================================================================================================================
4 [1 A% @" m% v840105 PCB_LIBRARIAN USABILITY PTF subtype is getting changed when Save As option is used in PDV1 e* g/ y* D& Y1 K4 l) C- g2 k
873075 PSPICE PROBE Decibel of FFT results are incorrect.
) D$ p9 \1 b/ s4 w& ~- S' ?: w938744 ADW COMPONENT_BROWSE Need ability to customize shopping cart columns to include any Part property
' `' L+ Q7 G X' d9 u943003 SCM REPORTS The dsreportgen command fails with network located project& T1 G9 E, e$ n. a8 c. d2 g$ u
961530 ALLEGRO_EDITOR INTERACTIV The problem of Display measure command, p7 Q5 F1 {- `( I$ t
962157 CONCEPT_HDL CORE Where is the setting for enabling the Enable PSpice Simulator menu?
o7 d* l& B6 e2 y& t962206 CONSTRAINT_MGR CONCEPT_HDL Import physical not passing all constraints from the board to frontend
+ g9 i3 L: k3 K0 x) p968205 PSPICE DEHDL_NETLISTER Change SPLIT_INST property to PSICE_SPLIT_INST for Quad Switch type of design.& K' g4 v) M/ B: k% D
968509 PCB_LIBRARIAN METADATA Incorrect pinlist.txt was generated if DIFF_PAIR_PINS_POS/NEG was set.
! \) J: p. V, v# ]969450 LAYOUT TRANSLATORS OrCAD Layout to Allegro Translator crashes
2 U8 e0 Z" o0 t* T Z969997 CONSTRAINT_MGR CONCEPT_HDL ERROR(SPCOPK-1053): Cannot find a ppt part that matches the instance pro~
1 ~, { S2 }* L6 I% n. S1 N971193 CONSTRAINT_MGR UI_FORMS Copy and pasting a formula causes the application to crash on windows., M# j# r% M/ {/ i3 V4 [# D; i
971601 CONSTRAINT_MGR CONCEPT_HDL ERROR(SPCOPK-1053) and WARNING(SPCODD-66) because of directory structure
8 \. }0 e, a3 Q; }$ M! y973398 CONCEPT_HDL OTHER It should be not packaged with error while working the packaging process if the design has a ERROR: o7 G g0 \1 d T9 u- }
973859 PSPICE ENCRYPTION Pspice crashes with encrypted model& E7 ~ L7 ~( ^3 S, H6 o
973938 PCB_LIBRARIAN VERIFICATION pc.db is missing
0 {# ?' f1 L ?3 S0 ~# W$ f4 C974540 CONCEPT_HDL CORE Graphics updates are real slow
" u+ l$ m& M) D974791 F2B DESIGNVARI Variants are not back-annotating to schematic and turning to ?
) ]) W1 j6 M0 b8 D974818 ALLEGRO_EDITOR NC Backdrilling produces 0 plunges yet no errors reported.
" G6 `' q6 k8 d8 k$ X" G974945 ALLEGRO_EDITOR SKILL Why is axlPolyOperation is giving different result and not working/ ~( S5 e6 x0 R1 k- s5 s, S
974946 MODEL_INTEGRIT TRANSLATION ibis2signoise returns the error - Delay measurement fixture must contain V for ECL technology# |+ L! m9 ?$ }; e. e
975396 CONCEPT_HDL CONSTRAINT_MGR Constraints are dropped after migrating from 16.3 to 16.59 N. s7 I$ V* G5 w% ]
975633 ALLEGRO_EDITOR GRAPHICS 'dynamic_layer_visibility' option in 3D Viewer when checked or unchecked should not change (until next change)
0 W: C2 Y( }" c# d975720 ALLEGRO_EDITOR DRAFTING Datum dimension lines not adjusting to text move/ i% s/ b# r1 F" A G9 B% l4 t
975745 ALLEGRO_EDITOR SKILL cdsServIpc different 16.2 vs 16.5 when Allegro exits
: `; R8 B ?9 Z* Q/ W& ^976013 CONCEPT_HDL INFRA Power pin connection of FPGA symbol is missing in netlist.8 C+ @1 ~4 W! S2 s
976058 CONCEPT_HDL COPY_PROJECT SCM Copy project does not create the con and dcf files in tbl_1 views% E1 U; V W2 [2 R& S: `
976073 CONCEPT_HDL COPY_PROJECT All the constraint data is lost in the SCM copied design& A( t2 S1 J1 n* D. N; l
976160 CONCEPT_HDL CREFER Cref fails due to some Caeviews error in the design
& G( F1 Q! h' j5 F& K: g976204 ALLEGRO_EDITOR DRC_CONSTR Application falsely reporting Mechanical Pin Antipad to Shape Spacing DRC
) b& A- W, ~- K# e0 o976448 F2B PACKAGERXL ERROR(SPCOPK-1069): Invalid POWER_GROUP property value
" ^/ O* Q( {, q, r3 p, ~: x2 E976521 ALLEGRO_EDITOR DRC_CONSTR multi-thread update DRC causes the application to crash
7 Y! y; d" m3 o5 V! Y( s; S3 u976838 SIG_INTEGRITY OTHER Unable to create XNET for highlighted nets on attached database even after assigning proper Signal Models.
: ], g' [3 Z9 E" t0 G! H! F9 G977517 F2B PACKAGERXL Export physical fails after update to 16.5 from 16.3
- n" @, e! d4 Y: t- A6 a) Z# }977902 ALLEGRO_EDITOR DATABASE generate module is crashing allegro* A# J2 ?1 W( W x; _
978652 ALLEGRO_EDITOR PADS_IN PADS_IN fails with ERROR: Finished with errors.
) r! ?8 i% \ Y. z4 G+ k978744 APD DEGASSING Some shapes will not DeGas on this design8 ~: \+ Q6 I0 X0 h7 p
979940 SIP_LAYOUT OTHER SiP Layout Leadframe autobonding with profile selection
7 \. w$ O# n( q* {! ^981699 CAPTURE HELP Start Page still shows Hotfix 14 after installing Hotfix 153 G5 ?# |2 y0 M1 \& t) _4 s
9 q8 f8 \' V4 Q3 G9 {
DATE: 02-03-2012 HOTFIX VERSION: 015
6 |" i9 Q# e: V5 I+ B) x===================================================================================================================================& N/ `* z. b" f- r! Y# O8 J* B0 Q
CCRID PRODUCT PRODUCTLEVEL2 TITLE6 }: Z) Y% ~" K9 X7 C, y$ O
===================================================================================================================================% Q2 b& X0 f0 C) X9 `/ O4 D
871567 CONSTRAINT_MGR SCHEM_FTB Ability to filter out Single Node Nets from Constraint Manager6 o$ a7 P' X% i: {
921436 ALLEGRO_EDITOR MANUFACT Change in 'decimal place' for new dimension changes the already placed dimension
* E Q! f9 ~$ u) J$ d941433 CONCEPT_HDL COPY_PROJECT 16.5 Copy Project should warn if trying to copy a 16.3 design
+ u! ~, Q; {8 E9 U2 L954375 ALLEGRO_EDITOR MANUFACT Change dimension accuracy for few instaces of associative dimensioning2 K6 M8 P- b# E7 G8 X
961646 PDN_ANALYSIS EMVIEWER EMViewer Help > About shows wrong version/ U3 j3 [; k! H0 A2 p! l6 F
964912 CONCEPT_HDL COPY_PROJECT ASA project crash after using copy project
- s; l0 _! V. w, W- ~967223 ALLEGRO_EDITOR MANUFACT Bug:Oval slots orientation in one direction only( v6 p1 [' z1 J
968865 SIP_LAYOUT DIE_ABSTRACT_IF load of die abstract fails due to differences between component and symbol- ~9 X$ J' B; `1 u% U3 N! G5 d
969485 ALLEGRO_EDITOR SHAPE Shape does not update correctly in 16.52 U' W$ t' u' ~
970331 CONSTRAINT_MGR ANALYSIS Impedance worksheet shows a zero value for impedance
; d" | K2 K6 X# D( z! l970600 SIP_LAYOUT SYMB_EDIT_APPMOD Option in Die Editor to be able to "physically swap" pins
( |, j1 J1 K- x8 J: G970910 F2B PACKAGERXL Our customer has problem with pin color after pxl 16.5.0 g# {1 [4 h e9 F8 h
970970 SPECCTRA FANOUT Fanout Vias is placed far away from decaps and does not change the Fanout length even when max_length is reduced.
|0 \+ v5 U' X- H8 b4 B970985 SIP_LAYOUT OTHER Importing a .spd2 database file using NA2 will cause the APD/SiP tool crash& |5 X2 e! k0 @7 v! S1 v
971757 CONCEPT_HDL INFRA Crash while Saving/Packaging the Design1 \" {; E# Z4 }+ ?" ~6 D- }
971923 ALLEGRO_EDITOR MANUFACT Allow to change decimal accuracy for dimension instances
0 x+ z5 ]; P. _+ L; A972568 CONSTRAINT_MGR UI_FORMS Tools >Excel missing from CM
5 z& s3 i3 _. C. S# m972821 CONSTRAINT_MGR CONCEPT_HDL connectivity server warning: Unable to add property WEIGHT
0 G$ A0 w* @ i P1 h973185 SCM CONSTRAINT_MGR ASA2 block not seeing all instances in a package.$ U( ?$ y) H0 S/ R' P
973211 ALLEGRO_EDITOR INTERFACES IDX Object Type Change not recognized; H5 I! e# A) b3 Z s2 j" Z
973214 ALLEGRO_EDITOR INTERFACES IDX import package keepout height value change assigns incorrect value3 F/ g& f1 Z9 W5 z4 O# S8 }
973384 CONCEPT_HDL CHECKPLUS The multiple SIG_NAME has to be occurred an ERROR at the SPB16.5.2 q1 M- f( B8 m7 d# h, s5 v. s
973514 SIG_INTEGRITY OTHER Mapping error when Ecset is updated to constraint manager from extracted net5 ^$ c, k, Q- e F$ h. w
973950 ALLEGRO_EDITOR SHAPE Update to smooth crashes application
- [ V9 D4 C B( f974533 SIP_LAYOUT OTHER Crashes in Edit > Die Properties and obviously has a setup problem.. ?0 i: V8 T3 L# U6 q$ B x) R
974809 ALLEGRO_EDITOR SKILL argument available for hiding a property with function axlDBCreatePropDictEntry is not working
& r$ P- X) j e1 M8 I976179 INSTALLATION ISR Installation of ISR S014 to 16.5 on windows is breaking the documentation index
& x; E" N: h7 P# Q6 G9 q& W7 ?. e8 M" L! J0 u. P
DATE: 01-20-2012 HOTFIX VERSION: 014) n! _0 N7 M# t6 y- l" K4 f* V
===================================================================================================================================7 P0 p5 l; E6 y2 `! P8 i
CCRID PRODUCT PRODUCTLEVEL2 TITLE
8 [) E5 N( x+ {+ i2 W# j; E/ h; r3 b===================================================================================================================================
. V m# G# o9 G5 x2 w733285 PSPICE SIMULATOR Enhancement:In server-client installation use existing index file from server6 a9 W' o& p8 n/ o8 S5 Z, R+ s3 D$ v
941020 SIP_LAYOUT OTHER Soldermask enhancement
+ N8 o- E. `- w l946407 CONSTRAINT_MGR TDD When is it safe to open a 16.5 design in 16.3?' Q* D7 v f! N- Q: x
953067 CONCEPT_HDL OTHER Variant Editor "Error/Warning messages" form is unusable
8 m# o+ b: z% Y1 e5 a$ Y! d954818 CONCEPT_HDL COMP_BROWSER Replace button turns to Add in component browser when a component replace is done on the schematic
& I" x$ {9 e0 f4 L* m956450 ALLEGRO_EDITOR DRC_CONSTR Analysis always shows analysis failed in uncoupled length in some diffpairs) I+ y) b. }- q3 r
958259 F2B DESIGNSYNC ds.exe crashes on a big design when accessing the design from network drive% k" J0 K; w- ~( ?7 M- l1 X
958395 ALLEGRO_EDITOR SHAPE shape voids won't merge
% z$ x" M, p* C% X959212 MODEL_INTEGRIT PARSE Attempting to use "Mark qualified" option on DML File results in dmlcheck and Modelsim wanrings.
) F# S; S$ x1 x1 I! n/ O' I- k959940 APD AUTOVOID Void all command gets result as no voids being generated.4 ~* A0 A/ W# s7 l' t2 B# w6 a
960252 PCB_LIBRARIAN CORE Splash screen in PDV prevents showing error message
6 s. P( m2 ~$ p; [961634 PDN_ANALYSIS EMVIEWER Cannot launch PDN EMViewer from withing PCB SI
/ B( b% Q2 z; W8 g+ X4 o* Q5 \2 I961645 PDN_ANALYSIS EMVIEWER Standalone EMViewer will crash when opening any result file in the form of *.emv file.
# X9 a) q7 n$ W- T4 Q; x8 q961700 ALLEGRO_EDITOR SHAPE dbdoctor reports ERROR(SPMHUT-144): Illegal arc specification
. n) b D( l9 T2 s* Q/ X- e961733 ALLEGRO_EDITOR SKILL Allegro crashes. Appears to have a memory leak.5 z; v' C7 S! H# W. t
961758 ALLEGRO_EDITOR DRC_CONSTR DFA check produces no DRC when the dfa bounds are not a rectangle.
" M, n9 }( n% x7 G. W+ f961887 CONCEPT_HDL CONSTRAINT_MGR Match Group created from ECSet cannot be deleted in the same session of CM! r- X+ t3 q: w0 ]( W% F6 v$ G
962552 APD EDIT_ETCH BUG:APD crashing when we try to slideget information but move works fine1 n5 c! }1 K( j: }+ ~
962869 CAPTURE STABILITY Capture crashes after RMB click on rotated parallel wires* D9 V' P4 j: c/ y! v. E
963232 CAPTURE MACRO Macros not being played in Windows7: }% A0 Z5 z5 Y
963300 ALLEGRO_EDITOR DATABASE Create > Module crashes in 16.5 but not in 16.3" [/ N" J0 S( V9 r
963651 CONSTRAINT_MGR CONCEPT_HDL ECsets are renamed after packaging on linux
5 b" x( D) e; K; w1 G963663 CONSTRAINT_MGR ANALYSIS Q- Why the customized worsheet for Diff pair Impedance not analysing at all for this SIP design5 B' M9 y9 i% A: x% i; e
963715 SIG_INTEGRITY OTHER Application only adds the bottom conductor thickness for the via z-axis length
4 Q' |- x5 D1 Q( n( m4 [& X964068 ALLEGRO_EDITOR INTERACTIV Allegro crash when using move alt sym mirror alt sym...
3 s* Z- V0 {" Q) b4 _9 e964267 CIS PART_MANAGER Capture become non-responsive, working on Part Manager and creating CIS BOM, for large designs
8 u9 W! L, `( F964597 ADW LRM Issue of LRM license checkout after renewal license by 16.5 (ADW15.5_S23+SPB16.3)
* |. L& Y3 y3 X4 j5 c1 {4 i966148 APD INTERFACES Character Limit for DIE Files (*.die) Import
4 p9 t% j4 ]& A1 }966416 F2B PACKAGERXL Cannot package this design b- O! L J# D* X; w
966421 CONCEPT_HDL CORE DEHDL Crash when applying property on components in duplicated blocks
* K+ |/ ^5 r& u% m t966693 CONCEPT_HDL CORE DEHDL crashes when doing model assignment if CM is open) y% K3 O. @8 g7 r! W
966795 ADW ROLLBACK rollback utility does not honor -product option from command line
; M. ]) O' W$ X8 F* d4 ~% q967089 SIG_INTEGRITY OTHER Matchgroups created by ECSet not deleted when ECset is removed from object.* d" q4 y" w3 f, i1 E
967222 ALLEGRO_EDITOR OTHER PDF export is leaving data off the drawing
% C7 R: @* j' k( A* A$ }/ _967240 SIP_LAYOUT WIREBOND Change default bond fingers selected on multi-site leads during "bond to leads" program
K( d' b1 m2 d' r1 V4 r' H' @967297 ALLEGRO_EDITOR OTHER Dynamic Fillet&Eliminate unused stacked vias cannot be used as the Miniaturization option.' P, Q& `* w& K d4 I
967576 CONCEPT_HDL CREFER Occurrence location property values do not appear in flattened schematic generated by CreferHDL) l* u# s P8 ^. c& m7 n& Q
968096 ALLEGRO_EDITOR DRC_CONSTR Mechanical Pin to conductor spacing is not followed.- U) u! B; d4 p7 A, i
968222 SIP_LAYOUT DIE_EDITOR die pin loses IC net for a co-design die with multiple ports within IO-cell! {9 |) `4 e6 ~8 Z8 K$ u$ C
968358 CIS PART_MANAGER Capture crash on removing a part from subgroup in part manager1 u2 @5 E. @6 r
969594 CONCEPT_HDL CORE The dcf file is not updated with schematic changes
7 K/ y: R' ~/ ~
" w* \, T( r% f. _& x% J5 P& U; iDATE: 12-16-2011 HOTFIX VERSION: 013- ?1 \" w9 r1 p* @
===================================================================================================================================
9 L! [& W; Q4 }( ~4 |- ICCRID PRODUCT PRODUCTLEVEL2 TITLE
2 L& I. @! s2 t1 f" v9 Q& `===================================================================================================================================
_" M) b. f5 O% n* b875695 SIG_EXPLORER INTERACTIV Enforce Causality check box doesn't work.
- V! C' a% e; ?5 q$ ^8 N4 m) |$ e927148 CAPTURE PROJECT_MANAGER Capture crashes on creating scehmatic folder with name which already exists in design9 k4 t9 u+ M* N
938013 CAPTURE NETLIST_OTHER The netlist in RINF Format contained two identical lines for PCB FOOTPRINT) M9 E5 V2 h0 e- g O7 u/ \
941409 PSPICE PROBE BUG : Search accuracy wrong in new cursor window
- ~% A* v* {* P6 a945242 SIG_INTEGRITY SIMULATION Unable to select "shapes" in find filter for 'show parasitic ' command: i; D- r- a" K
946293 CONCEPT_HDL ARCHIVER Archiver hangs if there is a whitespace at the end of the path of cref.dat) V- Z4 s6 I" J: m. o; A* y- S# Y
946770 CONCEPT_HDL CORE 揤iew Design� function is missing in Windows Mode after reseting the menus.
4 S0 V& {. O' q950994 CAPTURE NETGROUPS Problem in expanding the netgroup in Auto Connect to Bus function
+ c9 i( C+ e: J! I" T953530 SIG_INTEGRITY GEOMETRY_EXTRACT Display Parasitics is displaying wrong results for EMS2D Field Solver compared to topology extraction using Probe.
2 l) n+ n3 ~* \7 L& J953713 CONCEPT_HDL PAGE_MGMT Random page replacement/duplication in block: d) P# G/ o7 y! q2 m& D6 ?2 H F
953917 CONCEPT_HDL ARCHIVER archcore should handle errors correctly
5 v' w3 O. v9 s953971 ALLEGRO_EDITOR MANUFACT NC Drill files not generated correctly when using the option "搒eparate files for plated/nonplatedholes�& d* a9 o" S8 S n; b
954400 CAPTURE NETGROUPS BUS members of NetGroup are getting converted to Scalars in Export-Import NetGroup.
( C0 d0 F; H+ Z1 _954498 SCM B2F SCM crashes when importing physical
4 n5 I- C9 @& y( d e954623 ALLEGRO_EDITOR EDIT_ETCH Unable to complete connection with Add Connect - related to soldermask to cline check?
; k8 y0 G' d! O( R3 \; }954894 ALLEGRO_EDITOR MANUFACT Dimensions disappear when opening database in v16.5 from v16.32 Q- w' y$ j4 ^) {. X' \7 H
955029 CONCEPT_HDL CORE custom text font size not recognized in symbol view' h+ @* C- ]7 W, O
955133 SIG_INTEGRITY FIELD_SOLVERS The Field solver creates the differential trace model which is reversed T(D1) and T(D2) of bottom side.
& A# [( [) Q/ Q1 ^' Z, j: i955290 CAPTURE DRC Description for UPD0014 missing in the Browse DRC markers window
+ L6 N2 ?8 I+ g5 Q- n5 X7 S955299 ALLEGRO_EDITOR DRC_CONSTR drc text to smd pin does not work any more on this database in 16.3 S039* V; x1 k* z# f1 @" w2 @
955338 CONCEPT_HDL CHECKPLUS Need to change PART_NAME
9 z* ^3 w; N! M' b0 G1 k955447 SIG_EXPLORER OTHER Model path set in DE HDL Model Assignment not used by SigXP from CM in DE HDL
1 L! v2 H& R# \" @# A! `955740 SIG_INTEGRITY GEOMETRY_EXTRACT Crosstalk with Timing Windows does not work correctly
; d% ]8 }8 i0 [8 D. B8 G955749 ALLEGRO_EDITOR MANUFACT show element Info shows symbol dimensions on incorrect subclass8 S5 G* Y+ D- t6 i3 s9 r; w( I6 l
955912 ALLEGRO_EDITOR OTHER Shapes with voids that are exported to PDF have gray filled area over the void. ^( `+ V& H- x; v9 {0 N
956129 CONCEPT_HDL INFRA DEHDL uprev hierachical design from 16.2 to 16.5 packaging failure.
6 s8 s+ x* i( f& w956373 ALLEGRO_EDITOR NC drawing name doesn't display in the log file
o* y! i7 M! ]6 T& }0 a956393 CAPTURE PROJECT_MANAGER "GENERAL" and "TYPE" tabs are missing from " roperties" dialogue box.
+ ^7 @! \( ~; [9 N956448 PSPICE MODELEDITOR Can not generate a DEHDL symbol from Model Editor, because no Capture license found( e, I' s* f2 q! g
956456 CAPTURE NETLIST_OTHER OrTelesis netlist not transferring user properties defined under combined
% V9 Q0 e. S7 v" s956489 ALLEGRO_EDITOR MANUFACT dimensions lost when symbol with diemnsions attached to symbol origin placed on board% }* z; O/ f! n/ b4 x9 a" |9 F
956603 CONCEPT_HDL OTHER Part Manager "has stopped working" after changing a component' Q; t* [& k- L1 i* u% K
956751 ALLEGRO_EDITOR ARTWORK Import Gerber command does not work correctly
3 r f* [1 ^3 Y, X# ?956847 PCB_LIBRARIAN METADATA PDV - Partdeveloper symbol to function linkage broken/changed in 16.5
, |+ C5 t! q! J) D+ z956987 CAPTURE OTHER Find from "Search toolbar" doesn't gives complete results) I* L7 ~* t+ a/ X4 j* S8 O
956996 CONCEPT_HDL INFRA Correction to ERROR(SPCODD-7): Following Primitive instance causes CM to empty' C* E9 W7 h6 N/ J9 G# ^
957009 CAPTURE NETLIST_OTHER Problem getting database property in Mentor PADS PCB netlist
m8 ]! c! D' d8 R' @; n6 Z* [957137 APD DXF_IF DXF out command dose not work correctly.1 r' |5 C4 l- a+ a
957167 APD GRAPHICS Highlighting for Static shape with display_nohilitefont environment variable.
3 c; h7 y8 u. r w. }4 K) d6 J957232 SIG_INTEGRITY OTHER Allegro crash during Model Assignment.4 z6 A2 }8 v! i. S K d
957267 CONCEPT_HDL INFRA Packager Error after Import Design
1 T; Z& E h! k% E957866 SIP_LAYOUT DATABASE Cavity outline is not getting deleted from symbol file
% ?$ }, Z* e- H+ z* O ^958010 ALLEGRO_EDITOR REPORTS Wants the ability to extract "Batch" reports from Partition ".dpf" files.- H& D( w7 j# b/ S: v1 A4 b7 ~. X
958252 ALLEGRO_EDITOR TESTPREP Resequence testprep with the option - Delete probes too close crashes the design3 X. h0 l9 [# f" V
958253 ALLEGRO_EDITOR REPORTS Shape did not have thermal relief connected to pin but unrouted nets still shows zero.
4 {; O7 a" W$ |" k958433 ALLEGRO_EDITOR DRC_CONSTR False embedded component DRCs
' X/ u( I: P" c$ H958753 ALLEGRO_EDITOR SHAPE Dynamic shape is getting corrupted in 16.51 R6 E5 H4 L4 b; k
959011 ALLEGRO_EDITOR OTHER copy problem of via and cline
3 d! _" }- n# O# ` T0 }959101 ALLEGRO_EDITOR EXTRACT Using extracta with excluding Thermal reliefs
: _9 H9 w! ` w+ O: B, M959253 CONCEPT_HDL INFRA Design will not open! W/ _1 C6 ^1 J0 f& u! z5 S
959299 APD MODULES Getting ERROR(SPMHDB-279) when trying to update modules placed on the Top side
# _* p/ p; n: a9 _7 N# B959884 CONCEPT_HDL INFRA Design Uprev/concept2cm crashes with Application Error/Out of Memory Error.
/ d' c6 O. E) ?4 [; }4 x+ m959909 ALLEGRO_EDITOR SCHEM_FTB Site level propflow.txt file is ignored property is transferred) [, z5 i4 d0 S9 M, a/ T1 ?3 {2 x
960067 SIP_LAYOUT PLATING_BAR Creation of plating bar removes "NODRC_ETCH_OUTSIDE_KEEPIN" property from the clines.
6 m) Y4 E% U; t) g8 O0 ~960126 SIG_EXPLORER EXTRACTTOP Allegro PCB SI license is used automatically at Topology Extraction of Allegro Physical Viewer.$ b. W1 d5 ?" H3 Y O: r4 Z
960143 SIG_INTEGRITY GEOMETRY_EXTRACT Running simulation in Bus sim happened crash while enable Coulpled Via model to S parameter
3 a) K6 m3 s+ w N- G& h* Y! N* p961349 CONCEPT_HDL HDLDIRECT Motorola designs have broken connectivity compared to 16.3+ L, i6 ]/ ] K% A3 A) n5 G
961816 ALLEGRO_EDITOR INTERFACES Normal Export > DXF fails and offsets the pins of the BGA symbol1 q& l$ b2 }% h1 `8 J
962519 SIP_LAYOUT WIREBOND Align option doesn't work for wb_tackpoint fingers# Y& @- n! m* f3 E% M
( |5 t' m4 s3 H7 FDATE: 11-30-2011 HOTFIX VERSION: 012! u1 k$ K ]( w9 U% E# n1 r
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E3 D d6 u* b8 E G===================================================================================================================================
8 h: _/ n& [6 [; Y+ _8 ~959581 CAPTURE NETLIST_OTHER PCB Footprint is getting replaced by VALUE in OTHER netlist formats( z3 }% R$ y r2 j- H
) S+ k9 B$ [3 eDATE: 11-18-2011 HOTFIX VERSION: 011
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1 x, A7 y+ t) P2 @# i7 D735439 PCB_LIBRARIAN CORE PDV Moving line-dot pinshapes by arrow keys breaks the pinshape! I' _: R9 M' Z; c$ F! S" Y
894815 CONCEPT_HDL COMP_BROWSER Why does genlibmetadata command give 'Aborted $PROG' Message?- @. [# _" y/ K& E5 [
903073 ADW COMPONENT_BROWSE datasheetl_url directive should support a display string for URL
: j; I& n% h3 [$ w6 [909919 CONCEPT_HDL OTHER Why is the PublishPDF UNIX command line looking for "true" script?
1 r2 _/ j1 L; R, C! [1 J* X911561 CAPTURE CORRUPT_DESIGN Capture crashes on trying to save the design.
& s7 L5 w1 k ~* W6 x0 O919579 CAPTURE PRINT/PLOT/OUTPU Print mode be selected based on schematic mode/ ?; f! F. B: y+ Y2 G/ u6 `3 q2 P
921247 CONCEPT_HDL COMP_BROWSER genlibmetadata.bat file does not have err defined! A$ k7 K: L1 c4 S r8 l3 f G' s
925182 CAPTURE PROJECT_MANAGER ENH: Feature to run update cache on all the parts in design cache at once.
, j% S6 w2 o2 N. k0 N926858 CONCEPT_HDL CORE Usability- Modify Component dialog forces user to do 'Reset Filters' to see other ppt rows% d. l0 O) T8 e! _; Y; k9 Z
927657 CAPTURE NETGROUPS Enhancement: Placement of netgroup definitions under design cache list8 B, R- c ^' B( ?- S3 d3 z% }
934684 ALLEGRO_EDITOR MANUFACT The relation between the linear dimension and the symbol breaks., a/ J* P. o6 p# l/ k: g
935836 SCM SCHGEN ASA crashes when generating Flat Document Schematic$ G, K) N: @: l- F T
937165 SCM SCHGEN Can't generate Schematic; B1 E d: }2 X7 w7 C
937292 CAPTURE GENERAL Memory usage keeps on growing and finally gets exhausted while search
# |2 p/ T- Y D5 {8 e4 z937322 CONCEPT_HDL CORE Master.tag file alters the sequence of the files and Genview fails5 B. N: A4 Y' q( o1 t; P1 @9 C
939135 CONCEPT_HDL CORE Unable to uprev a 16.3 Design to 16.5 with DEHDL-L License
- |5 n9 L) a% r1 t' y: T940373 CAPTURE TCL_INTERFACE Enhancement: TCL command to add nets to Netgroup; B9 i& n! W( Z8 q& J: z
940547 TDA CORE ERROR(SPDWSD-69): highspeed cannot be checked in! K1 E# r- x; [9 A
940607 SIG_EXPLORER OTHER Inconsistancy in License usage for opening sigxp -orcad
1 b' u% t- n [% [! ?+ q* X940790 F2B PACKAGERXL User doesn't want to display pin numbers after Export Physical 16.5.9 j2 H) U1 o( E
940944 SIG_EXPLORER OTHER Inconsistant license usage while opening Orcad PCB SI using allegro -sq -orcad and allegro -sq" @; r4 c& }9 I2 V$ p' _8 b
941354 CAPTURE NETGROUPS Enhancement: Option to rename the unnamed NetGroups* b, B+ c6 t0 E
941455 ALLEGRO_EDITOR MANUFACT The Dimensioned mechanical symbol when placed in the board does not show all the dimensions.& w: ]) d* N* k6 V3 |4 E# a. L
941863 ALLEGRO_EDITOR EDIT_ETCH Different behavior of design in v16_3 & v16_5 when add connect is executed on a segment thru script
% m7 N5 R: y6 U941881 CONCEPT_HDL COMP_BROWSER How can I suppress the dialog from universalbrowser -genlibindex?, ^7 h* H+ Q3 Z5 Q. @; o6 J
942474 CAPTURE NETGROUPS NetGroup member type of last added member must be remembered by Capture
2 ?% ~% N& U8 {$ j942522 CAPTURE GEN_BOM Export in excel check mark doesn't invoked BOM in Excel
# V( V( ^* K' O6 N, z8 C& \# G942557 PCB_LIBRARIAN EXPORT_OTHER PDV Export to Capture crash% q6 {! U6 j2 ~# @; c
942569 ALLEGRO_EDITOR MANUFACT Dimension move and change text deletes leaderless balloon/ U" [* F+ a. o& V% z* k
942573 ALLEGRO_EDITOR MANUFACT Balloon type parameter has no effect on leaderless balloon.. J# }! R p' g9 v0 S+ v6 E7 j* u
942613 CONCEPT_HDL CORE Genview supports only SCHEMATIC/SYMBOL/VERILOG/VHDL views as input type. .xcon not recongnised+ ?1 d9 H5 R: ]2 R. o. d4 Y9 j- i
943032 SCM OTHER ASA is not passing the correct reuse_module name to Allegro PCB layout.( }5 r3 j5 N/ N# _/ x/ D3 e
943401 CAPTURE NETGROUPS Alphabetical ordering of NetGroups in Place NetGroup8 I, l, Y4 ^' b& b S* k) L
944006 ALLEGRO_EDITOR EDIT_ETCH Vias added to shapes behave differently4 f7 I3 O% j0 C( @! P* g
944367 CONCEPT_HDL OTHER Too late to do Model Assingment in conceptHDL 16.5
! m' z% z% Q: R5 e. {2 @944788 ALLEGRO_EDITOR GRAPHICS Oblong Pad shows unexpected lines
: M/ w; L$ K( T2 c/ O945221 CONSTRAINT_MGR RETAIN_CNS CM Conflict Resolution fails on more complex designs using ECSets and constraints
|' b- G& L% y946270 ALLEGRO_EDITOR PLACEMENT The Rotation Type was changed to "Absoute" if the "iangle 90" use at placementedit mode of spb16.5
# v. T) i% Y6 U% q2 o' X946350 F2B DESIGNVARI Variant Editor rename function removes all components
\ v; _( ~' h. r4 p) \946380 F2B DESIGNVARI Some VARIANTX properties are hard some soft - why?
3 i7 S: @% T& Y7 d' [/ Q I3 U946419 SIG_INTEGRITY SIMULATION Cannot select component on BoardModel for controller in bus setup form# D# @* e F, s3 B& A' |- B0 @; V
946458 SCM SCHGEN Schematic generator adding an unnecessary page
/ V4 c$ m' P& b6 _0 C' c) L947667 ALLEGRO_EDITOR PADS_IN Need support for PADS-POWERPCB-V9.3-BASIC' `" o" {6 w3 O' M
947789 ALLEGRO_EDITOR MENTOR mbs2brd crashes during translation on the attached design.% x, r- V2 s1 ?. `" t
948110 CONCEPT_HDL CONSTRAINT_MGR Concept HDL craches when opening SigXP from CM1 F; V: \% I5 G3 c( F+ t, C
950970 ALLEGRO_EDITOR MANUFACT Unable to generate artwork, dbdoctor fails to fix errors.! G$ J7 i, Q/ u4 V: k4 U% ?" b
951901 ALLEGRO_EDITOR EDIT_ETCH In 16.5 add connect to same net is shoved6 n5 e) `; N* R" g
951919 ALLEGRO_EDITOR OTHER Exported package symbol soldermask and pastemask padstack locations not the same as original
; [) `+ g( R8 S8 |951926 CONSTRAINT_MGR OTHER What is MaestroNotifyNotSetReport.txt file?1 c$ N; V+ V* a+ |* ^
951939 F2B PACKAGERXL Uprev to 16.5 is changing refdes for some pages5 n. a K7 B% M% U/ y9 g3 W
951983 CONCEPT_HDL INFRA Problems converting an Allegro design from 16.3 to 16.5
. T& q+ Z( B8 q: W" _1 L952057 SCM PACKAGER Export Physical does not works correctly from SCM' T/ F6 @: z7 `: j; U5 \6 k& J
952217 ALLEGRO_EDITOR GRAPHICS crash when opening 3d viewer in PCB Editor( H" x8 Y ?5 w) \/ ]& _+ I1 p
952634 CONCEPT_HDL CHECKPLUS Checkplus logical rule fails on a design which packages fine in 16.52 @+ h5 D* W5 G3 W( ]* p n
953018 APD REPORTS Shape affects Package Report result.
. b% A" E1 e3 B R953337 ALLEGRO_EDITOR OTHER Allow netname and padstack names to be visible for testpoint vias when viewed in Allegro PDF Publisher.& v, d, z4 y3 J0 R, D2 d
953827 ALLEGRO_EDITOR EDIT_ETCH Snake Breakout function crashed Allegro' m( b# Q1 t2 D8 L$ H! e
953918 GRE CORE GRE cannot route second and third row of pad in die symbol.
2 w% ^. ~1 B: w% b954055 CONCEPT_HDL CREFER Crefer fails with UNC install path: Q* G; E* M2 c4 j( ?4 l8 i) G& {
954920 SIG_INTEGRITY CIRCUIT_BUILDER Each neighbor crosstalk simulation crashes or returns blank report
* \- J) j, T4 A# {# W5 \( z! ~$ m
9 m% T8 Z! |. KDATE: 11-7-2011 HOTFIX VERSION: 010
9 v; K8 ?/ ?: \( M===================================================================================================================================
7 i; H0 N) p3 @2 {CCRID PRODUCT PRODUCTLEVEL2 TITLE
5 P1 n7 ^- E7 i=================================================================================================================================== C! x* ?% ?# c# @1 Z
658866 ALLEGRO_EDITOR EDIT_ETCH enhancement option - so that Sliding a via inside a pad does not create a cline
" C1 ?; g$ R+ R1 V, S! R" I928624 ALLEGRO_EDITOR GRAPHICS Layer visibility control for 3D Viewer5 n: B* m2 D8 K5 y! Q* M0 a9 w
934991 SPECCTRA LICENSING Specctra_adv option is not working correctly for PA3100 plus PS3500 license in v16.5 tiering profile
5 q4 L$ r5 V& T- w8 A0 B938073 ALLEGRO_EDITOR PLOTTING Plot Page size A0 and A1 with problem
3 w' z q9 @, J) s938128 ALLEGRO_EDITOR DRC_CONSTR DRC changes when do update DRC.
+ ?' P# Z, g/ g( @" |, f938648 ALLEGRO_EDITOR GRAPHICS Enh - Requesting a way such that Package keepout appears transparent in 3D Viewer
6 I( M& G" y9 a4 c0 I, s/ d940518 SIP_LAYOUT SYMB_EDIT_APPMOD Swap pins command doesn't complete" K" q3 V* z1 \. w' |2 m
941426 CONCEPT_HDL COPY_PROJECT Copy Project fails - Updating opf view This can't happen!
% W- b5 o$ _6 n# ^: Z, u0 @941499 ALLEGRO_EDITOR DRAFTING BUG imit Tolerance isnot working for Dimensioning$ M) S4 Z0 D5 ^. w2 P, R
941814 CONCEPT_HDL CREFER CreferHDL crashes during ScheGen
' n! G0 p* b$ X( P942914 SIG_INTEGRITY OTHER ZAxis delay calculation" O$ `+ B5 E' f$ _# N1 Z! `
943053 ALLEGRO_EDITOR SHAPE Modifying the Board Outline shape will cause the tool to crash
0 o# {+ Y+ |& f: \945321 SIP_LAYOUT EXPORT_DATA generation of a xml file from cdnsip for shrunken die2 I% A7 U8 `, h0 K1 e8 H' x( N
945350 ALLEGRO_EDITOR SHAPE iPick does not work on shape boundary edit.$ j2 @. T7 @! w( [! {0 G, P
945449 APD SKILL When they create a new menu entry with skill APD crashes with next menu selection.# }& @) u0 x' f1 Z
946390 ALLEGRO_EDITOR DRAFTING refresh_symbol crash when trying to refresh mech sym that has dimensions
/ S. }/ {3 R; n+ K# ]; s0 O946401 APD EXPORT_DATA stream out gdsII results in shorting of PWR/GND nets due to elongated etch
9 n* U* @/ ^) _2 d" G7 D946819 SIP_LAYOUT DEGASSING Shape degass command$ Z8 y6 c7 l" j" ?- J, \5 V0 C# z
946869 ALLEGRO_EDITOR OTHER Allegro PDF arc representation needs cleaned up
6 q5 Y% B+ S# L3 Q G6 ]% I947230 ALLEGRO_EDITOR SKILL Skill execution crash Allegro 16.5 but work correctly with Allegro 16.3
3 F4 z2 h4 D$ l2 z6 {: _947603 ALLEGRO_EDITOR OTHER Component Properties (Default or User Defined) not transferred to PDF file
, z8 I+ i$ p9 k4 B0 `; Q) }1 [950995 SIG_INTEGRITY OTHER Netrev fatal error when importing logic
; x5 S" J$ C9 b* F( w951123 ALLEGRO_EDITOR INTERFACES IPC fails to output drill hole info in columns 33-37
9 C# `' f$ u; d* \: t& i951557 CONCEPT_HDL CORE Cannot create the entity folder for old plumbing symbol3 v1 ] z! `* D+ k/ X
1 [* u7 s) y$ {4 e0 gDATE: 10-26-2011 HOTFIX VERSION: 009
4 [" `4 t; A, |$ v$ [4 k===================================================================================================================================
4 ~1 t2 V' j4 w0 _3 |+ TCCRID PRODUCT PRODUCTLEVEL2 TITLE' P9 F. Q! l S& ?2 m) B( [2 a
===================================================================================================================================
. |$ c+ l+ P+ m7 n945788 CONCEPT_HDL CORE Some component properties on the parts are incorrectly changed after Import Sheet" o1 d+ j& _- ]8 }: t; L. F) F
945789 ADW LRM Some component instances are not updated by LRM even though cache ptf is updated from reference. R% H- h& c% c3 A: z
* E$ n! F, g+ m. U2 s4 V1 D8 A
DATE: 10-21-2011 HOTFIX VERSION: 008" e: |! i( s2 d# E$ r3 b
===================================================================================================================================; g9 w* G& _3 n* t* n
CCRID PRODUCT PRODUCTLEVEL2 TITLE- t3 n7 G& A5 T9 B/ q
===================================================================================================================================
" i- I6 n# B* w' h; ]4 _( b1 s/ Q/ s906827 ALLEGRO_EDITOR DATABASE Logic > Parts logic does not work correctly.
' @: p [% j% Y& n, a; b: C923346 CONCEPT_HDL CORE Not able to move the reference designators inside hierarchal blocks after uprev to 16.5
# \; m& ?8 F3 h; E% h; [926347 ADW COMPONENT_BROWSE Usability- Libflow Part check in comment should end up in Comments attribute for UCB/Designer to see it0 U8 P3 K1 C O, `9 c
929348 F2B BOM Warning 007: Invalid output file path name/ f" i' \: p1 E$ p
929777 CONCEPT_HDL OTHER Component Revision Manager gives internal error2 @$ L) l. P2 ~: l# a" s/ E
930783 CONCEPT_HDL CORE Painting with groups with default colors8 E1 e1 p9 P% ?9 U, R3 k
936748 ALLEGRO_EDITOR INTERACTIV "Unplace Component" menu inconsistent between General Edit and Placement Edit Mode.
' N4 i# g1 ~- Q. d938143 ALLEGRO_EDITOR CREATE_SYM Why is this Extra Property 'ECSET_MAPPING_ERROR7 }+ r9 q7 H5 W& p% I7 P; S
938281 SIP_RF OTHER export_chips creating bad data when symbol is split and contains V- V+ pins4 t5 a1 {' G: d2 ?: F
938812 ALLEGRO_EDITOR SYMBOL Cannot create a BSM with this DRA, errors out but does not state a reason.# V& w) s" K& }3 m$ {
939075 CAPTURE TCL_INTERFACE Texts are getting garbled in command window4 O+ ?! z0 {6 N
939193 F2B PACKAGERXL ERROR(SPCODD-439): Connectivity server is unable to load the design.. [: \2 H) z$ M7 B# S
939199 CONCEPT_HDL DOC "Retain electrical constraint on net" mismatch between schematic (YES) and design (NO)
- d6 ~$ F2 L8 k3 G/ Q939346 ALLEGRO_EDITOR SHAPE Shape disappears when updating with variable shape_rki_autoclip set.
F+ I% P e. d# n# ^$ h B939901 CONCEPT_HDL INFRA NET_SPACING_TYPE shows �?� on lower hierarchy level nets after Upreving to 16.5 version.+ z4 K: B8 \$ e. f- n) Q
939918 PSPICE PROBE Print > Preview for output file causes Pspice crash.2 w5 z; z6 ^5 i& Z. m. Q
940217 CONCEPT_HDL COMP_BROWSER UCB reports 'No Symbol found for the part'. w' Q4 Y% b U1 K6 l
940835 CONCEPT_HDL INFRA Desing package different after uprev to 16.5 where comp instance propeties are lost lost
9 U- \- t l9 D: f941125 ALLEGRO_EDITOR DATABASE Performance advisor doesn't skip non plated slot padstacks5 e( V" z% T6 L3 L/ d3 M* ^
941876 SIG_INTEGRITY OTHER Illegal model name cause pxl fail in 16.3% X C2 [0 ^- Z7 Y# X4 L
942210 SCM OTHER Is the Project File argument is being correctly passed?% j0 h: N2 P, S, c+ o
942274 CAPTURE PROJECT_MANAGER Crash on renaming a Design Cache part in Project Manage after doing replace cache% N( A; G, \" `' V
942839 ALLEGRO_EDITOR GRAPHICS Graphics Issue- Pads are not visible
) Y! j! i) B" H943055 ALLEGRO_EDITOR SKILL axlDBCreatePropDictEntry causes application to crash% `( r: m, @5 e* Y6 w( i
$ V1 y% ~, x, y; b/ fDATE: 10-21-2011 HOTFIX VERSION: 007
* o& \/ r( X f9 r4 \===================================================================================================================================
$ S3 D% z, J; _; FCCRID PRODUCT PRODUCTLEVEL2 TITLE
8 K. l$ Y( @* S0 L7 d5 [# I===================================================================================================================================: r1 x, y0 m- H0 B; ^
841096 APD WIREBOND Function required which to check wire not in die pad center., w3 U1 p/ Y; N, ^0 n! Q
903263 CAPTURE SCHEMATIC_EDITOR ENH: Selecting parent netgroup must select the underlying netgroup bits.
( v! b9 {" U$ `3 |4 Z1 }' ]* ]906692 ADW LRM LRM window is always in front when opening a project
2 a. O" H: R/ p9 u912942 APD WIREBOND constraint driven wire bonding
8 P0 A& C7 t0 F: I, c/ X912951 CONCEPT_HDL CONSTRAINT_MGR Need to manage temporary files on Linux systems
& M" H% Z0 H0 ~! V+ P/ ]915178 SIP_LAYOUT DIE_STACK_EDITOR Die Pad names changing when updating Die in a design3 i- Y' v. S. g
917887 PCB_LIBRARIAN VERIFICATION Part should not be released if the alt_symbols has errors
0 @! e& _# s* j; x; A" ]! C923315 SIG_INTEGRITY GEOMETRY_EXTRACT crosstalk simulation fails with TMP popup failure
, K1 M7 L0 c, j' x4 q# D927382 CONCEPT_HDL CHECKPLUS 'Verify Symbol' forces the use of 'Concept_HDL_Studio' license
) S, N1 A/ Y4 A4 O927664 CONCEPT_HDL CONSTRAINT_MGR Internal Error disposeipsp/ r" @+ k8 _' L! C) j$ x' c9 P
930152 CAPTURE NETGROUPS Scalar net names when being connected to net group overlap when connections are made one by one
: j7 N. e# n* T2 b6 f930180 CIS LINK_DATABASE_PA Visible property position on schematic get reset on "link database part" operation8 r1 f* ~+ G. g; R8 |0 B
930188 CAPTURE DATABASE Capture 16.5 crashes in being re-invoked.
1 C8 G+ W8 y# I- {# ^930541 CAPTURE NETGROUPS NETGROUP element renaming doesn' renames the associated net ?
# {; P: L% ? q. j9 j; F b7 |930866 PDN_ANALYSIS SETUP OrCAD PCB SI Session crashes when we open PDN Analysis with "OrCAD PCB SI" license.
# j: r7 c2 d& [& J- K5 i930926 ALLEGRO_EDITOR GRAPHICS Via and Holes not visible eventhough set to Visible in Color form/ |2 z7 |' R$ B. F4 a# U8 `
931274 ALLEGRO_EDITOR DRC_CONSTR Negative Plane Islands waived DRCs reappear after performing update DRC.
" d/ w% I( x& v932091 CONCEPT_HDL CORE Prop attached to SIG_NAME property2 [1 R0 Z$ H! ^7 D8 {% \! k( a
932255 ALLEGRO_EDITOR GRAPHICS Change in Zoom level makes arc segment to disappear
6 M! Q8 X: E4 o$ Y7 g932292 ADW LRM LRM crashes during Update operation on a customer design
9 N5 ]2 C z8 Y4 _932639 SIG_INTEGRITY OTHER Add Connect command hangs for about 14 seconds and then returns.6 x5 M) [1 `9 x/ A3 V3 z. b
932704 APD DEGASSING Shape > Degass never finishes on large GND plane
( d! p' h1 s" `. J4 a6 F: H932871 APD GRAPHICS could not see cursor as infinite
6 t+ A# S( k1 I5 f2 A% s932882 CAPTURE SCHEMATIC_EDITOR Capture crash with FIND command - ISR050 K) a! O+ g+ s9 S! V& A! }
932969 CONCEPT_HDL CORE ConceptHDL crashes when you save the design in 165 > hotfix #05# f9 n% Z9 t; ?2 u! o
933024 CAPTURE NETGROUPS Naming restrictions for NetGroup members) R! h3 N5 k( q8 T
933145 F2B PACKAGERXL Add Subdesign list is truncated in Force SubDesign Design Name pulldown
4 M3 Z9 n3 @; U: f$ `933214 APD ARTWORK Film area report is larger when fillets are removed3 p) O+ y- M, b8 e$ u n
933356 CONCEPT_HDL CORE Net prop display size become 0 if it was attached to SIG_NAME prop.) V+ S/ x- r) i( ~7 q. N
933532 ALLEGRO_EDITOR COLOR Bad color assign and initialisation during creation of new subclass% E& U% O7 u! {* K* @/ E a# T# H
933549 ALLEGRO_EDITOR OTHER Chart text missing in export PDF file.
( `+ N1 t5 b \# k! D9 \934008 ALLEGRO_EDITOR REFRESH refresh symbol updates symbol text to some unexpected values7 S( G. @% Q& c+ q
934031 ALLEGRO_EDITOR DRC_CONSTR Bug : Update DRC removes Waived status for some DRCs8 l, i7 k0 w9 `4 f8 \$ L, q
934087 CONCEPT_HDL CORE Opening DEHDL and Model Assignment before design loads causes crash) m9 z. W7 f p( Q: {0 S3 Y. F. n. B
934396 CAPTURE SCHEMATIC_EDITOR Find operation is not searching power symbols with + or - signs.0 Q P5 Q) E( K! C9 i/ S
934533 F2B DESIGNVARI The Variant Editor errors are not written to the variants.lst file5 K. T1 }! d0 w
934811 SIP_LAYOUT UI_FORMS CDNSIP should not hang if contraction value in z-copy command is out-of-bound, K2 x. `, S. a2 Y3 ?4 \( V0 U+ k
934909 SCM UI Require support for running script on loading a design in SCM
& F% m( J$ j, ]. t/ s7 [3 z! J935632 CAPTURE SCHEMATIC_EDITOR SHIFT+Mouse wheel scroll(horizontal) of page is not working in Auto Wire Mode., S. b7 n5 ^2 k1 z' e
935794 ALLEGRO_EDITOR SHAPE BUG:Shape not filled in 16.5 but it does in 16.3' J& X% o& A' r q- T
935988 ALLEGRO_EDITOR INTERFACES When attempting to downrev this 16.5 design to 16.3 the tool will crash
/ D2 D* I0 V1 P1 y4 }936056 ALLEGRO_EDITOR DRC_CONSTR place_manual crash while moving mirrrored symbol
. [+ f0 m0 Y4 F- t7 W+ V- r936098 ALLEGRO_EDITOR SKILL axlDBCreateCloseShape does not work correctly.
/ ]1 y0 W* `/ R1 y936212 ALLEGRO_EDITOR INTERFACES DXF not created if Blocks created for Symbol and padstack5 f3 C! \0 {/ x' J0 @' G
936797 CONCEPT_HDL COPY_PROJECT Copy Project crash# O) n$ o$ t# V
936808 ALLEGRO_EDITOR DATABASE Allegro crash replace mechanical symbol) b! B6 j0 r( a: J" i
936853 CONCEPT_HDL CONSTRAINT_MGR DEHDL crashes when trying to extract net from CM# q, b j: m. j t
937087 CIS DESIGN_VARIANT Upreved design becomes very slow in Variant view mode. DELEET THE DESIGN AFTER RESOLVING THE ISSUE9 s) ^0 `. ?% G# l+ |
937173 CAPTURE OTHER Wrong license information "UNLICENSED" in Capture >> Help >> About) Y0 x: R3 d0 H8 u { D
937290 APD PLATING_BAR Plating Bar checks does not recognize connection made through etchback through shape." b+ x- G" P! }5 k1 c) v4 |* G
937411 ALLEGRO_EDITOR DATABASE downrev_library reading from one directory and writing to another hangs the command.) G' b. [ H" _# R1 E6 ?
938235 SIP_LAYOUT STREAM_IF Die Orientation is not correct after importing a stream file.+ r6 h% P- z2 o' ^
938273 ALLEGRO_EDITOR OTHER PDF export is is not opening viewer with ads_sdlog variable set3 d; m7 t- i; _: \7 A! [4 V* `
8 \1 Y4 ~- ?3 n( l( g( a, B; n
DATE: 09-16-2011 HOTFIX VERSION: 006
+ V. i4 j+ v% P1 N g( L- F3 ]9 q( n===================================================================================================================================3 D7 y3 ]' q) v, p$ K1 \5 T. y* I
CCRID PRODUCT PRODUCTLEVEL2 TITLE
" ?! W b( Z( p. v: R) x- J===================================================================================================================================
3 i! E4 f2 C' M# y9 l# B* v820131 CONCEPT_HDL OTHER Moving symbols to other page will make Allegro components unplaced because logical_path changed.6 r( [- m7 R2 p1 N- w
863860 CONSTRAINT_MGR SCHEM_FTB CM should display or Local Interface and Global nets to help defining low level constraints5 N2 n2 a; f5 @5 L0 h& ?* Q/ f
919822 TDA CORE Cannot configure LDAP to only list the login name5 ~2 x: I$ y& X+ D5 P
922907 ADW TDA 搇ast_callout_file� directive in the BOM section is empty causes tda for show Access Denied error: c* g6 B/ b4 x b5 r2 J
924322 ADW COMPONENT_BROWSE Random - No instance properties are added on Add To Design (RMB or double click) from Search Results
% X9 D4 t- f- b( B& b" S Z' \924448 F2B DESIGNVARI Design does not complete variant annotation6 @/ C# @" i4 B Q2 u
925584 CONSTRAINT_MGR SCHEM_FTB 16.3 upreved Design passes the SLOT/Function Properties to PCB6 e; i4 H" C3 n1 P& p
927102 ALLEGRO_EDITOR OTHER Question of Conductor Detailed Length Report, i# `2 ]: O6 k! n; H& W' d- E
927104 F2B DESIGNVARI Tools > Annotate variants crashes when there are ASCII characters in the property values
" ~' n. K4 O4 ^" @2 a, d ]& y927142 F2B DESIGNVARI Incorrect pop up asking while executing variant editor from the command line
" o6 c9 c& [1 k# x* u, j8 h1 \927166 CAPTURE NETLIST_ALLEGRO ENH: Feature like NET_SHORT in Capture Allegro flow which allows user to short 2 or more power nets- D. I8 L# U6 R: A) n
927410 ALLEGRO_EDITOR DATABASE ERROR(SPMHUT-144): Illegal arc specification error when Run DBDoctor7 c$ v/ k* _) Y! n% n4 t. X0 g: c
927475 CONCEPT_HDL CORE About forcereset command of nconcepthdl/ v; N1 c' _, A5 b% w
927498 CONCEPT_HDL CORE Pin_Name starting with minus causes incorrect behavior for $PN display
! F) `8 R, ^2 U+ t) x4 j& F0 D927608 ALLEGRO_EDITOR PADS_IN Import PADs fails with error message: Failed to close the Allegro database
. b& w- ?+ H7 T927637 SCM CONSTRAINT_MGR ASA crashes on change root and also performance is too slow.
! \, E- v6 u/ u0 P4 a928429 SIG_INTEGRITY OTHER Request - Package Wizard to work in PCB SI.
- a: A+ O9 j8 ]7 y P928483 ALLEGRO_EDITOR DRC_CONSTR Running Update DRC removes Via List DRC Error when via is actually not in the list
. T" b7 K) u) d; @928738 PSPICE PROBE Y-axis grid settings for multiple plots
5 Q; t3 W4 m7 E5 C2 ]* P8 h: U928748 PSPICE PROBE Cursor width settings not saved
1 K0 {, d1 q% e7 Z8 x5 C: u) p928779 CONCEPT_HDL CORE Error (1053) occurs on a copied part in SPB165 release
4 S' Z4 J8 @% n: p928838 CONCEPT_HDL CONSTRAINT_MGR ECSets not migrated in 16.59 h) `- {" e! H! {) [
928885 SIG_EXPLORER EXTRACTTOP PCB SI crashes when extracting a net from Probe6 u: D! s5 L8 r& o/ w
929284 CONCEPT_HDL ARCHIVER archive does not create a zip file
& A7 i% n% v9 ?( f8 P929542 SIP_LAYOUT DIE_ABSTRACT_IF net issue of multiple ports of co-design die in SiP
) P w3 O& x$ {+ p929656 ALLEGRO_EDITOR PADS_IN PADS translation fails with Microsoft Visual C++ Runtime Library error
% j3 P7 T$ L3 ]930063 ALLEGRO_EDITOR TESTPREP Test prep crash Allego when it can not create pin escape
" F8 J* T9 f9 j9 a: G' g, o Q930217 CAPTURE NETGROUPS Net aliases doen't gets assigend to bus bits if bus name is checked in NETGROUP. Q! i, [- \1 c, J/ }8 [& R5 n
930355 SIP_LAYOUT WIREBOND about "wirebond add nonstandard" command
5 |2 W% u! g1 n% A3 p) f) e! J930607 APD OTHER Layer mapping information is reomved from Layer conversion file upon exporting DXF from board file.2 D. N' p) s/ ?8 H, K
930646 ALLEGRO_EDITOR DRAFTING Bug - Adding Linear Dimenstion for ISO standard add the Angle information as well) T/ q! i" e. t. X- m! Q
930894 CAPTURE TCL_INTERFACE PDF export doesn't creates property file if some symbols are used in page name/folder name; X) E. g9 _+ q0 O) R" v8 `
930944 ALLEGRO_EDITOR OTHER Setting variable 'appmode' equal to 'none' is not changing the Application Mode when reinvoked/ d& Z1 X, ^3 p6 c
930978 ALLEGRO_EDITOR SCHEM_FTB 3rd party netin error - Pin is connected to net <netname> not reconnected no longer happens
+ U5 ~3 s; ? O8 y/ u8 S9 E1 s931248 ALLEGRO_EDITOR DRC_CONSTR Match Group was removed if member nets became xnets.
" t, ~+ ?4 _; ~* _+ u- Z931278 CONCEPT_HDL INFRA $PN gets copied when upreving design from 16.2 to 16.5 version
, o7 h9 _3 I" `" Q) \931349 CONCEPT_HDL COMP_BROWSER DEHDL craches and corrupts connectivity file when using Modify command extensivly., a. {* D) r P# \
( g! k; U& G/ T# h
DATE: 08-31-2011 HOTFIX VERSION: 005% s: k5 E7 J0 D6 y6 \4 C
===================================================================================================================================
* D* n2 q$ W8 h" p+ o5 K! }CCRID PRODUCT PRODUCTLEVEL2 TITLE: R' h+ s! O' J: F' R& }
===================================================================================================================================
# E1 C; r# b/ ^! J* q- T: l' m825848 ALLEGRO_EDITOR SHAPE Shape not filled when edges from 2 RKO shapes touch around mouting hole$ [6 F% R/ i' A$ W; C5 X
837723 CAPTURE PROPERTY_EDITOR Occurrences of external design not related to current root should not show
# c& ]- @1 o% x/ H+ O891079 CONCEPT_HDL CORE DEHDL crashes with large number of commands in Winodws mode% T! y7 e- M. y9 k
910908 SIG_EXPLORER OTHER Cannot open top if Tx AMI dll name contain more than 2 dot.
7 g% I2 g; y' y914036 CAPTURE LIBRARY ENH: Option to delete a corrupted part from a library and leaving other parts intact in the library.
9 l+ n/ P! v1 t6 P( z' g% Q" v914679 ALLEGRO_EDITOR INTERACTIV Custom toolbars are not retained when switching between brd to dra and back to brd file using the File > Recent Designs
. m! K, X3 B# K- `: Q914870 MODEL_INTEGRIT OTHER mergedml fails to merger 2 DML files from the model integrity
4 E& J6 q" {1 Z/ h$ I. K915645 ALLEGRO_EDITOR MANUFACT Allow the user to place the cross-section chart at a desired location( E/ s$ Y. n4 C' O4 d- L% M; r
915653 ALLEGRO_EDITOR INTERACTIV unable to delete non-etch shape# e7 [5 X1 E0 V/ Q* r! s0 e; D, v7 i( b
915711 ALLEGRO_EDITOR MANUFACT dimensioning tolerancing by limit not working
; Y! m5 \5 Y) \. Z Y3 b916321 CAPTURE GEN_BOM letter limitation in include file. r0 N& F$ ?( x/ X) ?
916907 CAPTURE SCHEMATICS 揂uto Connect to Bus� should place the wire through non-connectivity objects
3 p8 X% @" l1 ~920327 CONSTRAINT_MGR ANALYSIS The TotalEtchLength predicate in Constraint Manager does not work for a netclass with a bus.
& ]4 C" P2 t! O; a920753 ALLEGRO_EDITOR GRAPHICS If I confirm to padshape with zoom-in after install the s002 It was changed to wrong shape.
& B% u" k9 H* m- A6 a) C" `! l& W& J921097 ALLEGRO_EDITOR GRAPHICS Padstack seen partail filled when Zoomed in even "static_shapes_fill_solid" is set" P8 P8 n- g) P7 y: ]
921226 ALLEGRO_EDITOR DRAFTING Unable to select Package Geometry class when dimensioning in the symbol editor.
" _0 H3 W# L" t0 P# x7 v921623 ALLEGRO_EDITOR GRAPHICS Bug : Symbol not visible when zoomed in 16.5 S002
$ G. x" u: r, Z5 d921891 ALLEGRO_EDITOR DRAFTING dimensions are lost after downrev(ing) a SPB 16.5 design with associative dimensions+ ]5 G% Q& Y: ]. c
921937 ALLEGRO_EDITOR COLOR Padstacks with shape symbol are not showing correctly
3 c% e1 R5 e( i; g922066 CONSTRAINT_MGR ANALYSIS Custom measurement Actual not being cleared when layout changes.
' Z3 i. [/ N6 s922117 PSPICE PROBE Label colors are not correct in Probe# @' y* G J% ?, R. W
922519 ALLEGRO_EDITOR SKILL add_bviaarray command fails for some clines but not all8 m% i. n& u6 R- W+ r# A* h0 _1 E
923224 ALLEGRO_EDITOR GRAPHICS Thermal flash Display problem in Allegro v16.5 Hotfix S002& h, V" a# Z/ \* U
923286 CAPTURE DRC DRC markers not reported for undefined RefDes
' Y& \8 l* H, |! x6 l/ f923362 ALLEGRO_EDITOR PLOTTING Print to Postscript file not correct in 16.5$ |0 P, n% V( A
923416 ALLEGRO_EDITOR PAD_EDITOR Pad Designer crash on clicking on the Arrow before Soldermask_top
+ P: q$ D* x8 [0 H4 u' p. V923507 CONCEPT_HDL CONCEPT-PCBDW The function of Import Design in the SPB16.5 Design Entry HDL (for data of ADW15.5_S23 + SPB16.3)
- X1 A8 H* [9 x% S5 T! K- M/ Y923910 CIS PART_MANAGER Copy & Paste operation from Part Manager copies properties only to first section of the part./ k) `% Y. |" m9 w* p: K
923913 CAPTURE PROJECT_MANAGER Capture runs slow on attached design
1 p3 U% p: k. N% v6 y* [923937 CONCEPT_HDL CORE Back annotation time significantly increased with the metadata generation on* K3 ?9 J$ a+ p4 {; ?: Y$ m% j
923949 ALLEGRO_EDITOR INTERFACES Incremental DXF_IN gives 'Invalid subclass' error3 e" o4 @4 I8 U9 n( l7 ~ g' p
924458 SCM OTHER Project > Export > Schematics crashes6 d; g! h/ B2 q% G
924621 ALLEGRO_EDITOR SHAPE Dynamic shapes are disappearing upon updating them to smooth.9 j' B5 j/ X1 v z1 D4 @
925193 SIG_INTEGRITY FIELD_SOLVERS Diffential Impedance (DiffZ0) values computed in the layer stack-up is incorrect8 z6 r6 Q$ M2 M
925195 ALLEGRO_EDITOR DRC_CONSTR Incorrect pin to shape DRC error
6 i; j1 f9 _5 \! {- `- @925338 CONCEPT_HDL CORE This application has requested the Runtime to terminate it in an unusual way& z# S4 R4 M1 p1 F& M
925435 CAPTURE TCL_INTERFACE Capture crashes if 揝ave design as UPPERCASE� option is disabled.
7 r9 J5 C* X" Q% W( \925530 SIG_INTEGRITY OTHER Why the single line impedance value for Top and Bottom layers are different for this design?
; W7 X$ G5 h& v3 f$ J925864 ALLEGRO_EDITOR DRAFTING Ability to add dimensioning to different CLASS/SUBCLASS
" ]( K6 @' ~$ {6 q: f$ H2 D925976 ALLEGRO_EDITOR MENTOR mbs2brd fails to import data+ E, Z! }6 s& I3 `
926409 SIP_LAYOUT DRAFTING Exporting a 16.5 design to 16.3 will cause the leader/dimesion lines to be removed.* ~4 A# o+ O8 Y4 i
926443 CONCEPT_HDL CONSTRAINT_MGR In new 16.3 "035" ISR Concept2cm will crash with error.
0 E; o% n0 ]" R, ^3 U926503 CAPTURE GENERAL Memory leak Capture/Pspice+ D+ V0 M2 I8 G! H6 [
926553 CONCEPT_HDL CONSTRAINT_MGR CMGR ERROR There is no net in the Cset that has pins matching those in net 1 in the Xnet
) P! F7 j6 M6 C ~9 D w% |926691 ALLEGRO_EDITOR OTHER Crash while Importing Technology File in CM, with Overwrite Constraints.
4 u' \+ O3 q: P* @926887 CONSTRAINT_MGR CONCEPT_HDL Pin pairs lost after Export Physical
# T0 T9 O3 B* z$ v w# ~2 \8 M6 {8 `8 Z927159 CONCEPT_HDL CONSTRAINT_MGR Export Physical fails due to errors in ConCM.log when SIGNAL_MODEL injected property is ''
( g0 x* ]) H+ o; v2 p2 ^5 N4 l
' U3 q3 {" r6 W4 m. bDATE: 08-19-2011 HOTFIX VERSION: 004
* @ {1 ~! ^& B c9 R3 `===================================================================================================================================3 i3 Q( t$ q% W/ U9 G
CCRID PRODUCT PRODUCTLEVEL2 TITLE* r9 t; Y9 |1 I, Z2 l6 v1 ~+ e
===================================================================================================================================& t; e; r( U( }* ^! F
785417 CONCEPT_HDL COPY_PROJECT copyprojectui crashes with a Windows runtime error
; s( j) Z! X4 U& {851044 CAPTURE GEN_BOM "Export BOM report to Excel" does not appear in the Standard Bill of Material Window.' {5 C; D8 N- p( o- q. K' B
868216 PSPICE MODELEDITOR Encryption of subckt names, internal nodes, comments1 |, r' `4 y. P3 F/ }( b! e
870247 PSPICE SIMULATOR Encrypt a model and simulate it, info about inside nodes being dumped in the probe file
* y" Q# B# a$ U877091 CAPTURE SCHEMATICS Save JPEG, GIF, PNG and other image formats in the database in its compressed form
. p# q# t, E( y. f" t894059 CAPTURE OTHER Enhancement: Adding column in edit>browse>parts window
, I8 Z# Q: I% l# }895902 RF_PCB OTHER Alphanumerical allegro pin numbers are unusable in ADS 2009 Update 1
9 |, w; S x4 n5 B895919 RF_PCB OTHER Round trip Allegro to ADS to Allegro requirement
! y' o: [: `: F2 G# |% d+ [& J903102 ALLEGRO_EDITOR OTHER Zcopy shape command for cline seems not to work correctly., F+ D9 }- B" ?4 x9 s; X& _% n& Q
905562 SIG_INTEGRITY SIGWAVE Noise margin seems not to be measured correctly with Eye Measure function.4 s, V$ y; l! t% u" j( _
909469 SCM TABLE ASA crashes when opening project+ ^0 }1 B, e$ d9 G; p; O0 N: _
909595 APD LOGIC Inconsistency between export die text out and show element after pin swap
, J7 R8 R; M- X( D5 _911123 CONCEPT_HDL CORE 16.2 Design uprev to 16.5 fails with ERROR SPCOCD-152
; u9 a9 E* n- B( R. U- n" `911569 CAPTURE EE_INTERSHEET_RE Q: Why is capture assigning incorrect Irefs in attacehd design ?
$ ]# Z6 T6 t5 A P915657 ALLEGRO_EDITOR OTHER Allegro PDF Publisher Mirror capability
8 C6 X* o% r* q& ^; z915755 CONCEPT_HDL CONSTRAINT_MGR Cannot view net in SigXP
9 p0 B+ `% h' l. g3 X1 _916062 CAPTURE GENERAL Auto Wire Crashes Capture" N5 L, k1 H1 L( T
916820 F2B OTHER RF create netlist with problem0 d+ {* [; J9 p# y4 i
917967 ALLEGRO_EDITOR REFRESH Update symbol resets refdes location for bottom side components only.3 r: s. ~4 ?! o( {
919343 ALLEGRO_EDITOR PLACEMENT Place Manual is crashing the board file
+ F& `% c- ~% V% M9 i" P A919481 CONCEPT_HDL CHECKPLUS CheckPlus isGlobal function is not working1 h8 D% _) `9 Z$ B9 V. N
919510 CONCEPT_HDL PAGE_MGMT takes 10 min to insert page in DE HDL
2 d) V# W) Y' @" V7 P+ T919976 APD DATABASE Update Padstack to design crashed APD.
" w9 e: Z H. N8 p2 r! i" v! H$ Y920418 SIP_LAYOUT OTHER SiP enhancement to Auto Assign Pin Use to add ability to change the pin use definition; s: v* R; Y- a5 L' c. Q
920420 SIP_LAYOUT LOGIC SiP enhancement to Logic Auto Assign Net to display a dialouge Auto Pin Use assignment should be run$ T+ E0 w& } [5 ?' p/ i$ U
920712 ALLEGRO_EDITOR ARTWORK Program has encountered a problem ... error when creating artwork. U1 |. O2 H: u |( x
920763 ALLEGRO_EDITOR ARTWORK Soldermask gerber missing thru-hole pins! O" O( Z$ X7 i+ Z9 A* G5 v
920976 ALLEGRO_EDITOR GRAPHICS Question regarding the difference in the behavior of 3D Viewer w.r.t. height_min
5 I$ J B7 d) }6 x920993 ALLEGRO_EDITOR DRC_CONSTR Minimum Metal Spacing Error is detected on Same Net! ~- _; c9 T* h9 K/ V% ]1 O- P* m/ \
921727 ALLEGRO_EDITOR DRC_CONSTR Pad Boundary causing P/P drc to adjacent symbol.
! c9 j) y, L$ p% k- [& M922579 CONCEPT_HDL CORE Xcon file gets corrupted upon Save of Hierarchical design with Global nets tied to interface nets. H8 c% l4 V! [/ a, u: ^8 X
922592 CONCEPT_HDL CORE DE-HDL does not report illegal connection when Global Net tied to interface net using an Port symbol and named {, ~- ?5 { t' b$ B8 W
922758 ALLEGRO_EDITOR DATABASE Allegro crashes while placing second mechanical symbol with route keepin# c8 u% }3 _8 i/ K
922839 ALLEGRO_EDITOR DFA The DFA drc display is unstable.
3 I9 w0 s, R Z923293 ALLEGRO_EDITOR INTERFACES File> Export> IDX is failing for this design while creating an empty error log. U" Y0 Z/ J; J' J6 {7 U$ ]
924772 ADW PCBCACHE Import Sheet is not bringing in Parts used in the source pages into target cache ptf/ {, C! w8 r3 {9 I" x" _
6 Q5 a6 U, G9 W3 s; `' y
DATE: 08-4-2011 HOTFIX VERSION: 003
6 w: P: {1 f4 F: l===================================================================================================================================
. v* W, x9 B% w. Q1 g$ ~, mCCRID PRODUCT PRODUCTLEVEL2 TITLE
, _0 B2 X1 j* h7 \' O; ^7 L0 x===================================================================================================================================
( f1 d( U0 ^- U1 s2 h M& h787414 CAPTURE PROPERTY_EDITOR Part value can抰 be moved on schematic if a part has been copied to a new design and not saved yet.4 y3 X0 _8 p* X8 i' M# r
903898 PCB_LIBRARIAN GRAPHICAL_EDITOR PDV move symbol graphics and Undo causes corruption in graphics7 D: }) s1 i8 h. d G q1 H7 W. f
904287 ALLEGRO_EDITOR ARTWORK some cline with arc is missed, when creating artwork.
! N' @: J q! E6 J; r1 s% C3 k! ]904418 CHANNEL_ANALYS SIMULATION channel analysis sim does not give valid result8 G, h% X0 M) ]9 J5 {3 }
905777 SIG_INTEGRITY SIMULATION User gets popup message that halts an analysis until it is acknowledged# T( m5 f& J% B9 o
906139 SIG_INTEGRITY OTHER Bus sim result were cleared at the next run even if no preference changed.3 t' t: h: |4 g- a! l9 @$ a- F
908680 SIG_INTEGRITY OTHER Extra prop delay due to resistance) y2 Q. m5 _ K" d
909583 ALLEGRO_EDITOR SKILL axlPolyOperation AND operation is not working correctly.' t9 M- C$ F5 q
910315 ADW LRM Import Design with ADW causes partmgr and pxl errors% S) L* H* n t
910689 CONCEPT_HDL CONSTRAINT_MGR NO_SWAP_COMP warning after uprev to 16.5
* y, q" O: w! P" V) L7 t- H2 @911684 CONCEPT_HDL CONSTRAINT_MGR Attribute Definitions are incompatible for attribute 'HEADER'. when attempting to place in 16.54 i; @8 F' c# v& a% J
912343 APD OTHER APD crash on trying to modify the padstack* p# R* Y2 W" O$ V, d
912384 PCB_LIBRARIAN CORE PDV Symbol Editor often freezes when moving groups objects by arrow keys' h- ?8 k, c# E6 U" N; B& D: z: u
912853 APD OTHER Fillets lost when open in 16.3.
0 N6 N* T* {( I% q9 M2 o913586 ALLEGRO_EDITOR ARTWORK Cannot create the drill figures in this design.
: R+ j$ y* v7 g9 a3 E. [, j914009 ALLEGRO_EDITOR DRC_CONSTR Diff impedance worksheet showing almost zero impedance for differential pair in attached testcase.- t! [5 d( a+ H3 l) F9 Q3 R. _% R
914110 CONCEPT_HDL OTHER DEHDL 16.5 Uprev overides property values on hierachical blocks
: T5 c+ a/ C) {914264 F2B OTHER Cross Probing from DEHDL for global nets present inside block doesn抰 highlight in PCB Editor.; Z7 o$ G" N9 Z9 } Y7 V
914309 CONCEPT_HDL CORE 16.5 DEHDL crash on saving the user design' R3 i. c' g4 }: L
914558 ALLEGRO_EDITOR ARTWORK Gerber6x00 output creates unpainted niche in a shape5 d6 K7 Z6 Z1 F- y
914633 ALLEGRO_EDITOR ARTWORK Artwork failing in v16.5 while the same design when downrev'd to 16.3 is working fine.2 N- Z# u$ v+ M0 _. e1 A$ f
914634 ALLEGRO_EDITOR SKILL IsThrough flag for a padstack is reset
. h! L* a6 z* M2 F914746 ALLEGRO_EDITOR DRC_CONSTR DRC Update repeats takes longer on each successive pass.
" L0 P& a4 o0 l* V0 a4 Q" d914962 ALLEGRO_EDITOR SHAPE Corruption with Shape filling1 R2 i* Q# {, w
915583 CONCEPT_HDL CORE performance issues in 16.5 compared to 16.3. y* T% X" s% v* j! e8 h
915630 PCB_LIBRARIAN OTHER Error when running SI Model Interface Comparison using IBIS models1 C$ N4 ~) T( i y# }; C& b
915742 CONCEPT_HDL HDLDIRECT I get a newgenasym error and crash when trying to save the symbol
- I0 \" q* Q. f" ^3 I& M916154 SCM NETLISTER scm crashes when exporting physical database to allegro
5 j2 _4 Z1 z- z* q916448 CAPTURE NETLIST_LAYOUT Capture 16.5 Layout netlist contains errors
6 ~/ G; u1 ?! L% j1 [916462 ALLEGRO_EDITOR DATABASE Edit>Split_plane>create hangs Allgro PCB Editor* h3 }0 `, b1 H$ P6 D
916469 ALLEGRO_EDITOR REPORTS One Unrouted pin does not show in Unconnected Pins Report+ G' E! E! T8 s( ?' s6 O D W
916495 ALLEGRO_EDITOR INTERACTIV Pick selects components from invisible (Off ) layer% w+ V' C9 F0 q( |$ k
916889 CAPTURE NETGROUPS How to change unnamed net group name?
( t) T3 N3 `' u917002 ALLEGRO_EDITOR OTHER Allegro PDF Publisher creates extra circles not available on film
$ o# p' R+ g0 O4 i3 D: k917434 APD OTHER Stream out GDSII has more pads in output data.5 w d0 A" A9 H0 L. o+ j
917739 CONCEPT_HDL INFRA Global Net tied to port is getting split into 2 nets in 16.5, in 16.3 it is treated as a single net
7 R$ V) X1 m4 S& x7 \' E- |918187 CONSTRAINT_MGR OTHER Missing acGetTotalEtchLength predicate.
3 M& F7 A- F& f$ N* C918576 CAPTURE DRC Incorrect DRC is reported for visible power pins which are connected to power symbol
( ]/ {5 ]8 k' R6 X
( x9 S7 d; ^8 S. tDATE: 07-24-2011 HOTFIX VERSION: 002# |: l; y( r c' ~, P
===================================================================================================================================
# z) @( q! w' D L" J6 cCCRID PRODUCT PRODUCTLEVEL2 TITLE6 i8 K2 s+ p1 q+ v
===================================================================================================================================0 `+ Q1 R8 x" t& Q: S0 H/ q& ~2 x
527444 ALLEGRO_EDITOR EDIT_ETCH Slide command needs to be enhanced for same net spacings
4 ^7 W- I- x4 t583257 ALLEGRO_EDITOR EDIT_ETCH Add Connect and slide command needs to be enhanced for same net spacings.* z. n/ J+ L0 A: ~; C
592956 ALLEGRO_EDITOR EDIT_ETCH Same net traces will not push and/or shove each other.
1 \5 ~! m* i5 b745285 ALLEGRO_EDITOR EDIT_ETCH Requesting a true "shove" in Route > Slide for Same net routing.! j, U2 P9 {" O3 V. G
773503 CAPTURE OTHER Doing "Mirror Horizontally" creates extra un-connects or extra junction dots in Capture V16.3.8 W% v+ Q4 W' `& C! q: u
774270 F2B PACKAGERXL Require to ignore space in Pattern setting to prevent duplicated Refdes., `9 Q' v' K; `5 u/ X; [
799984 ALLEGRO_EDITOR INTERACTIV Enhance the Fix command to select just cline segs
# T. z5 e; f$ A, A u, n809008 CAPTURE SCHEMATIC_EDITOR New nodes get appeared within the design when we select the design and do "Mirror Horizontally".
) C: O# Q. R# C810058 CAPTURE SCHEMATIC_EDITOR New nodes get appeared within the design when we select the design and do "Mirror Horizontally".0 L: ~7 c Y4 ~# z" G6 P% [0 ]
821133 ALLEGRO_EDITOR MANUFACT Output artwork for pad data that are suppressed unconnected pads with Gerber 6x00 format; j8 ]: h/ l4 N4 V2 u, P
831710 CAPTURE SCHEMATIC_EDITOR Capture adds extra junctions to design by itself2 |4 N& ] M) s* ?# W
842410 ALLEGRO_EDITOR EDIT_ETCH Ability to slide with "Shove" for "Same Net" segments/vias.
8 u0 h7 Z8 U' ^- v+ h# t) o* F( Q854971 ALLEGRO_EDITOR INTERACTIV Capability to add cline segment in a temp group, S5 J6 X) O) p9 p* R) i3 J
860772 ADW PCBCACHE Save Shopping Cart (pcbcache) is crashing component browser
$ A0 c- C( ]+ P7 K( j3 [867842 CAPTURE PROJECT_MANAGER Capture crash with 'Open File Location"
! {* i; Q: z2 S& \% s2 U5 t3 e" k868306 CAPTURE CONNECTIVITY mirror vertically removes junction creates extra nets
; ^& {" S R5 L2 R0 g2 z882677 EMI RULE_CHECK bypass_plane_split fail if BYPASS_XXXX_EFFECT_DISTANCE
. L7 Z) i! E' F+ P4 ?891439 ALLEGRO_EDITOR INTERACTIV moving cline segments
4 `& v# J/ Q. f893544 ALLEGRO_EDITOR INTERFACES IPC-D-356A netlist issue with BB vias.
# `+ Z9 }( j0 S# m. @2 k893765 ALLEGRO_EDITOR PARTITION Mail command not sending out email on Linux platforms.! g7 y/ ?' z3 g R
894390 SIP_LAYOUT EXPORT_DATA Generate all balls in the xml file for export to EDI's readPackage command
/ x, d' H' a: p6 A895933 APD DATABASE Update Symbol shifts the center of the Dynamic Fillet and creating DRCs9 i% l1 G+ J" I z
896598 ALLEGRO_EDITOR PLACEMENT error message is misleading2 ^' ~0 A8 _% K5 S
897196 CIS LINK_DATABASE_PA Schematic Contents are not shown in CIS window while link Dbase part for parts placed from library' e0 Z( ^/ T2 ^# ]# w0 E
898598 ALLEGRO_EDITOR MENTOR Negative planes from Mentor Board Station not being translated.# d$ J& S- w8 H& E1 f" x1 p8 p$ z: ]
899556 ALLEGRO_EDITOR ARTWORK Import artwork seems not to work correctly.
. r$ E! E: w8 q, ^! y9 n900501 ALLEGRO_EDITOR PLACEMENT "lace Replicate Apply" is showing lot of DRC's during placement of replicated circuit in 16.5% ~3 I) A; B. t: ^+ P* t# l) C0 `$ G
901141 CIS EXPLORER Japanese character appear garbled in CIS explorer window.
+ a' z, `8 Y! f901666 CAPTURE OTHER Home page of Flowcad-Switzerland and Flowcal-Poland is not preserved on captre restart on start page$ {( b Y# B# `. V$ v7 `5 |" \- G3 r4 X
902066 ALLEGRO_EDITOR DRC_CONSTR Shape in Region not follow the constrains, k" K ~# X) s4 `" G B. A. V
902349 CAPTURE LIBRARY Capture crashes while closing library
0 y' \7 i" Z& L# L0 W w902508 F2B PACKAGERXL SPB16.5 Packager-XL consumes much more memory than 16.33 e' s6 m; t% `+ f5 O
902841 CAPTURE GENERAL Capture Start page does not show% D! G8 v1 T U
902876 F2B PACKAGERXL Packager fails on the design upreved in 16.5
9 z( k3 I b1 ^, _8 e1 ?* ^902959 CONCEPT_HDL HDLDIRECT HDLDirect Error while saving design0 @( K$ a* e5 i! w% \
903171 PSPICE NETLISTER Why Capture is treating hierarchical power ports as floting nets in complex heirarchy designs?
$ \. m: f! M7 V R9 ?+ e6 |903713 ALLEGRO_EDITOR PARTITION Placement Replication do not work fine in the Design Partition
, e. j m# J( V0 r/ B% A, t: w903799 SIP_LAYOUT DIE_EDITOR Disappear die pins after exiting co-design die editor
# a8 Y8 W( b# y904021 ALLEGRO_EDITOR OTHER Export PDF from SPB 16.5 produces a file not text searchable3 y' k# y1 H( o) Q' g E1 q
904339 CONCEPT_HDL CORE new design crashes using the attached CDS_SITE0 d, f6 J e, g2 A
904522 F2B PACKAGERXL Part will not package in 16.5 but packages in 16.35 D7 g: ]. e$ u, O# y9 F1 @
904764 APD OTHER Enhance Scale Factor of Stream Out to support 4 decimal places
' ]9 ]. G3 I' H+ O904771 ALLEGRO_EDITOR MANUFACT Pin Number display issue.
X3 I3 L; M! h9 @& H904853 ALLEGRO_EDITOR GRAPHICS Enhancement for showing Static shape as it was seen in 16.33 T: g6 f) ^2 ]% R, w
905144 CONSTRAINT_MGR ECS_APPLY Min Line Spacing is larger than Primary or Neck Gap less(-) Tolerance but No Warning in CM
0 S) Y2 p& H8 P1 x3 ^/ Q2 m {% d905314 F2B PACKAGERXL Import physical causes csb corruption; G- g$ q& N# ~8 N; Z. ]
905337 CONCEPT_HDL CORE ConceptHDL crashes after Import Design process.
& U, Q+ P! e& x" f5 R3 ]$ A905533 ALLEGRO_EDITOR INTERACTIV Pin numbers for components on BOTTOM Side are moved in Preselect mode,when the BOTTOM layer is invisible
K0 r/ N+ d, V; V6 u905796 CONCEPT_HDL CONSTRAINT_MGR Fujitsu CM issue inaccurate concept2cm diff pair issues
, H( \& K. O. P! g0 G& ^905811 CAPTURE EE_INTERSHEET_RE interesheet references in the form of grid grid page number instead of page number grid
' \1 [5 A6 p, y! @ L5 h& C5 ~! {9 J906118 CONCEPT_HDL CONSTRAINT_MGR Cannot open CM if SIGNAL_MODEL value was not assigned in ptf.3 M m/ o: ]. u9 O! t4 B8 o
906153 ALLEGRO_EDITOR SCRIPTS Unable to run allegro script in batch mode on the attached board.
! I! {# |% Y; K6 E) Q+ V5 ^0 F906182 APD EXPORT_DATA Modify Board Level Component Output format; \9 L/ H6 o/ u( W4 w8 |
906200 ALLEGRO_EDITOR DFA Enh- DFA drc invoked in Batch mode returns false constraint value in Show Element
+ |1 h; y# I0 q9 T, l$ ~ y906517 PSPICE PROBE PSpice new cursor window shows incorrect result.
+ R8 A. c, `( `" E$ M906627 ADW COMPONENT_BROWSE ppt options are not read if ucb is launched from FM. works fine if launched from dehdl.
) z' U' ^/ g( U' z2 g906647 SIG_INTEGRITY LIBRARY lib_dist creates a signoise.log in current directory (with backup files like ,1 ,2 etc.) on each run3 @; v! D6 o* S( \5 D( B4 w5 ]
906673 F2B PACKAGERXL Ignore the signal model validity check during packaging# N* K+ @, s! `) B: E
906688 ADW LRM A copy of source design gets created in worklib of target design after 'Import Design'4 q) v0 j" o0 a1 F2 a4 e- ]2 D
906750 ALLEGRO_EDITOR PARTITION Importing design partition removes the testpoint reference designation9 d' A" ]- g0 G' m/ O- W) A
906874 PSPICE NETLISTER Error less than 2 connections for unconnected hierarchical pin" E) T# w9 p6 @% u4 b. x
907095 F2B OTHER Part Manager does not show Error as Undefined when directive ptf_mismatch_exclude_inj_prop is used+ l' E6 I. Q( H0 c
907424 ALLEGRO_EDITOR GRAPHICS Allegro add option for pre 16.5 shape display- ]; J$ T4 {' H/ b) Q
907490 CAPTURE NETLIST_LAYOUT 16.5 Layout netlist is not correct. It differs form 16.3 layout netlist.5 _8 C$ C$ ~# A/ o/ N' W
907884 SIP_LAYOUT MANUFACTURING Need to add an "NC" pin text option for "Manufacturing Documentation Display Pin Text"6 C( g$ j3 J4 d8 }! Y! L
907885 SIG_INTEGRITY OTHER Matchgroup targets lost when importing netlist to Allegro layout in HF31
$ b9 z& f; h7 D6 m7 ?907929 CAPTURE TCL_SAMPLE TCL command to delete a property from parts in a library is not working correctly
0 R) `; C& K: T* [907933 SIG_INTEGRITY OTHER Single line impedence not working in OrCad PCB Professional
/ Z8 K9 j. o/ O907963 CONCEPT_HDL CORE Design uprev issue when moving from 16.2 to 16.5
3 s- ]: _1 z8 N( \9 s908000 SIG_INTEGRITY OTHER Inconsistence z-axis delay reported on Tpoint when define at via location.
0 s+ f8 u# v% R6 z; R908057 CONCEPT_HDL CORE DE HDL crash with the cut and paste of a signal name, B, O- r2 H# s# [1 {# _% E
908060 CONCEPT_HDL CORE CTRL+LMB Option not working correctly in 16.3
0 i- R. ?) E8 ?8 I908210 CAPTURE CONNECTIVITY Connection is being lost while dragging a component2 v5 ~+ K" J$ J' Y
908241 CAPTURE DRC DRC error column is blank in DRC markers window in 16.56 }" h3 h5 z4 i$ [, u( J% t
908339 RF_PCB BE_IFF_IMPORT mechanical holes VIAFC are not at the right place7 `6 `! e# f2 {- p. a" \
908534 SIP_LAYOUT SYMB_EDIT_APPMOD issues with symbol editor and copying pin arrays2 \$ L( g w! I O
908535 F2B DESIGNVARI When I try to view my variant file the variant editor crashes* ^. a: }3 r4 Z( D* m
908595 APD 3D_VIEWER Cadence Design 3D viewer" screen pops up and is all black because the colors have all converted to b, q" V/ ^7 r6 {& s0 k
908849 CAPTURE ANNOTATE Getting crash while annotating the attached design
# l0 e0 f0 @2 d( I. E) z908874 CONCEPT_HDL CORE Part Manager - No Part Found error when using CCR# 775788 feature
( A7 S f, |' ~" W- S909077 CONCEPT_HDL CORE After packaging pin numbers remains invisible even when $PN
/ Y, r) |% |$ l2 c5 i7 l E909104 ALLEGRO_EDITOR SYMBOL Warning message needs to be modified. It does not save the symbol and also not tell the actual problem.
5 h/ F0 [$ o! A4 _) @1 t4 @909417 ALLEGRO_EDITOR REPORTS "report -v upc" returns 'Segmentation fault' on Linux
, p$ _3 A9 y1 V- }; o909635 SIP_LAYOUT DIE_STACK_EDITOR Add Interposer crashes in SiP Layout
& H4 ?0 v- a+ A j% N909749 ALLEGRO_EDITOR MANUFACT Allegro Crash during dimensioning- H3 b5 h" F# d, k
909760 SIP_LAYOUT MANUFACTURING Create bond finger solder mask doesn't follow the mask opening as defined in the padstack
( t+ J) _: h& E6 z8 Q909861 F2B PACKAGERXL NetAssembler broken within the latest 16.30.031
, V# E' K/ }. u- `2 s+ Q4 Q3 r910006 CONCEPT_HDL INFRA Motorola design fails to uprev from 16.3 to 16.5, xcon file is getting corrupted.
! l% L/ u2 i% T. A1 G# I1 ~910141 CAPTURE NETGROUPS Modify NetGroup definition does not update Offpage Connector
5 I, v1 |8 |* t, T5 ~910340 ADW LRM Import design in schematic, only 1 page import, the entire block is getting imported.- P& ~ r+ e+ n) j. h" }
910678 SIG_INTEGRITY OTHER The Analyze> Model Assignment> Auto setup is not creating/assigning models to discrete components in 16.5
+ U! X5 Z1 w& A" j4 X% E910713 F2B DESIGNVARI Variant Editor crashes when you click web link under Physical Part Filter window.
2 k# n, M% b! ^; X2 F3 c. b/ `910936 F2B PACKAGERXL ConceptHDL subdesign net name is inconsistent
/ E# S, ]) V# a911530 ALLEGRO_EDITOR SYMBOL Package Symbol Wizard does not create symbol with the name given
: q& `; c& r' U3 ]8 |' m* e- G911631 CONCEPT_HDL CORE DEHDL crashes when opening a design6 c: m7 _& {" b0 n! `! N) I
912001 ALLEGRO_EDITOR OTHER option_licenses entries are made in allegro.ini even when not set as default: S o" U: Y: E0 @& z E( x
912459 F2B BOM BOMHDL crashes before getting to a menu) ^( W" @0 w/ }. ^ h2 S
913359 APD MANUFACTURING Package Report shows incorrect data$ A! {. y7 U; h, E
* t c/ h/ @) [$ _- v. G8 ?7 b( \
DATE: 06-24-2011 HOTFIX VERSION: 001( J2 E4 ~# G1 X: i( l: }! W5 N
===================================================================================================================================
6 b4 L. Z( K' @2 vCCRID PRODUCT PRODUCTLEVEL2 TITLE
0 H' _- m9 O9 R===================================================================================================================================6 A" `( \( H( l1 F: M, _1 K" t
293005 ALLEGRO_EDITOR DATABASE Allegro crash when attempting to move mech. symbol/ q& _/ a4 ]6 c
298289 CIS EXPLORER CIS querry gives wrong results
+ n4 H2 a) ?7 @: f1 g366939 ALLEGRO_EDITOR OTHER Cannot attach refdes on silk subclass with add text6 x/ }$ I% g5 V6 M$ G+ u
432200 ALLEGRO_EDITOR MANUFACT Fillets with an arc are required for Flexi designs
K+ @6 M+ ?9 T/ g q s8 Q443447 APD SHAPE Shapes not following the acute angle trim control setting.
1 }# W) T& M6 h& x7 }473308 PSPICE AA_SENS Passing variables to lower level blocks using subparam
5 J. L9 C# m- {% X4 }3 e/ V" X517556 PSPICE AA_SENS Advanced Analysis does not support variables being passed down the hierarchy
# a9 A9 a2 `, q* {3 s548143 ALLEGRO_EDITOR SHAPE Dynamic shpe on Etch TOP will not void properly.
$ L- R, N( @1 Z5 \5 a2 w606959 ADW COMPONENT_BROWSE Key properties with blank values are not getting read in shooping cart
, E% r- A. n2 |. s, z, d M+ P616466 ALLEGRO_EDITOR SHAPE Solid shapes are not getting filled. W) u( f5 F, E! a' b
641358 SIP_LAYOUT DIE_STACK_EDITOR Request for Via and Multi Layer Pin support for DIE stack Area (blue region)& o. [1 Q$ m( D- I
644122 SIP_LAYOUT OTHER SiP Layout - xsection - ERROR Adjacent conductive layers are not allowed, but these are diestack layers not conductor
$ s7 j( v ^" z- x1 b* Q645816 ALLEGRO_EDITOR SHAPE Slide a cline all removes gnd shapes on board
2 R( p$ ~" w( A$ X" U725355 ALLEGRO_EDITOR SHAPE User can not voided Logo correctly.3 O7 @7 N8 R$ R8 D
763569 CONCEPT_HDL CORE Display status of Hide/Show unconnected pins icon in DE HDL UI1 s4 ^, H2 @/ M- _
770021 CAPTURE BACKANNOTATE Changing pin group property after pin swap resets pin numbers* A6 m' _. m' D" G0 `6 o5 b* x
792126 CAPTURE PROPERTY_EDITOR Attempt to change display for occ prop resets
- o |/ c+ u9 m799014 CONCEPT_HDL CONSTRAINT_MGR concept2cm errors not shown in export physical after hier_write6 B" O$ p# b' r3 _8 G* E1 j1 V
803147 CIS LINK_DATABASE_PA Link DB part should not change RefDes of multi package part
3 V6 e) f! _* E- w( N804240 PSPICE DEHDL Problem in simulation result for a multi-section split part.& }& q5 v4 `' ~) l, ]
809118 CAPTURE NETLISTS ENH to compare two schematic Capture designs
2 k9 D [5 R7 I G. ~1 m4 ]816568 ALLEGRO_EDITOR SHAPE shape disappears when update to smooth.. State no etch3 [# `& }6 Z8 f4 T% p8 x4 I
830053 CAPTURE STABILITY DXF export fails if schematic folder name as /
6 F; G2 ]7 C) l$ c: M! ^832108 ALLEGRO_EDITOR SHAPE Shape void incorrectly.
! }+ t2 R( a7 t, c833542 CONCEPT_HDL CORE PDF publisher font is NOT WYSIWIG with respect to what seen in DE HDL
) N* o5 x' M! I) e. W# p835777 CIS DERIVE_NEW_DB_PA For XLS, donot display table as worksheetName$worksheetName to avoid 8012 error- W3 N& b/ z% D
837640 CIS GEN_BOM date format of CIS BOM has broken macros of 16.2 in 16.3 version6 V# V9 O: ^0 `+ v) `! L9 S
844074 APD SPECCTRA_IF Export Router fails with memory errors.
8 B8 T6 y- w. h; c8 E! p s) R851595 CONCEPT_HDL CORE Pin numbers overlap on the pin and increase in size
. f3 j) A0 c+ t3 G, S/ w. e852832 CAPTURE BACKANNOTATE Why is Capture crashing with Mentor back annotation?+ e. T9 K7 {$ s0 ]7 G
855015 ALLEGRO_EDITOR OTHER The rats are NOT connecting to the ends of the clines like they should be.
5 d a' U0 U" u. ?2 ]$ @859883 CAPTURE NETLISTS ENH to compare two schematic Capture designs
" H- Z$ s. e b$ p1 a) v$ ]866009 SIG_INTEGRITY OTHER Net with Pull-up/down should not be used for Diff-pair.
# q: N4 p/ c( H/ M3 A0 }! L866830 SCM REPORTS Multiple lines added as separator between title block and report header instead of single line: l$ E9 d0 |0 \( C! t
866833 SCM REPORTS Extra indentation is left in the left side of the report when the Line Numbers are set to OFF
9 e7 X9 I8 p7 u1 I% X868618 SCM IMPORTS Block re-import does not update the docsch and sch view4 ~! E$ ~8 \; ]% f0 J
873402 SIP_LAYOUT LOGIC pin swap for co-design die in SiP
7 q' j" K/ g9 r' t+ k: I# e874010 SIG_INTEGRITY OTHER PCB SI crashes when the Xnet is extracted with VARIANT_TO_IGNORE property.
6 e5 [: a( |# y5 r c: [' P4 Z874400 ALLEGRO_EDITOR INTERACTIV Flip mode issue with move command7 i5 C3 j2 `2 C$ r# H9 f' `" b
874966 ALLEGRO_EDITOR INTERFACES Placed mechanical component do not get Ref Des or part number in IDF file
& F6 u8 W2 N( ^2 |! {7 C t875709 ALLEGRO_EDITOR REPORTS Film area report generated incorrect data at l1
9 Q1 h. F! l# e876275 CONCEPT_HDL CONSTRAINT_MGR Constraint Manager not retaining target net2 {8 U0 e" F$ M6 V
879361 SCM UI SCM crashes when opening project
; \/ E. L. J: \. L4 L- {879496 CONCEPT_HDL OTHER Customer wants to have the tabulation� key as separator in HDL BOM.8 C: s; X" {9 ?) @: Z
879514 PSPICE AA_MC Monte Carlo to handle equation as comp VALUE.+ @- {5 n2 Q( h# j
881845 ALLEGRO_EDITOR SHAPE Delete island deletes complete shape
. \' W. T% i$ b6 A& Y' f8 w882413 PDN_ANALYSIS PCB_PI PDN Analysis should support routed power nets* F2 s) a$ H. n6 ~
882427 PDN_ANALYSIS PCB_PI PDN Analysis target impedance should have a variable multiplier% N- X0 L$ J/ f
882567 SIG_INTEGRITY OTHER PCB SI crash if boolean type prop was specified to VARIANT env.# J( J, ~5 Q j! W9 {
882644 ALLEGRO_EDITOR PLACEMENT PCB Place Replicate Function automatically match Enhancement3 Z' c) Z8 x; a8 e% }; Y- F6 M. C
883164 ALLEGRO_EDITOR INTERACTIV Vias marked fanout moves away from position when moving component; @6 c3 c* C; c0 n: l
883224 SIG_INTEGRITY SIMULATION crash while reflection simulation from Constraint Manager& x9 F4 `1 N5 U6 l; J
883760 PCB_LIBRARIAN METADATA Incorrectly formatted revision.dat file in the metadata folder6 Y- N/ j B* |% u' ~1 y( R
885391 SIG_INTEGRITY SIMULATION RLGC data sampling algorithm and w-element interpolation. E1 O$ }7 S: A, n" ]4 Z- @! ?
885849 ALLEGRO_EDITOR MANUFACT Silkscreen Audit cannot find Solder mask for the text string
( Y* X2 a! Z# e6 ^2 C885996 SIG_INTEGRITY OTHER The effect of sn_maxwidthlimit user preference is not seen in cross section impedance calculations0 }7 S4 n- |1 T
886090 ALLEGRO_EDITOR INTERACTIV Add Arc w/Radius does not snap to grid8 I0 Z7 A. M; y( g o. X
887180 CAPTURE SCHEMATIC_EDITOR Signals Navigation window doesnt get updated for Buses1 A9 T2 W9 u! ^. O6 Y
887442 APD SHAPE Copper pour of Dynamic shapes on Top layer which contains many existing signal traces fails.: c# L* o, w; ~$ M$ I
887578 SCM AUTO_UI Component Replace pops-up the DSPANE-204 Message6 r8 @5 ?3 k" I
887926 SIG_INTEGRITY GEOMETRY_EXTRACT Field solution failed if diff trace on bottom doesn't have reference plane.3 o9 G$ X+ V& a6 {! b7 l( n) D
888414 SIG_EXPLORER OTHER View Trace Parameter display the thickness of dielectric incorrectly.( | |" d c) f9 x" W4 h
888600 CONCEPT_HDL CREFER Cross References not added to Schegen schematic
6 v, E+ s; I( b& M. g5 ^& J888679 SIP_LAYOUT SHAPE Can't create the Dynamic shape on layer M1_sig without unwanted horizontal openings appearing.
3 d- F9 z! ?) Y0 L888804 ALLEGRO_EDITOR OTHER Fillet will become static shape after import from partition board.
/ K( D9 V3 ~; D) m0 M888945 CONCEPT_HDL OTHER unplaced component after placing module- P/ s I2 \5 N3 U/ |) N8 Q
889222 ALLEGRO_EDITOR SHAPE Allegro freezes/hangs when adding shape as Polygon with OpenGL ON.& j- S% v8 ^# @* ~3 h
889365 SIG_INTEGRITY GEOMETRY_EXTRACT top/bottom trace impedances extracted to sigxp are wrong in 16.3/ ~6 |4 r, U( j% n+ U/ {
889404 ALLEGRO_EDITOR OTHER Incorrect pad size for Top conductor padstack written to column 59-62.
4 S9 V/ o- }$ L' B0 ?, N889426 CONCEPT_HDL CHECKPLUS CheckPlus does not find single node net. s7 Y5 X9 S" G0 \% U/ K
889636 ALLEGRO_EDITOR MANUFACT Incorrect spelling of "Visibility" in "Film Control" tab in the Artwork Control Form3 e7 K% Q2 I* Q; c J
891235 F2B PACKAGERXL Packager crashes without creating a pxl.log file
B5 B' i) @7 k( `7 j2 l1 x- |891292 ALLEGRO_EDITOR SHAPE arc routing causes weird undesireable shape fill performance3 p8 b2 A& J+ |/ w( n. u
891856 ALLEGRO_EDITOR EDIT_ETCH crash when sliding diff pairs! R2 t' [: R! ?6 P; _
892375 ALLEGRO_EDITOR PLACEMENT Place Replicate Update disband other groups, irrespective Fixed property added or not.
4 T& o" I+ X l) A4 D2 K6 l892455 ALLEGRO_EDITOR SYMBOL Why the overlapping pins are not reported with DRC?
, r! f4 L8 K% z: r892541 SIG_EXPLORER OTHER Export/Import layerstack through the technology file is changing the layer thickness/ Z8 @6 Q+ E6 E: \5 e4 L- ^% E3 {
892766 APD WIREBOND Excuting Finger moving cannot push aside finger to move with together by shove all mode
4 O" k; N+ Q$ Z3 h892907 ALLEGRO_EDITOR DRC_CONSTR DRC not reported for etch_turn_under_pin violations
0 r* i7 o* O7 G. C) j892963 ALLEGRO_EDITOR SKILL Bad shape boundary created after axlPolyOperation 'OR
* q% m0 F) r6 G4 e892964 SIP_LAYOUT LOGIC Request that Edit Parts List use Dashes "-".
; l0 Z& A6 W. T, K3 Q893295 APD WIREBOND Why move wirebond command does not shove wirebonds? This result in drcs.6 S/ Q0 M* Q5 X! m
893706 CONSTRAINT_MGR OTHER On line DRC hangs on partitioned board- G/ a% f" [7 W! k. r
893743 APD EDIT_ETCH Route behavior when spanning pads not as expected.5 O( p' `8 r" n' S# X! }
893783 SIP_LAYOUT OTHER Padstack Design Editing update File menu with a Update to Design and Close instead of 2 operation
: Z3 j% Z+ l ^' B7 ^( U" w% o0 g894456 ALLEGRO_EDITOR REPORTS Request Net names be added to Propagation delay lines of the DRC report.
$ J/ C2 A/ V/ l: a894499 SIG_INTEGRITY LIBRARY Tool crashes when moving a cline or selecting the Info icon with OpenGL on.
# Y2 u$ h _$ Y- U894582 APD SHAPE When making a dynamic xhatch Via shapes surrounding are abnormal.
. j, j, S, _3 v% V895542 SIP_LAYOUT WIREBOND SIP design crashing when moving bond finger using blur mode BLUR_BONDFINGER_PRESRV_CON! G% v( m8 h+ |( d- J0 \* L6 d
895591 ALLEGRO_EDITOR PCAD_IN Importing PCAD file fails to get to the point where we can map layers( v, A2 s/ ] H2 x# n' z
895757 APD ARTWORK Import Gerber command could not be imported Gerber data
2 F; B9 `# N: }' h7 K/ t. u/ K+ S895964 CONCEPT_HDL CHECKPLUS The CheckPlus command getFileSubstrings is not working correctly
6 z1 a' v, o+ \* v1 r9 F% v896428 SCM UI Changed Ref Des value not maintained in DEHDL block when part is replaced: K( u' ] P$ c& e1 A" q
896655 CAPTURE EDIF Import/Export Design of Hierarcy design with OrCAD Capture5 }; a! f" e" w. c
896846 CAPTURE IMPORT/EXPORT Import edif2cap and capture is crashing
" V$ M, t' s9 E Y897155 ALLEGRO_EDITOR REPORTS Copper coverage in L2 and L7 looks like the same but film area report had large gap.! w! W" Z# V0 `( e( i$ t3 A
897654 CAPTURE EE_INTERSHEET_RE Capture crashes on adding intersheet refernces in abbreviated format on attached design.# N( G; |$ T3 P6 B2 z
899344 RF_PCB BE_IFF_EXPORT dlibx2iff does not provide the component boundary drawing
8 G' g2 d3 I. o) a1 A899629 CONSTRAINT_MGR OTHER ECset for Total Etch Lenght is not present in OrCAD Prof7 J' P4 G' f2 a
900175 CONCEPT_HDL CONSTRAINT_MGR Few Xnets are lost from Match Group after packaging and importing the netlist to board file.
9 N# M1 T0 y1 k! ]+ J4 c, h2 b5 C900481 CONCEPT_HDL CORE Genview creates a larger symbol without taking the no. of pin in consideration. O$ q2 [4 h8 x2 B
900813 ALLEGRO_EDITOR DRC_CONSTR With rotated pads, pad (pin - via) soldermask spacing DRC is unreasonable.5 o! e1 Q! a' X: {' r% W
900905 PSPICE STABILITY Simsrvr crash and RPC Server unavailable error while running simulation.
+ S+ p3 L/ d, x) z& t% `4 Z7 y+ R901783 CONCEPT_HDL CORE CDS_PART_NAME is annotated on the schematic canvas after running back annotation in 16.5
, O: S$ w! m% s9 @6 ]- F4 n: v901909 APD EXPORT_DATA The "package_pin_delay_length.rpt" with Z-axis delay turned on seems wrong6 _ q, l* _9 ^4 V1 l, G2 N, J
901987 CONCEPT_HDL OTHER SPB16.5 zoom fit does not center the page while ploting the schematic page
5 }) x* P$ v: @+ V4 {902133 CIS OTHER The visible part property value are being shown very distant from part graphics on schematic
, n& E1 a4 _- r+ u1 e% l902166 SPECCTRA ROUTE Specctra crashes when reading in "bestsave.w" file
7 } V* r. S, }0 ^ l902170 ALLEGRO_EDITOR DATABASE Diffpair Issues with OrCad PCB Designer Professional
7 n, c2 l# y9 K$ H1 F" n P902177 CONSTRAINT_MGR CONCEPT_HDL Option to view the layer thickness in CM worksheet through worksheet customization4 p/ L8 f2 G5 R; I* h
902463 ALLEGRO_EDITOR INTERACTIV APD crashes when we click ( show element ) on certain components3 s8 y/ \2 K) N
902621 CONCEPT_HDL OTHER Design Differences (vdd) Crashes0 ?, a7 a i! B8 x# V
902909 APD WIREBOND die to die wirebond crash
1 a+ C- v3 T1 F902933 ALLEGRO_EDITOR PADS_IN Pads_in fails while reading PADS ASCII file body
4 v Z- J7 P5 C4 f903284 PDN_ANALYSIS PCB_STATICIRDROP IRDrop voltage gradients are plotted outside of the PCB outline! a( w7 a* s/ P/ ~" p: x
903680 CONSTRAINT_MGR ECS_APPLY Constraint Manager not passing all hiearchical member objects to a custom measurement.
( c2 A8 C" k5 A, m3 C, S1 L( k904403 ALLEGRO_EDITOR DATABASE Allegro crashes when refreshing module |
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发表于 2012-2-21 14:58
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发表于 2012-3-8 15:09
