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我是新手，我用orcad画完原理图，drc检查没有错误，但就是不能生成网表，请教：谢谢！
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Loading... C:\Documents and Settings\Administrator.ASUSTEK-4295C4C\桌面\sch\allegro/pstchip.dat
' G1 b }: N% z; \9 x- ]( }* w3 P#72 ERROR(SPCODD-72): A mismatch in the number of sections occurred on line 1701 while parsing logical pins.
8 I. J5 t8 { s/ F( q8 Q To avoid such errors, use Part Developer instead of manually editing the library part definition
$ s! l! A; ]$ Y; S8 A; W ERROR(SPCODD-47): File ./allegro/pstchip.dat could not be loaded, and the packaging operation did not complete. Check the pxl.log file for the errors causing this situation and package the design again.
& L. I4 G6 P& f#53 ERROR(SPCODD-53): Packaging cannot be completed because packaging has encountered a null object ID. The design may not have been saved correctly. Save the schematic and rerun packaging.
, ~. J: N! T- ^" y1 x. X#21 Error [ALG0036] Unable to read logical netlist data. |
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发表于 2009-8-30 18:30
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