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Cadence SPB 16.5下载地址（Hotfix更新至044）
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Cadence最新版软件SPB 16.5及其Hotfix下载链接如下：
) T/ W# L# b3 C1 \http://dl.vmall.com/c0sfvdb4yy* i; n1 i% Q4 H
$ F' w& k: c7 d7 ~( ~Hotfix中只需要安装最新的版本即可。 S7 a N* L0 B- c1 d2 n' w
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DATE: 06-7-2013 HOTFIX VERSION: 0443 I8 F+ G7 `0 X
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" u1 {4 t0 A$ sCCRID PRODUCT PRODUCTLEVEL2 TITLE% A4 m4 n3 w8 q9 }( g4 o9 J
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) q! r6 {7 d* G: k1 R* I1055338 SIP_LAYOUT DRC_CONSTRAINTS Soldermask to Via drcs on bondfingers1 u& ^6 K: H1 @+ j4 u3 H8 }
1084716 ALLEGRO_EDITOR OTHER Getting an MPS error when updating CM from SigXplorer1 R6 k+ n; K1 _7 X# s+ h% T! B
1104145 ALLEGRO_EDITOR SCHEM_FTB User defined properties do not appear in PCB
1 N' m! g5 a4 F! a6 g- ?1106116 FLOWS PROJMGR view_pcb setting change was cleared by switching Flows in projmgr.2 D( G$ b4 o& A4 |6 N8 X# r9 Y9 C
1106900 CONCEPT_HDL COMP_BROWSER Component Browser performance utility should honor CPM directives for include and exclude PPT5 u/ t8 B# `9 N3 E- _7 ?8 i5 z
1110323 APD DXF_IF DXF out is offsetting square discrete pads.
5 f( w" }5 e' d1119007 CONCEPT_HDL CORE PDF Publish of schematic creates extremely large PDF files' T7 q( T: ^* i& w% P+ J& l
1121020 FSP MODEL_EDITOR Cut-Paste from Excel causes empty cell in Rule Editor
! W8 l& |" j W8 ?# m( B U1121353 ALLEGRO_EDITOR INTERACTIV Local env setting will change after saving and reopening.$ K9 p z9 a! L4 t
1122781 CONCEPT_HDL CORE cfg_package is generated for component cell automatically/ C) C) m2 Q2 R4 ~) ^- p& `
1122909 CONCEPT_HDL CORE changing version replicates data of first TOC on 2nd one
4 T a9 V# q. @3 x$ m1123581 ALLEGRO_EDITOR MANUFACT Dimension Line gets changed on board
" ~; {- h* N6 H8 V! i1124544 CONCEPT_HDL CORE About Search History of find with SPB16.5
$ _# S8 X2 L- Z" H* W3 h1125366 CONCEPT_HDL CORE DE-HDL craches during Import Physical if CM is open on Linux
: S8 p& A, q$ N+ n& y1125628 CONCEPT_HDL CORE Crash on doing save hierarchy
9 k/ X/ m8 ?( P/ T8 Z9 H1126182 ALLEGRO_EDITOR DRC_CONSTR Shape fillet DRC in same net thru via to thru via was removed after update DRC.
4 q3 |. }1 y* }/ ^- H1130945 SCM SCHGEN SCM Export Schematic does not copy all cells in the library: @' _% H' T p5 E- _) p
1131567 CONCEPT_HDL OTHER Lower case values for VHDL_MODE make genview use pin location to determen direction.3 V* S" s$ _3 O- {9 S
1131650 ALLEGRO_EDITOR PLOTTING PDF Publisher doesnot display few component defination properties in Property parameters; a5 W* g5 c3 R) Z
1131868 CONCEPT_HDL CONSTRAINT_MGR Many net-class constraints "fell off" the design after uprev and Import Design of GEP40 [2 P* j3 m6 a+ X
1132457 CONCEPT_HDL CORE The schematic never fully invokes and has connectivity errors.
$ Y; Z) S& a% M. g7 m) A" V$ ~; ?1132575 CONCEPT_HDL CORE 2 pin_name were displayed and overlapped by spin command.0 N; M4 M& K8 i3 Q9 i
1132638 ALLEGRO_EDITOR DFA 'dfa_update' crashes when running the utility on the attached foder.4 |3 |( t/ Y3 W" n- S0 _8 f. P
1133677 CONCEPT_HDL CORE Cant delete nor reset LOCATION prop in context of top
- c Q1 n( f0 ]5 f6 Q t1133791 CONCEPT_HDL CORE Cant do text justification on a single selected NOTE in Windows mode.
+ ~) @# N$ v4 v& @* G" I) H1134083 CONCEPT_HDL OTHER Published PDF file's hyperlinks do not work fine when user use double digits partitions for page Border.
5 n2 H2 \4 @$ M$ n) C1134761 CONCEPT_HDL CORE Why does Mouse Pointer/Tooltip display LOCATION instead of $LOCATION property6 E3 u) w! p& Z: Q: {6 n
1138586 ADW MIGRATION design migration does not create complete ptf file for hierarchical designs
# }, e9 D% V3 S1139376 CONCEPT_HDL CORE setting wire color to default creates new wire with higher thickness# S! D% D k" M& q* F7 Q; }/ P% S
1141300 CONCEPT_HDL CORE DE HDL hier_write save hierarchy log reports summarizes Successfully saved block x while block was skipped2 Y+ G3 E# J- a
1142876 ALLEGRO_EDITOR SHAPE No DRC error when airgap between place bounds exactly zero
; T( n3 ?) V+ d1142884 ALLEGRO_EDITOR OTHER Boolean type user defined property doesn't export to the PDF' `) | v* Q D
1145112 CONCEPT_HDL CORE Warning message: Connectivity MIGHT have changed
+ G& n$ j, w, i1145235 CONCEPT_HDL CONSTRAINT_MGR DEHDL CM gives error when trying to launch SigXP- N( }4 l' F) ^
1145253 CONCEPT_HDL CORE Component Browser adds properties in upper case
% V1 f0 M0 J! ], k0 F1145284 CONCEPT_HDL CORE Publish PDF crashes DE HDL4 y( o; c% i, \# Q2 A7 V
1145333 ALLEGRO_EDITOR SHAPE SHAPE boundary may not cross itself. Error cannot be fixed.3 y0 @0 E0 \4 w, P# q
1145856 ALLEGRO_EDITOR DRC_CONSTR DRC Line to Thru Pin appear while Fillet be added
/ L3 ]8 \* S* A0 [3 J1146287 PCB_LIBRARIAN CORE PDV expand pins and change origin sets coordinates for few pins wrong and places pins on top of each other after collaps
. O$ {' j* j. `4 k9 ^: x$ q( f1146728 F2B PACKAGERXL DCF with upper and lower case values on parts causes pxl to fail
7 p* W2 U( |6 g1147326 CONCEPT_HDL CORE HDL crashes when trying to reimport a block |
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发表于 2013-6-17 17:16
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