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高速数字信号设计和高速互连; V2 a# m# U- e& n" {
CHAPTER 1 Transmission Line Fundamentals.......................................... 1
4 n; j4 f2 L. d! W# |4 vBasic Electromagnetics.................................................................... 10 }* Q, u1 {# H" Q7 h& {$ @
Electromagnetics Field Theory................................................... 1, n, ^9 h! p! a3 j! c3 d$ T* ^6 e
Propagation of Plane Waves....................................................... 6
# T# F' D( {$ v# E& PTransmission Line Theory............................................................. 10
; l/ r) K7 P4 N* {+ aWave Equations on Lossless Transmission Lines.................... 11
9 R( w. J( r- i; Z5 h+ UImpedance, Reflection Coefficient, and Power Flow8 r5 T1 e( j0 N8 U
on a Lossless Transmission Line......................................... 14+ }) e% w, d9 l5 v! P
Traveling and Standing Waves on a Transmission Line ......... 16
: q- ]5 S* b u7 ]% ITransmission Line Structures ........................................................ 18
# u* S- e t( y: K: VStripline ..................................................................................... 19$ W* Y$ g' z* P( d( d5 u
Microstrip.................................................................................. 20) _1 H2 Q1 q( x; C3 j/ @8 N" m
Coplanar Waveguides ............................................................... 215 Y# o9 n) U9 V& o! l4 t
Novel Transmission Lines ........................................................ 229 ^( ^3 |+ v) T
References ...................................................................................... 26
$ ?9 _7 `! [/ s& y P* ]CHAPTER 2 PCB design for Signal Integrity........................................... 27
+ ^1 l. l2 U( w# S( ]Differential Signaling..................................................................... 273 @: i7 G8 F1 k! v) s
Impedance ................................................................................. 28+ c0 [% D9 {! M; X, s, H* U# u
Time Domain Analysis .................................................................. 31! A/ Q! t. ]$ O! ~0 u+ n3 l! V
Eye Diagram ............................................................................. 31" y% E6 T( s/ x8 C T9 z
Jitter........................................................................................... 33
. W# a) f* u D8 RFrequency Domain Analysis.......................................................... 42
$ }1 |/ K1 A' G+ U! y8 k+ sSpectral Content........................................................................ 429 U7 a0 a. `4 ^! ~/ T- e
Insertion Loss............................................................................ 44: w8 D- N6 Y7 t- a
Integrated Insertion Loss Noise................................................ 46
M" f5 L( p, ^0 \, [Return Loss ............................................................................... 49
3 ~" d* h, F. ACrosstalk.................................................................................... 51
8 K* X, j5 E: J7 w! mIntegrated Crosstalk .................................................................. 54
6 k8 w+ e! F% kSignal-to-Noise Ratio................................................................ 55$ N9 A/ \/ {% U* v" A# Z
Stack-Up Design ............................................................................ 58% c" M, o# ]5 c+ D* X
Impedance Target (Routing Impedance) .................................. 59 j" F, E& J) L: c
PCB Losses ............................................................................... 61
# M7 `& i& L: B8 f. j5 iDielectric Loss .......................................................................... 626 X0 m2 N. _/ t0 Q2 v# p6 a0 C6 g/ V
Conductor Loss ......................................................................... 65
# O$ E; H. d; R3 ZCrosstalk Mitigation through StackUp..................................... 68) o8 p E9 X, Q: D R
Dual Stripline ............................................................................ 73
. V& j9 k( c/ hv
F1 {+ T8 G) d7 N$ HDensely Broadside Coupled Dual Stripline.............................. 84
1 K+ z- B8 _9 w [ pVia Stub Mitigation .................................................................. 86
$ o: B2 ]5 g. M7 i1 APCB Layout Optimization ............................................................. 95/ o2 G5 ]5 A4 k& s! H
Length Matching....................................................................... 96
& s3 ^1 E M3 n. R% aFiber Weave Effect ................................................................... 998 {9 d1 y, C4 N& N
Crosstalk Reduction ................................................................ 101
- R1 S! x; S2 I5 M5 ~+ }" kNon-Ideal Return Path ............................................................ 107
5 W% k: G) z u; b9 Z2 PPower Integrity........................................................................ 1104 ~0 Q: O+ U. ~0 G# _
Repeaters ................................................................................. 111
$ z1 h u% W8 G. SReferences .................................................................................... 115
. t v) X1 K, A4 zCHAPTER 3 Channel Modeling and Simulation.................................... 117" k; r0 t3 ]. A# v
Transmission Lines ...................................................................... 117
/ j2 x+ F3 P2 @Causality.................................................................................. 117# |/ {: ?8 V+ ^/ m" U" k
Checking for Model Causality................................................ 1185 @7 \9 E1 J* t" i0 }
Causal Frequency-Dependent Model...................................... 120
V' I' l9 }, U! C, `Copper Surface Roughness..................................................... 121/ |" N5 n3 u7 m* b# F
Conductivity............................................................................ 126& [4 S. D+ [# F |- l
Environmental Impact............................................................. 127
& _: n7 d8 e" [( A, {Model Geometries................................................................... 130. o# s$ O3 a& P) g/ ? }3 B- R
Corner Models......................................................................... 133 [% e+ Y8 o0 h
Ideal Assumptions: Homogeneous Impedance....................... 137
( T% b9 _# @! x; t- f9 D( b# @# iIdeal Assumptions: Crosstalk Aggressors .............................. 137
# [3 G; o& |; V. y7 z( J, ~) ZTransmitters.................................................................................. 138
1 Z$ B2 W* ^& B YIBIS Models ............................................................................ 138 E1 s% N$ f2 t
Spice Voltage Source Model .................................................. 139
: R% J1 \8 P: l7 n: ?3D Modeling ................................................................................ 141
; M; N. q Y; b* BPorts/Terminals ....................................................................... 1421 [) B2 y4 { |1 A
Model Analysis Settings ......................................................... 144- d4 s5 ~ a3 B- w) J1 f
Plated-Through-Hole Via............................................................. 146 l, h3 T/ p4 W6 K5 A7 ~7 H+ N
Model Techniques................................................................... 1472 c( \0 c/ k1 R" F4 [0 O, F
Pre-Layout Approximation ..................................................... 148& e0 ~/ j+ P8 c& i: Z
Pre-Layout Modeling .............................................................. 148( |" D' \% u5 I; l$ N7 Q+ a0 W
Post-Layout ............................................................................. 1490 N3 {: i8 i! z: m
Connectors.................................................................................... 150
- t: K3 k! m2 aConnector Variability.............................................................. 150& \6 |9 H; i( `: R( A8 E7 f) R
Signal Selection....................................................................... 150% k# \0 n9 q; w5 z; E! Z
Separated Via Models............................................................. 152
; u, I% R. L2 @; SUnconnected Pins.................................................................... 153
- a; S1 g" s- |+ i7 K( `Physical Features..................................................................... 154
2 |: r6 h! v6 Z) v+ A1 {3 yDesign Optimization ............................................................... 1547 }6 V l/ w; h: U
Packages....................................................................................... 156( I5 b' B. N3 @. l* H
C4 Escape................................................................................ 158. t/ _; A' ?5 r4 j& X7 l$ Y' b7 A
vi Contents
7 ^* G1 z/ P# g; X- Y3 R1 ]9 dTransmission Line................................................................... 158$ p& A E) l! K t2 U- F
PTH Via .................................................................................. 160- ^$ d8 \/ }/ E: C9 }) L
BGA Model............................................................................. 160
, S, x. {7 n& p0 {0 \6 v8 wSignal Selection for 3D Package Structures........................... 1619 w! s4 k* G; ^* E# }* ^* a
References ....................................................................................161
& B1 O& k3 l7 P; I5 FCHAPTER 4 Link Circuits and Architecture .......................................... 163& d1 t! J F9 z
Types of Link Circuit Architectures............................................163
% I: C3 W- @6 h; |Embedded Clock Architecture................................................ 163
9 \ U( y/ u7 ?Forwarded Clock Architecture................................................ 164& C- I5 H, X, t2 N" t: A' l
Termination ..................................................................................165
2 L2 N8 X: p) JDC and AC Coupling.............................................................. 165
0 `4 ~( Q" L$ wTermination Type.................................................................... 1668 B0 \4 y0 _: F; v/ {" D" [
Termination Circuits ............................................................... 167% ?& M v+ b5 F# M/ C0 C
Termination Calibration Circuits............................................ 168
5 T) n2 g$ l. M& N3 TTermination Detection Circuits .............................................. 169- Y2 D; y6 }: j
Transmitter ...................................................................................170
! v$ ~2 f$ U& T! M& sTransmitter Equalization......................................................... 171! T( m( I( ~* v* X
Transmitter Data Path ............................................................. 173- H4 C8 R- H x. N
Current-Mode Driver .............................................................. 174; G7 O$ j. W8 n E' x& ^
Voltage-Mode Driver.............................................................. 177: s& s* i) V& k% ~
Receiver........................................................................................179
* O, x4 X* S: S. z$ dReceiver Equalization ............................................................. 180
% P6 F9 o' `: n QReceiver Data Path.................................................................. 182
7 I0 t8 `0 ^8 K8 P m5 d' l; `2 LContinuous-Time Linear Equalizer ........................................ 184
. a1 M {* d3 {2 `0 lDecision Feedback Equalizer.................................................. 1845 W4 o5 ^! d6 l `7 h
Data Sampler........................................................................... 186- u2 r+ L' U8 _0 S# C( ^8 _
Error Sampler.......................................................................... 186" G2 `1 q: }/ ~- `8 T! @2 S
Receiver Calibration ............................................................... 187
0 n+ w# H, r2 W5 o" u6 `6 RReceiver Adaptation................................................................ 1889 C7 V' R2 h1 M* d7 u: @" P
Clock and Data Recovery............................................................1909 n8 U/ Z) S) v. N
Clock and Data Recovery Loop ............................................. 191
" S5 V. I) i! fPhase Detectors....................................................................... 192
/ m1 |4 K) Z1 ]' V! j8 ?/ \Forwarded Clock Receiver ..........................................................195
# X% t; p( D+ s2 ], @Delay-Locked Loop ................................................................ 195
2 W# X( s9 j: c" Z2 Y' \: SDesign for Test/Manufacture.......................................................195
k1 y9 o8 ?$ i: JAnalog DFx Features .............................................................. 196
. ]) J1 [1 W6 @$ a0 |Digital DFx Features............................................................... 196
2 H9 m; Q/ B/ H. g0 cReferences ....................................................................................198& A* T0 C0 |! l
CHAPTER 5 Measurement and Data Acquisition Techniques............... 199
% i0 P' M6 f: g! }" s$ {; g, ^Digital Oscilloscope Measurement..............................................199
' V: ?' e6 R! s0 [" GReal-Time and Equivalent-Time Sampling Scopes ............... 199) ~" _9 |$ W7 C% G) F1 }8 s' N+ M
Contents vii
: q+ G5 O% a2 E! g. O( M# ?Bandwidth ............................................................................... 200" l7 _' Z6 Z6 Y# J5 s3 g. z
Scope Digital Filter Applications ........................................... 202
( s- }4 X- ^ w" x, y$ RTDR Measurements ..................................................................... 2042 l% Y& N7 |' v0 ^) C5 B3 z
De-skew Differential Pairs with TDR .................................... 205
6 P5 y9 A. r# |. n6 YChannel Characterization with TDR ...................................... 2074 n& C5 ?3 \* { [7 b; S) m3 [
Return Loss Measurement with TDR..................................... 209' r6 a4 `: S) f
Vector Network Analyzer Measurement..................................... 211
' z7 u7 |) v. H- |0 P# \What is VNA?......................................................................... 2115 \. o! T% F" a9 L# v7 w& G% C
VNA Error Sources and Calibration....................................... 2135 z: A- `9 \6 M$ T) C4 A8 E: b s
Full Two-Port SOLT Calibration Procedure .......................... 217/ V3 {5 k" t) h, m8 ]- c
Example of Measurement Using VNA................................... 217# K9 g& I% t7 a) b9 T
VNA Measurement Procedure................................................ 218
, z9 r& K, H7 P" ]References .................................................................................... 2199 \" U5 Y/ A, [: f
CHAPTER 6 Designing and Validating with Intel Processors............... 2215 k1 N% s! u! j3 b* U- u( _
Designing Systems with Intel Devices........................................ 221; }$ S9 e. F4 k5 W$ [3 A
Interconnect Model ................................................................. 221: O( u% I2 o6 w( x: _3 m, E
Equalization Models ............................................................... 223* g7 l; \% o+ H& @
Automatic Equalization Adaptation ....................................... 225
+ f) j. t, \! G4 c! Q# d2 NPerformance Analysis ............................................................. 2274 ?5 P0 k8 U ]) n5 X
Solution from Design of Experiments.................................... 2327 H$ p- z( M! q! Z1 l1 G" j
Solution from Typical Models................................................ 2344 n7 N* c- q# N7 O) _- e* Z( g
System Validation with Intel Devices ......................................... 2379 Y# D9 ?' D+ ?/ {
Power-on Preparations ............................................................ 237
7 w+ i% u) c; R" V" hTypes of I/O Design Validation ............................................. 238
n' e& Y2 n# {! ^4 Q; WSystem Margining Validation Overview................................ 239
: d. w/ C6 [% W7 GDDR System Margining Validation ....................................... 244
/ M; U2 q7 _( b) I0 q- FHigh-Speed Serial I/O Margining Validation ........................ 246
$ T7 |1 X' K2 E- g$ P. Z) h7 e% ~Low-Margin Debug Guidance ................................................ 2495 e6 K. [% D. ~+ C+ E
Summary ...................................................................................... 250
0 P6 c e! [; i; ~5 L( @References .................................................................................... 250
+ {$ d2 j3 V9 v$ u4 IIndex .............................................................................................................9 C+ z& u/ G# {
# k w) n3 w* r9 ?" b# Q* `% x9 c3 O
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