|
|
EDA365欢迎您！
您需要 登录 才可以下载或查看，没有帐号？注册
x
高速数字信号设计和高速互连
5 i( _! d9 r8 m+ pCHAPTER 1 Transmission Line Fundamentals.......................................... 1
8 v% R. c4 h7 CBasic Electromagnetics.................................................................... 1
0 Z. \' f% f6 NElectromagnetics Field Theory................................................... 1
; Q3 d0 x% ?$ O5 a6 GPropagation of Plane Waves....................................................... 6
6 r. G' y, r) \; v0 K/ _/ JTransmission Line Theory............................................................. 10
5 b( A9 J$ l2 a/ }- XWave Equations on Lossless Transmission Lines.................... 117 H$ Z0 l% f5 a, @7 L5 U6 V, w
Impedance, Reflection Coefficient, and Power Flow
& Z2 H6 | n. h1 N$ Lon a Lossless Transmission Line......................................... 148 Q2 g- T7 V( x5 o$ A
Traveling and Standing Waves on a Transmission Line ......... 16( e) c+ t7 U: M1 i5 G: z
Transmission Line Structures ........................................................ 18
6 }7 W) T4 L ^% vStripline ..................................................................................... 197 t+ I _& o! v3 U0 V0 N$ }
Microstrip.................................................................................. 20
( E+ p; ~/ V+ t5 x: o# [Coplanar Waveguides ............................................................... 214 W3 O; _" j% B& y5 w4 N" V
Novel Transmission Lines ........................................................ 22% p! S; d! n1 i5 ?) b
References ...................................................................................... 26$ O3 t# g5 b. i6 ~4 _
CHAPTER 2 PCB design for Signal Integrity........................................... 27 ^2 Z6 ]2 v9 l b5 T
Differential Signaling..................................................................... 27
! m& T8 Z% J5 a" IImpedance ................................................................................. 28* W" h( T; O! D7 x: A
Time Domain Analysis .................................................................. 31
7 c! d9 t' X4 g% XEye Diagram ............................................................................. 31
9 e# X" B) A5 Q7 v% u* D HJitter........................................................................................... 33
4 b6 T" U/ }; i. b' CFrequency Domain Analysis.......................................................... 42
$ M M* t3 ~6 }9 l o+ [4 U2 [Spectral Content........................................................................ 42
3 Q8 g- H) f8 C. l# ?: {Insertion Loss............................................................................ 443 g; x- ^. x. d* b& L- r
Integrated Insertion Loss Noise................................................ 46/ F- T/ [% w9 f& D7 {% z0 ^
Return Loss ............................................................................... 49
, ]- ^' J: X' s! ^$ I& K+ A, u! lCrosstalk.................................................................................... 51% y+ ^9 o3 C2 @" w q
Integrated Crosstalk .................................................................. 54% ]) c7 o( ?; \9 ?, D7 Z b2 D
Signal-to-Noise Ratio................................................................ 55, ?. q6 H* p4 H
Stack-Up Design ............................................................................ 58
e+ y# i: w# h4 v9 PImpedance Target (Routing Impedance) .................................. 59$ V; L; \# w. U5 e& F
PCB Losses ............................................................................... 61
+ J6 |. d& G5 E- v% ?Dielectric Loss .......................................................................... 62; V' x) q: Q! j! U
Conductor Loss ......................................................................... 65
+ m' ?5 S7 @- K7 ?' F8 p& F! U. dCrosstalk Mitigation through StackUp..................................... 68/ q6 W+ x. A% l% v6 j1 A+ g: i
Dual Stripline ............................................................................ 73+ c5 R/ s' U9 W" T8 s+ G6 b& m
v3 F6 b' E1 ^& B0 B8 F* z
Densely Broadside Coupled Dual Stripline.............................. 84- p# i6 t S3 l1 m$ }
Via Stub Mitigation .................................................................. 861 \0 [) b" }5 ?% p T o/ o
PCB Layout Optimization ............................................................. 95& J: h0 y- b% q9 ]
Length Matching....................................................................... 96$ F' s* Y: R& h9 G1 p; ^/ Z0 M9 V
Fiber Weave Effect ................................................................... 99 o7 X b2 Z# X" F2 }0 _
Crosstalk Reduction ................................................................ 101
' k7 R) D$ A' j$ Y" P- d% XNon-Ideal Return Path ............................................................ 107
) M: Z8 F1 N4 G3 k# c% kPower Integrity........................................................................ 110
; |5 Z: C( o/ B3 y0 x+ O( ^3 fRepeaters ................................................................................. 111
4 k# S! m# b6 a- V- lReferences .................................................................................... 115
9 O: k2 ^* v, h8 S1 s! lCHAPTER 3 Channel Modeling and Simulation.................................... 117( e) x9 }2 Y5 I6 Q5 [' p9 W* f- b5 E
Transmission Lines ...................................................................... 117+ [$ A0 @( c) w3 ]
Causality.................................................................................. 117; F3 |/ I/ S3 u
Checking for Model Causality................................................ 118
1 X3 z N: k! O o, MCausal Frequency-Dependent Model...................................... 120
+ q. L1 W2 o/ E- M( ]Copper Surface Roughness..................................................... 121
/ _/ Q. `4 v! |' Y4 K9 ~" ^Conductivity............................................................................ 126
: M4 I+ X/ ?2 J" C; i1 x8 L; ]Environmental Impact............................................................. 127$ z, V( k0 b% \ Z. [
Model Geometries................................................................... 130
- x s- K* N+ _; SCorner Models......................................................................... 133
1 s! N# T' S+ `* I+ WIdeal Assumptions: Homogeneous Impedance....................... 137
- f9 J6 ]: _5 g6 i" I, BIdeal Assumptions: Crosstalk Aggressors .............................. 137& D9 u0 v$ M; g2 i) V- k" z& Z. o6 |
Transmitters.................................................................................. 138
# e7 g6 `: Z' `/ U0 e7 K+ sIBIS Models ............................................................................ 138
+ F( [7 K& S( \" D, VSpice Voltage Source Model .................................................. 139# p% p# A& @# c4 @0 I* O* ?! h
3D Modeling ................................................................................ 141
! m i2 k, q* r7 n# B( S3 IPorts/Terminals ....................................................................... 142
E U2 S7 \; N$ CModel Analysis Settings ......................................................... 144
4 q) S0 g8 u* I: C5 n1 A, dPlated-Through-Hole Via............................................................. 146
2 }# H6 O: W, Z, V6 K9 b- GModel Techniques................................................................... 147! u: N8 `5 A* C r: G: c
Pre-Layout Approximation ..................................................... 148
- V9 F6 ?; {1 |7 r: h# E( EPre-Layout Modeling .............................................................. 148
7 P( {7 B E4 l8 g) I n! p: RPost-Layout ............................................................................. 149/ R5 I2 l3 c w7 S. m9 N
Connectors.................................................................................... 1500 n4 v5 r" J/ a4 S3 H
Connector Variability.............................................................. 150( b9 \" U a3 q$ H4 a. b
Signal Selection....................................................................... 150' U, h* U+ Z/ I
Separated Via Models............................................................. 1522 s; c) g- ~+ N
Unconnected Pins.................................................................... 153& Q9 M. u0 V5 u. l1 M6 {/ k- H
Physical Features..................................................................... 1549 ?& o# T& B1 ?0 @1 B6 Q9 B3 @- w
Design Optimization ............................................................... 154
. K( Q3 r: d' K) L/ e8 t% |Packages....................................................................................... 156
) \4 R* \. x9 G7 XC4 Escape................................................................................ 158! z. V( |- J- Q7 N
vi Contents
/ C* h0 ~3 P( i) k3 v/ r: s+ GTransmission Line................................................................... 158 `4 ~. y6 H8 k' v( {, B; A
PTH Via .................................................................................. 160 u: s) y% J! S0 y/ ?
BGA Model............................................................................. 1609 M; x. K& z O1 }- h
Signal Selection for 3D Package Structures........................... 161+ ?3 v, U9 e: z) j& R9 G
References ....................................................................................161
, n5 h2 M3 X2 q8 lCHAPTER 4 Link Circuits and Architecture .......................................... 163
+ ^& j5 A; ?9 @) ]5 M& o( MTypes of Link Circuit Architectures............................................163
! O4 v* i3 g/ b7 v! r, lEmbedded Clock Architecture................................................ 163
. |1 N# u+ s" i& Z3 }4 eForwarded Clock Architecture................................................ 164
0 [' _$ U- Z3 [, e+ U# |Termination ..................................................................................165, L {4 {7 |/ h6 z# ~
DC and AC Coupling.............................................................. 165! n9 D- ~( N/ B' `
Termination Type.................................................................... 166! | P) t; a6 B {" H) i2 {
Termination Circuits ............................................................... 1671 ~0 K7 y8 M1 ~3 }+ |& H$ D5 M
Termination Calibration Circuits............................................ 168
# I7 ~- y8 a- g/ MTermination Detection Circuits .............................................. 169
8 L5 `/ p+ Z" YTransmitter ...................................................................................170
% c5 z+ l' P/ x1 X2 J' j/ Y9 lTransmitter Equalization......................................................... 171. t i+ |4 Q! L4 M7 g+ Y. S$ Q
Transmitter Data Path ............................................................. 1735 b# P# ?! c4 H# M$ S$ R c3 D! j
Current-Mode Driver .............................................................. 174( x! a6 v" m2 E
Voltage-Mode Driver.............................................................. 177
7 t5 _& ~# g' wReceiver........................................................................................179; m0 C( o U% G& E1 b
Receiver Equalization ............................................................. 1807 `* P7 V6 [* H5 v/ T/ Z
Receiver Data Path.................................................................. 1821 X2 H: {/ n" U( J! B8 w, D
Continuous-Time Linear Equalizer ........................................ 1848 Q$ h+ K' D: @$ P
Decision Feedback Equalizer.................................................. 184. ?! N D7 J/ s' U
Data Sampler........................................................................... 186- o$ O c% Z: ^6 ?. l
Error Sampler.......................................................................... 186
8 f* w8 C9 m/ r3 U- wReceiver Calibration ............................................................... 187- \9 K' C `1 J9 w8 j3 m
Receiver Adaptation................................................................ 188- p U; c) n7 U1 n' R8 b: X
Clock and Data Recovery............................................................190, X0 v2 ~1 Q4 e) l: T
Clock and Data Recovery Loop ............................................. 1912 h" u! f+ U& e% _4 N& Q3 v9 r
Phase Detectors....................................................................... 1929 L- h- w8 M0 t9 R( D1 z
Forwarded Clock Receiver ..........................................................195% t, {; k q. r6 v+ i& f" x
Delay-Locked Loop ................................................................ 195: e8 h3 [ z' }, p. J
Design for Test/Manufacture.......................................................195
) d/ ^. n, p0 e, A4 U5 a7 XAnalog DFx Features .............................................................. 196$ f$ O. L, @" H/ v G, Y% x3 U
Digital DFx Features............................................................... 196( A7 H- k; W8 e6 d
References ....................................................................................198
; m' M4 y! _9 T j+ `CHAPTER 5 Measurement and Data Acquisition Techniques............... 199 Y& K3 Y- Z, h% a, ^ w1 k6 J5 l* M
Digital Oscilloscope Measurement..............................................199. k7 H5 T5 g7 M1 F/ [ T7 _% q
Real-Time and Equivalent-Time Sampling Scopes ............... 1993 A# j8 E: m% w3 c& I5 D
Contents vii8 X M6 y! _+ I, S: [# k' N
Bandwidth ............................................................................... 200
: ?$ s9 c5 u) k6 I7 G0 `* \Scope Digital Filter Applications ........................................... 2026 t; W& c8 `% ]& R6 {2 S$ a, G
TDR Measurements ..................................................................... 204
2 J, o. H8 V# l. rDe-skew Differential Pairs with TDR .................................... 205
- r% Y$ Y7 D+ D7 s/ }3 NChannel Characterization with TDR ...................................... 2078 u( @2 _" d9 |+ z% x. c
Return Loss Measurement with TDR..................................... 209
) p$ }% @/ ~/ R0 N1 d3 H6 |- P, iVector Network Analyzer Measurement..................................... 211$ E$ Y6 P7 F) [7 Z9 \0 g7 a
What is VNA?......................................................................... 2116 ~; X9 }0 ]4 a Q$ ~' i& k
VNA Error Sources and Calibration....................................... 2131 W3 O9 Z- a, B( {# W
Full Two-Port SOLT Calibration Procedure .......................... 217
5 V; X) a6 z2 O$ r$ HExample of Measurement Using VNA................................... 2172 \3 o! ~( S7 H+ A' J' B: F" x
VNA Measurement Procedure................................................ 218
6 z! g4 x7 }9 k) D2 lReferences .................................................................................... 219
1 B0 ?8 o. T) XCHAPTER 6 Designing and Validating with Intel Processors............... 221
- ]' p: I, e; ~5 g: }" D8 `Designing Systems with Intel Devices........................................ 221
1 b0 R% I0 u% l. G, S# o+ cInterconnect Model ................................................................. 221) o3 z/ F9 k; V
Equalization Models ............................................................... 2233 M! U) a$ f& J( {6 E, W& @. u2 P
Automatic Equalization Adaptation ....................................... 225, P4 f& b: _5 |1 }' H+ O
Performance Analysis ............................................................. 227* F& ?2 h4 l4 g7 ^' C$ y
Solution from Design of Experiments.................................... 232/ j. B# ~9 S! ]3 l: E1 c3 r
Solution from Typical Models................................................ 2340 _3 g1 t7 p8 b3 c( l: ]* E' [
System Validation with Intel Devices ......................................... 237
, b! t7 c9 v0 ~" VPower-on Preparations ............................................................ 237
9 p1 \( \5 S( M) ]0 G( {Types of I/O Design Validation ............................................. 238
+ k8 r8 T- S: L4 j1 {5 M* J* |System Margining Validation Overview................................ 239
4 v) h' j9 Z+ G* E& g) n0 Z3 x: UDDR System Margining Validation ....................................... 244
& d+ d" }% ^9 }) ], f7 V1 v& a' c4 LHigh-Speed Serial I/O Margining Validation ........................ 2462 `2 q6 ]) b4 e0 C% _# \( U
Low-Margin Debug Guidance ................................................ 2495 C' s% o) N- g+ B; m
Summary ...................................................................................... 250' n# [5 J! z7 C% B2 t* Q1 D2 h; n
References .................................................................................... 250( R U. r: \2 E- r4 C4 G! C
Index .............................................................................................................5 H8 Y1 D) D2 C
. [! M6 c6 R+ F; @% f
2 z2 X# [" V' p' W; f2 ~6 H! p9 Z6 y7 M) [0 R
|
|
/1 
发表于 2017-7-6 14:49
QQ好友和群
QQ空间
腾讯微博
腾讯朋友
微信
收藏
支持！
反对！
楼主
