[仿真讨论] SFP SFP+简介

Take a look at the XFP block digram below which shows the XFI electrical interface from an XFP module connecting to the the host device (ASIC or PHY chip) on left. The test-points (arrows marked A,B,B’,C,C’ & D) aren’t part of the physical interface but are markers that we can use to discuss the diagram. The four boxes on the right represent transmit and receive sub-assemblies, drivers and amps. You’ll find similar functional blocks in all optical transceivers.

Focus on the CDR (re-timer) blocks to the left of the XFP module. The first thing to note is that there are two re-timers, one for the transmit path and one for receive. The Receive Optical Sub Assembly (ROSA) translates the optical signal received from the fiber into an electrical signal. The signal is then boosted by the Post Amp, before being re-timed by the CDR block. The CDR block is acting solely as a re-timer here, reconditioning the signal received from the ROSA. The CDR re-transmits this signal using the XFI serial interface to the ASIC. Similarly the CDR on the XFP’s transmit path, receives a degraded signal from the ASIC and applies re-timing to prepare the electrical signal for optical conversion by the the Transmit Optical Sub Assembly (TOSA).

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XFP Block Digram – source: http://40gethernet.wordpress.com/

At the bottom of the diagram you’ll see the PMD, PMA and PCS markers showing you which PHY-layer sub-functions are mapped to each block. You should note that XFI is a ‘just’ a set of electrical requirements and tolerances expressed as compliance masks  in the XFP MSA Specification. The serial bit stream sent on the XFI interface is exactly the same 64b/66b encoded bit stream received on the wire. XFI isn’t ‘intelligent’ and the IEEE may no reference to XFI nor the SFI interface shown below.

SFP+ transceivers are cheaper, smaller and less power-hungry than XFP modules, and performs similar duties. How is this possible? The XFP MSA specification was agreed many years before SFP+, so Moores Law would definitely have helped to shrink the internal circuitry.

However the main reason for the size, power and cost improvements over XFP is that the SFP+ simply removes the CDR blocks from the module. Tada!! In a classic case of lazy engineering the SFP+ module makes the signal conditioning the responsibility of the upstream ASIC or signal conditioning chip.

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The SFI interface almost identical to the XFI interface you saw in the first diagram.  If you zoom into the PMA block now you’ll see that it has two new sub-functions. The signal conditioning responsibility has shifted from the SFP+ module to the device performing the PMA function. On the TX side, the signal needs pre-emphasis to prepare it for the transmission to the SFP+ module. On the RX side the signal needs serious clean-up as it now contains noise and jitter from the circuit and the optical channel.

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The SFP+ module performs less functions than the XFP module. The CDR blocks which were included in XFP module are discarded by the SFP+ which shifts the responsibility of signal conditioning to other components on the circuit board. The PMA sub-layer must take up the signal conditioning role, but needs to adopt different techniques as it working at the other end of the noisy circuit-board.

Pre-emphasis and Equalization are the tools employed at the PMA and they will be the subject of the next hardware post.

Overview of the XLPPI and using it with QSFP+ modules

In the initial development of the 100/40G Ethernet 802.3ba specification the intended interface to the optical module were the XLAUI and CAUI, which were derived from the 10Gbps XFI used on XFP transceivers. As with the XFI, both the XLAUI and CAUI require that the module perform retiming on both transmit and receive data. This retiming function is found in CFP modules but not in the popular QSFP+ module, which means that the XLAUI is not compatible with the quad 10Gbps interface of the QSFP+ module. To address the incompatibility between the XLAUI and the QSFP+ module the final version of the 802.3ba includes the description of the optional XLPPI (and CPPI) which allows direct connection to optics without the necessity of a re-timer function. This blog will look at the XLAUI and XLPPI with respect to their 10G predecessors (the XFI and SFI) and how the XLPPI is used with QSFP+ modules.

Background on the XFP/XFI and SFP+/SFI

The XFP was the first 10Gbps pluggable module with a serial interface called the XFI and in order to enable the connecting ASIC’s to support the 10Gbps serial XFI the XFP module supported a PMA function for retiming of both the transmit and receive data. By introducing the retiming function into the XFP, the signal eye at the test points B’ /B and C/C’ were optimised for the benefit of the host PMA SERDES at the expense of the cost and size of the XFP.  The diagram below shows the functional blocks of the XFP module, the location of the test points and how it connects to a Ethernet host.

The next step in 10G module evolution was to enhance the SFP module (used for 1Gbps Ethernet and 1-4Gbps FC) to support 10Gbps thus creating the SFP+. The SFP+ module does not have internal CDR retiming which means the high speed electrical characteristics are very different to the XFI and as such a new interface was created, the SFI. The SFI only species the electrical requirements at point B’/B’ and C/C’,  the PMA function in the Ethernet host to both operate with these signals and to compensate for any additional distortion created by the PCB traces between the ASIC and the SFP+ module.

In the transmit direction the SFI requirement for the signal eye at B’ are much greater than those for the XFI, thus the host PMA must implement pre-emphasis to compensate for the signal distortion due to the PCB traces. On the receive side the SFI output eye at point C is not only smaller than with the XFI but the incoming jitter is higher, in addition a new element needs to be taken care of which is the pulse width shrinkage due to pattern dependency (DDPWS). In order to reliably recover the data from the SFI the host PMA needs to implement signal equalization and for some applications (like 10GBase-LRM) EDC is required.

The above eye diagrams give a visual indication of the difference between the XFI and SFI; the actual parameters can be found the table at the end of the blog.

The XLPPI and how it compares with the XLAUI and CFP modules

The XLPPI stands for XL(40Gbps) Parallel Physical Interface and is defined in 802.3ba Annex 86a as the interface between the PMA and PMD functions (where as the XLAUI dissects the PMA). The XLPPI is derived from the SFI interface and places higher signal integrity requirements on the host PMA than the XFI based XLAUI.

The diagram above shows the differences between how a QSFP+ module uses the XLPPI versus a CFP module, which uses the XLAUI. The diagram also shows the 802.3ba test points which use a different naming convention than the SFF XFP and SFP+ specifications. As with the XFI and SFI the main difference is the increased signal integrity requirements for the host PMA and PCB signal traces.

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Using the XLPPI with QSFP+ modules

The XLPPI interface is defined as being AC coupled on the host system, since the signals are running at 10Gbps (max 5GHz) it normal to route the traces as strip line on the top layer avoiding vias. When laying out the traces it is important to get both the impedance and differential trace length as close as possible to their target values. The impedance of the TXD and RXD pairs is 100Ω, with a termination mismatch of +/-5% at 1MHz; the closer your trace impedance is to 100Ω the more margin you’ll have for the modules and ASIC’s to vary their termination. The same applies for the length of the +ve and –ve traces, these need to be as close in length as possible since as any difference will eat away at the signal eye (note the effect of DDPWS in reducing the UI). However don’t spend time trying to match the length of the four TXD+/- or RXD+/- pairs, this is not necessary as the MLD function takes care of this.

Currently QSFP+ modules support 40GBase-CR4 (both passive and active) and 40GBase-SR4 (either AOC or using the MPO/MTP®connector). However in June 2010 Colorchip announced their QSFP+ based 40GBase-LR4 module which is stated to be available in 2011, thus a system using the XLPPI/QSFP+ interface will soon be able to support the complete range of 40gBase-CR4, SR4 & LR4 – Excellent!

In addition to straight 40G interfaces there are also 4:1 hydra cables which have a QSFP+ at one end and four SFP+ cables at the other, these cables are typically direct attach copper and are used for aggregating servers to a top of rack switch. When being used for this application the high speed interface of the QSFP+ needs to conform to the SFI specification rather than the 802.3ba XLPPI.

Whilst the future trend is to adopt the XLPPI the  XLAUI will probably still survive for special telecom orientated modules like SEI’s 40Km 40GBase-LR4 CFP (more like a 40GBase-ER4), or any future 40GBase-FR module.

Short note on the CPPI and CXP

The CPPI is the equivalent interface to the XLPPI for 100G, currently it is only usable with the CXP module and it’s not clear if the CXP module (defined initially for infiniband) will be used much for 100GigE due to concerns of reach and reliability of the MPO connector. The new 10x10MSA is currently defined as using CAUI though in the future this may move to CPPI for cost reduction. In the future 100G modules with a 4x28Gbps (CEI-28) interface will appear using a CFP2 format (similar in size to the X2 module).

Summary of electrical parameters

The above table captures only a small portion of the high speed interface requirements, when designing a board it is important to get the complete specification. For SFI and XFI the relevant specifications can be downloaded free at http://www.sffcommittee.org whilst the XLAUI and XLPPI specification is included in the (also free) 802.3ba specifications athttp://standards.ieee.org/about/get/802/802.3.html .

The 40G Ethernet Resource Center  |( N( B' g1 L
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http://twitter.com/40GEthernet

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Overview of TLA’s

CAUI : 100Gbps (C) Attachment Unit Interface# A( j9 Z% F7 A; U
CPPI : 100Gbps (C) Parallel Physical Interface* |2 @% N& I4 |( l) @% v
EDC : Electronic Dispersion Compensation& t# [1 u$ i; X; U' t
DDPWS : Data Dependant Pulse Width Shrinkage (in UI)" @) Q0 p% S* {% U
SFI : Small form Factor Interface
8 k$ n3 F7 L7 t% ?! d6 g% GSFP : Small form Factor Pluggable
' I7 A( r" p7 r, W  N; IUI : Unit interval of a bit period, for all the interface above this is 96.97ps (10.3125Gbps)
8 G! \! ^3 O% S1 z6 RXFI : 10Gbps(X) form Factor Interface  }. I2 T9 w; N$ V! ~9 t' |2 d/ o
XFP : 10Gbps(X) form Factor Pluggable
+ f# _; J' Q: s. a% C: DXLAUI : 40Gbps (XL) Attachment Unit Interface7 S; h, h% m  ?: r
XLPPI : 40Gbps (XL) Parallel Physical Interface

XFI/SFI/10G-KR Transformation

XFI <=> SFI

XFI <=> 10G-KR

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从产品兼容性方面考虑, SFP+和XFP,XENPAK能正常通信, 这样就解决了SFP+和XFP/XENPAK共存的问题。

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当然10G已然即将成为历史。