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通过Verilog HDL用数码管设计了一个40s的倒计时，想在10s之后加上一个蜂鸣器，无奈本人初学FPGA，苦试多次无果，故来此请教各位大神，能帮我在40s倒计时上面加上一个蜂鸣器吗，跪求了，谢谢！！！！module led_rxd(clk,rst_n,SOS_En_Sig,led,led_seg);
$ M- x( ~" _# e* B9 ?input clk,rst_n;3 N0 E, u3 `' D. K
output [7:0]led;
, j& [) y, z1 G# Ioutput [5:0]led_seg;% C' w6 ?, V0 l1 B
output SOS_En_Sig;4 R6 Z8 M8 E2 G1 E: f0 _7 Z
parameter seg_num0=8'hc0,
& S7 S6 H3 D/ t! M5 [* X seg_num1=8'hf9,+ O8 p0 Q& b0 J3 [$ J% H
seg_num2=8'ha4,* r5 f% T1 B8 P0 [* E$ w
seg_num3=8'hb0,$ S* E V, k5 j- J( t; h
seg_num4=8'h99,
- ?, f% S w3 v2 V X+ r4 A seg_num5=8'h92,6 ?+ t: u8 P: L; D Y
seg_num6=8'h82,
* v4 Y4 ]. o( r+ Q; ]6 H seg_num7=8'hf8,
8 Z- I7 [! w" I9 r/ H, s seg_num8=8'h80,3 p& S7 b2 l# y4 r: @& o# m
seg_num9=8'h90;) W% R' H/ [8 @$ x
parameter seg_en0=6'b111110,3 e a( _3 ~! S6 ~0 n9 Y2 W8 H4 X
seg_en1=6'b111101,; @8 \$ i# P o9 c2 A" ]# A
seg_en2=6'b111011,
$ H. g& c! G9 d0 L seg_en3=6'b110111,8 ?* P) {9 o& E& \% T& }7 k
seg_en4=6'b101111,
$ T9 _7 z. v; ~ seg_en5=6'b011111;
' {% A( ^& s# k! @0 k; Ireg [26:0]count;# s* s1 L7 B2 R
reg [3:0] count1;
9 w2 U( `5 b; g$ P- u. j* y vreg [3:0] count2;: y: e+ }% I9 A
reg [7:0] led_reg;1 |3 b1 L' P" m9 q
reg [5:0] led_seg_reg;) e6 P0 q3 O' G
always@(posedge clk or negedge rst_n)* U! d2 K# J$ v* M
if(!rst_n) count<=27'd0;
/ U/ c8 ~; q: {& Gelse if(count==27'd49_999_999) count<=27'd0;
4 z' r5 r" P' Z* _* celse count<=count+1'b1;; ]' n- U, i @3 c5 X1 r
wire clk_div=(count==27'd49_999_999);
9 M6 H2 S3 C" z0 m: Calways@(posedge clk_div or negedge rst_n)* J& L2 h- V/ R w/ z5 S9 D
if(!rst_n), h; L* S% E( B; r1 U. L* S$ H1 d5 x- P
begin
3 [+ Y! s0 ^) x4 qcount1<=4'd0;+ O' H0 ?* s; i, s* V
count2<=4'd4;. k: s( |7 }3 D2 l8 d* a
end
; Z2 k5 s+ q, v1 c: X8 delse if((count1==4'd0)&&(count2==4'd0))* |$ U! h0 L: E" E/ Z! _+ T" ~, t
begin
7 n* w( r& j- u0 {9 P+ n3 i& Wcount1<=4'd0; ( i3 X6 G. Q3 y4 M% g/ G, m
count2<=4'd4;
+ v) p; Z. J; S9 ]end
o; y+ B- l% P/ oelse if(count1==4'd0)
; V! T# y/ Q& V/ V3 o: N3 tbegin0 q+ ~4 {9 G; [2 T/ H
count2<= count2-1'b1;
1 @* |% I- r1 S3 x% l( N$ Qcount1<=4'd9;" o" D( L: b R- |
end4 ?1 `! d9 }4 h% J
else count1<=count1-1'b1;% E3 E2 ]9 X, v1 [2 ]9 w- s8 ^2 l
reg [26:0]count_1ms;//" q1 T) a3 o9 k* x. N, j
always@(posedge clk or negedge rst_n)
$ n, Y1 f5 f2 K5 R& G0 {if(!rst_n) count_1ms<=27'd0;
. K$ c; A) W- b; U' kelse if(count_1ms==27'd49_999) count_1ms<=27'd0;
) _/ }5 Y+ r5 v: V5 A. @else count_1ms<=count_1ms+1'b1;% T% Q( V" ?4 {) X6 t9 R# A
wire clk_dis=(count_1ms==27'd49_999);//
7 v6 N* N9 a5 D7 ^# |//
* O3 {; R5 a- T/ J: _reg [1:0]state;
9 U* ?# U" `8 j. j0 ?always@(posedge clk_dis or negedge rst_n)! w0 ` L, a8 k/ d
if(!rst_n)
0 b% s* A) L7 i9 Ibegin
# _. e- F5 H. L( A6 `1 z$ jled_reg<=8'hff;
* f# y1 u* v9 C1 aled_seg_reg<=6'b111111;
: z( W! U4 [ E& Q9 ystate<=2'b00;) k3 _: X0 y0 Y
end, V: W2 U8 E5 K# G: t% k
else if(state==2'b00) 4 S& `0 c; T" j( D, P1 l0 g8 R
begin4 C: s# ~2 j6 `3 Z* D: O
state<=2'b01;
; L- T: N8 m, G h$ G' Rled_seg_reg<=6'b111101;/ D' I8 n- W. H4 w( a, _
case(count2); a/ t1 P( ?# ?# a0 y6 x: ^
4'd0: led_reg<=seg_num0;
% | B- f9 j$ v" i! F4'd1: led_reg<=seg_num1; t/ f- G* K( S( N+ }7 w, g
4'd2:led_reg<=seg_num2; 2 ~4 x% J6 x2 x: e( ?3 D* F# H
4'd3: led_reg<=seg_num3;
9 B9 K; v4 U' j; N! v4'd4: led_reg<=seg_num4;
' x- q' r1 w, {$ ]: E2 F8 n! S4'd5: led_reg<=seg_num5;
. s. g% |7 y( G# ?1 @3 [4'd6: led_reg<=seg_num6;
; ~% s5 Z& y1 x% M' ?- O- g+ }4'd7: led_reg<=seg_num7;
# I/ L# b. f* b0 k. o w+ H( M; |4'd8: led_reg<=seg_num8;
* p8 c% b' F9 ?6 D$ A, Q6 J4'd9: led_reg<=seg_num9; - ^2 h3 k% ^5 W7 W, i: Q
default: led_reg<=seg_num0; 6 a4 w' p9 Z1 E( H f/ ^6 F" d' }( ~, M
endcase
. {3 v) K+ ?# W/ Bend
/ G2 m5 O3 ]9 Gelse if(state==2'b01)
5 Y* {+ h- l2 |2 ]begin
! Z E7 k2 V( L% @9 |4 l- F& Vstate<=2'b00;5 `7 H* N8 K' p% E4 \
led_seg_reg<=6'b111110;
' ?' q5 }1 E4 k3 ? J; j* ^case(count1)4 R8 N" V& K. O# k7 I" g, w2 {7 @4 N- a
4'd0:led_reg<=seg_num0;
2 i3 {/ m: S( k" n% B3 h9 `: p4'd1:led_reg<=seg_num1;
' z6 ? O% _3 O4 B4'd2:led_reg<=seg_num2;
$ s) t6 Q# k& j5 [& A6 ], F4'd3:led_reg<=seg_num3;) r$ ]" T* h! `% m( D V
4'd4:led_reg<=seg_num4;3 M$ s7 j7 y8 P/ c- G
4'd5:led_reg<=seg_num5;7 Q q' A! _" P6 i
4'd6:led_reg<=seg_num6;
( D! g9 y) L# d4'd7:led_reg<=seg_num7;2 i- x' h D+ Q3 E4 u. `# }0 t
4'd8:led_reg<=seg_num8;
% W, {+ N2 w6 N- d4'd9:led_reg<=seg_num9;9 n; P- {1 m' D: K
default:led_reg<=seg_num0;% r0 t2 _- ?1 V/ t
endcase M+ z1 O" I z/ T: T
end
9 @" ]! m/ ~6 K; Q- Greg isEn;. r5 e8 {8 x0 ^: {
always@(posedge clk or negedge rst_n)( g, a( v V" K s: ^; U9 F
if(!rst_n). }. r5 C. q9 s% `* k3 A
begin6 N% Q) F( m3 O- c
isEn<=1'b0;
6 y; w4 _( s& r2 ?4 ~' ^- g" Dend
( A2 Z" H8 Q4 v+ N$ A! q5 Delse
1 w8 i, u0 i5 v& Y2 F$ }begin$ W7 a3 L$ c9 g$ V4 A/ r- `
isEn<=1'b1;
2 g0 A: g5 d5 p9 Qend, H4 N3 T; t' i) u h* n3 E0 _- o
assign led=led_reg;& S% {" {$ P m8 w
assign led_seg=led_seg_reg;
1 y. r& }9 I3 h8 Z- N* v% @' Passign SOS_En_Sig=isEn;
7 ^ F( {* u) ~# qendmodule
3 \( K1 Y# `3 d, T) Q7 p! X8 H u6 H" M
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发表于 2016-4-13 18:01
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