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标题: 数码管倒计时和蜂鸣器同步的问题，麻烦大神们进来看看，指教一二。 [打印本页]
作者: zhangsong123    时间: 2016-4-13 18:01
标题: 数码管倒计时和蜂鸣器同步的问题，麻烦大神们进来看看，指教一二。
通过Verilog HDL用数码管设计了一个40s的倒计时，想在10s之后加上一个蜂鸣器，无奈本人初学FPGA，苦试多次无果，故来此请教各位大神，能帮我在40s倒计时上面加上一个蜂鸣器吗，跪求了，谢谢！！！！module led_rxd(clk,rst_n,SOS_En_Sig,led,led_seg);
3 T7 {+ }  F7 O2 d" ?9 u4 _5 ^* ginput clk,rst_n;
  Y1 q( m1 R9 w) M7 ioutput [7:0]led;" w' [' u2 i) M- r
output [5:0]led_seg;
" E0 n1 F2 s# d2 K2 Q1 qoutput SOS_En_Sig;
' G. P# }% w# u+ L# Uparameter seg_num0=8'hc0,
& V- u* g" [. s- B          seg_num1=8'hf9,
0 B' V# P( X; ~0 R; {! ~+ `! L. G/ W             seg_num2=8'ha4,
( h# B* H1 ^( |: b; E: k, z2 N             seg_num3=8'hb0,
* D% B- f% ~% f% Q& B4 k2 j             seg_num4=8'h99,5 H4 F1 Q/ L* i, C$ ~6 b
             seg_num5=8'h92,: ~4 \7 |1 X* k0 h: t1 j" p
             seg_num6=8'h82,. m% b# L) s9 q$ Q
             seg_num7=8'hf8,
) _/ u& L7 h' x- c( p             seg_num8=8'h80,1 x: x) u: @9 ?5 L
             seg_num9=8'h90;% n; F; |$ k  m4 `0 S) a
parameter seg_en0=6'b111110,5 g2 v% Q  c) k( M5 u. x1 _
          seg_en1=6'b111101,
' Y: T4 f$ ^5 ]% E: e             seg_en2=6'b111011,
+ L& U3 _. a% H: f5 s6 J             seg_en3=6'b110111,
& ~1 P0 i6 A( L  _  X1 u2 F* S: Q             seg_en4=6'b101111,
6 f4 p- O; b' [& Q- v             seg_en5=6'b011111;7 T3 ~$ [% P  s5 Z1 V: Q
reg [26:0]count;4 ~8 d% m# ]7 ?
reg [3:0] count1;
5 Y+ I/ t+ u. e! Lreg [3:0] count2;
# ]- V: q# i% G" z0 Jreg [7:0] led_reg;
3 W" u1 Y  U  z3 M& dreg [5:0] led_seg_reg;6 m8 D; S3 C1 ^# t8 u' O4 M  n
always@(posedge clk or negedge rst_n)
! a0 l+ M& J0 p, ~9 `; o0 v9 Gif(!rst_n) count<=27'd0;# t" H. m3 _2 \, t5 [0 _9 k+ Y
else if(count==27'd49_999_999) count<=27'd0;
. q* O. t3 Z8 a/ jelse count<=count+1'b1;& ^9 Z: l. Q* L- e3 x% }* v$ c
wire clk_div=(count==27'd49_999_999);
( i& W( H! ^# A$ q! aalways@(posedge clk_div or negedge rst_n)
8 P% i  R! X) v  Uif(!rst_n)
4 _0 E( I- o0 D' l! Nbegin
7 C; B! k, _% v8 w: v8 s" ncount1<=4'd0;
) y& l% Q! S8 q% N& `8 \4 ccount2<=4'd4;
; I0 \% D8 E: dend
; d3 f6 x5 t7 k/ H! uelse if((count1==4'd0)&&(count2==4'd0))9 b1 K9 W$ G. Z. ~, I
begin
; N* z# C" T3 u9 {count1<=4'd0;
; `8 T& x" o' s8 ^count2<=4'd4;
9 q: E/ X- x! e9 Y) qend+ l' J; ?- I1 Z
else if(count1==4'd0)& R( p2 u( ~/ _& ~" [
begin- {9 |% s' S$ m, x( i6 W
count2<= count2-1'b1;. i; J7 G5 G4 F: ]& \% @
count1<=4'd9;- a) y. D# O+ K3 J- R, c) ^( ^
end
5 X3 d2 `. c7 q/ U2 w  X' `else count1<=count1-1'b1;/ X" G8 y* C  V  o' U
reg [26:0]count_1ms;//; Z& a% M4 i! ^5 @0 J6 i* v
always@(posedge clk or negedge rst_n)  a. q8 i+ ?+ k( @8 q1 w
if(!rst_n) count_1ms<=27'd0;  
5 G9 G9 Y+ X( j% [; F7 {else if(count_1ms==27'd49_999) count_1ms<=27'd0;" h; T( u" _2 @7 Y9 R
else count_1ms<=count_1ms+1'b1;
: z" q6 D4 c! e$ R! Uwire clk_dis=(count_1ms==27'd49_999);//" i3 Z4 I0 A' Q( {- i
//
! V( n& H- u! w2 ^) breg [1:0]state;
) P3 k* C7 z* p, N9 Halways@(posedge clk_dis or negedge rst_n)
9 j5 p1 T% Q4 K: ~if(!rst_n)6 K9 _  I6 Q3 c% w2 }
begin" d' h: Z! b% G6 C: L2 }
led_reg<=8'hff;5 F3 M5 y* I, Q/ M+ d8 _
led_seg_reg<=6'b111111;% ]! L  E3 O, {
state<=2'b00;, q4 G9 [+ U  b" J- F
end; t' O9 j+ C$ z0 S7 r
else if(state==2'b00) 1 O& k' A9 c5 i- z" V' o
begin
, `5 X1 T5 T& w. o4 L* }0 Ustate<=2'b01;  d$ m0 ^; B+ R( k+ X* ^9 r4 C; c
led_seg_reg<=6'b111101;
8 p  k; M, H# |* k6 R; m% ^, Ncase(count2)
: D9 G2 i$ i4 n/ R9 k: w& G( A4'd0: led_reg<=seg_num0;  
. }& q+ ]3 D( G0 b" B4'd1: led_reg<=seg_num1;  
0 C, n$ v  a' q8 R5 C+ e) z4'd2:led_reg<=seg_num2; ; N: O4 n. R4 |1 E/ O
4'd3: led_reg<=seg_num3;  
- P, u: K5 C2 X' C# J$ y4'd4: led_reg<=seg_num4;  
) S) T3 u3 l- |8 j; ~8 e4'd5: led_reg<=seg_num5;  4 I4 C+ c2 G! p% G2 h
4'd6: led_reg<=seg_num6;  
$ e1 i- i  K, `/ G7 f" R4'd7: led_reg<=seg_num7;  
& @$ E1 Y( ^9 o4'd8: led_reg<=seg_num8;   - `4 Y) `; B9 m( N/ ^. ^
4'd9: led_reg<=seg_num9;  . o% _, r8 I% A; a( d- ^9 w! I
default: led_reg<=seg_num0;  5 J, R+ r0 l0 o. u- H
endcase# i' ~" K' j+ L+ Y3 f/ Q
end
8 M  s0 s" t8 }. belse if(state==2'b01)' v9 b. e+ o; V; L  j
begin + _$ o8 L/ B. X6 P
state<=2'b00;
" l) d9 ?% |" rled_seg_reg<=6'b111110;
) A' A8 H) x  c5 A; y5 Scase(count1)/ `: x' q' j! g& G9 K
4'd0:led_reg<=seg_num0;$ W) y; z' k1 w6 h' P6 K
4'd1:led_reg<=seg_num1;
  i1 @4 K& W: r4'd2:led_reg<=seg_num2;- M# N' u8 U1 }$ P; g3 m# V
4'd3:led_reg<=seg_num3;
: Q- l7 G/ y0 J3 w! c8 p4'd4:led_reg<=seg_num4;: o# P- N3 Y9 `0 b/ x
4'd5:led_reg<=seg_num5;% Z' t4 p* ~- ]' _
4'd6:led_reg<=seg_num6;4 o  ^0 C9 O- V% s: w4 b
4'd7:led_reg<=seg_num7;
* Y9 J( w+ l6 _( e1 o2 r. V5 }; ^4'd8:led_reg<=seg_num8;0 Q0 m, w2 n! v
4'd9:led_reg<=seg_num9;
2 c, H9 i5 P& Z2 U' \default:led_reg<=seg_num0;+ h. L+ T- s8 z6 q: i
endcase4 V/ ^% V) b& W- Q* d; d+ F6 C! a
end# {4 [! X5 d" ^+ M) ?) ]
reg isEn;
. Y2 y# Q+ i' F4 Yalways@(posedge clk or negedge rst_n)9 Q$ H0 P5 ]$ ]: X3 ^$ S8 P7 c
if(!rst_n)
( a( ~0 \8 w% h, N5 Q9 P! D& }begin' I  r* _! {# E
isEn<=1'b0;
2 Q* G) Y7 m1 M" tend8 S. w  F9 h3 d" n. q3 \* d6 o5 Z
else" _, s. U7 {6 n) `0 C! T
begin
2 c! b" G% F" A1 a$ m3 DisEn<=1'b1;
, _! G- o: _% j7 A$ Uend
' w+ h+ }  q: V7 ?1 r: g+ e# B4 I! Q$ |assign led=led_reg;
1 o# I8 ?: l4 @% m# E( u, W% Eassign led_seg=led_seg_reg;6 R3 }. S& _1 Z2 o7 A
assign SOS_En_Sig=isEn;& k- D6 j% N6 ]9 Y  y- G$ T
endmodule
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