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本帖最后由 Csec 于 2014-4-28 11:04 编辑
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- b- @! g$ u$ u+ V% H7 q$ z( Mhttp://sw.cadence.com/P/download ... e4d05&file=.exe& z# b5 N% w! I
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DATE: 04-25-2014 HOTFIX VERSION: 027
, W# i) F; z& U" n8 A9 g9 {% C$ F O: k===================================================================================================================================
7 M8 R# D$ B9 _% ACCRID PRODUCT PRODUCTLEVEL2 TITLE; z& S& ]1 ~; h% y" H
===================================================================================================================================
+ x$ [4 p. X3 R: `1 T# E' @0 {6 p. Z308701 CONSTRAINT_MGR OTHER Needs to delete user defined schedule in CM
$ |: y% c" f2 {% i0 m0 {+ c' U481674 ALLEGRO_EDITOR PADS_IN No board file saved from PADS_in- V3 F# y( k! K6 A- r, @6 @/ y
982929 ALLEGRO_EDITOR EDIT_ETCH can't route on NC pin and other that are not pin.% [, n: o+ q" K5 ^/ k
1012783 FSP OTHER Need Undo Command in FSP9 ~) F& R( ?# |/ a: H0 `2 h
1017381 ALLEGRO_EDITOR DRC_CONSTR Need Dynamic Phase to be able to measure back to the Drive Pins.; j& ] p1 G0 W6 d! x# K, @; l
1072673 PCB_LIBRARIAN GRAPHICAL_EDITOR Copy paste goes offgrid if mouse is moved
# W5 e' T3 {& H+ e) q1073231 CONCEPT_HDL CORE Copy-paste of signal names goes off-grid in Windows mode.
1 J) T/ T% g: \( q$ C- B1105371 CONCEPT_HDL INTERFACE_DESIGN Strange behavior when shorting two Net groups
6 @1 h! s, F W& W# a7 P, R1116498 CIS LINK_DATABASE_PA link database with modified part results in Capture crash
3 s* ]9 V8 s( D/ [6 d4 R5 P1118632 ALLEGRO_EDITOR GRAPHICS Text display refresh issue while in Edit > text command
4 P9 o! J9 ~2 T, H5 x1155821 SIG_INTEGRITY LIBRARY Xnet are not recalculated correctly when model is changed on the Series switch part defined as discrete with Espice mode8 {: r- A" p( z# l1 `' `7 N2 e
1157372 ALLEGRO_EDITOR DRC_CONSTR Dynamic phase for Diff Pairs not reporting back to Driver pin if pin escapes present7 [' q6 F8 i4 i, w2 d) M$ K: w
1171951 ALLEGRO_EDITOR CREATE_SYM Jumper has a limited of count when it add to list./ _( T3 ]1 |& X% S
1180871 CAPTURE LIBRARY_EDITOR Copied parts don't retain pin name and pin number settings
# X+ V1 B7 R" l, q3 n1185575 SIP_LAYOUT DIE_STACK_EDITOR Updating symbols causes the graphics for the Assy layer to change from Bottom to Top.- f0 C3 X' A- m o& F+ I$ X& S
1185772 PCB_LIBRARIAN CORE VALID_PACK_TYPE warning when cell was opened in PDV
% X/ r! C5 h% ?6 x: W1192377 CAPTURE SCHEMATIC_EDITOR Pin name/number position is incorrect on schematic if it is changed for a rotated part.
+ r0 c) C/ y/ g6 J) _4 z: k8 r @# f1202654 ALLEGRO_EDITOR GRAPHICS Zoom using mouse wheel shall maintain the center co-ordinates$ H0 T# W9 j) ]
1208031 ALLEGRO_EDITOR INTERACTIV Snap to Pin for via during Copy command do not snap to connect point everytime" [. e6 V! t0 s, V
1208478 PSPICE PROBE Attached project gives overflow error with marching ON.
1 ?% Q( J/ s- h! o8 r8 M1 b2 r6 B1210015 CONCEPT_HDL CORE The value of $PN should be not turned on spin or rotate symbol$ Q9 W: V2 m+ j! w$ n
1210425 CONCEPT_HDL CORE When moving a circuit tool reports that connectivity has changed
( n) Y9 n: v l; q# K1215858 ALLEGRO_EDITOR SHAPE Force update does not void cline with the shape. z' ]! q& ~% u) O% ^) [5 m& ?# N( o
1215906 ALLEGRO_EDITOR SHAPE Dynamic shape fill smooth failed when copying to other layers
8 p) e$ x0 w, I9 \6 Y$ ^1216358 CONCEPT_HDL CORE Can we improve our export BOM function to check if user did export physical function before exporting BOM?
# s1 J V% K+ D9 y4 L z! `6 f1217364 CONCEPT_HDL OTHER Netlist reports fail because error: GScald failed.
9 E0 y2 F$ B: x' ^( c% K0 r1217529 CONCEPT_HDL CORE ADW checks do not catch single quotes in PTF values( k3 T9 W7 l5 X4 ~; O) H
1217556 F2B PACKAGERXL signal name change not sent to Allegro after packaging
J3 ]* y& Y9 S- p1219283 ALLEGRO_EDITOR DRC_CONSTR Show constraint is inconsistent when displaying region information( L) h( |/ B; u9 I A. }
1220078 F2B PACKAGERXL Export Physical crashes when ALL the part pins are added5 R+ c% W1 g q+ S4 c+ `
1220393 CONSTRAINT_MGR CONCEPT_HDL HDL import physical from board file will annotate CM data back to HDL which includes cross-section thickness.
0 b" S4 N! e2 r* K1220540 ALLEGRO_EDITOR GRAPHICS Need an option to see the pads inside the internal plane shapes0 B* j4 r# H' R5 C0 p# `
1220936 CONCEPT_HDL CORE About crash by vpadd/vpdelete command on Linux
) }* V7 R A% x- p8 a( M" e* h1 v1221059 ALLEGRO_EDITOR DRC_CONSTR Get a "Shape to Thru Via Spacing" DRC error only the first time when the shape is manually voided.& ]; H) N) K/ t" `" m4 O
1221182 ADW TDA Team Design with SAMBA* O! W! Q: D7 v* N6 h$ V) }
1222442 CONSTRAINT_MGR UI_FORMS Duplicate pin pairs appear in DiffPair
6 F& }& _6 {3 t; v" ?- x1223175 CONCEPT_HDL CONSTRAINT_MGR Schematic crashes when opened
F1 c" ? {: E3 J/ X) m1 q1223533 ALLEGRO_EDITOR GRAPHICS Why the through pins for STEP models are shown at an offset when viewed in 3D inside Package Symbol?4 k. ?, p- z) Q ^" h/ \
1223680 CONSTRAINT_MGR ECS_APPLY Improve ECSet mapping by allowing user to address ambiguity of Parts6 o* N: C h" v
1224156 SIG_INTEGRITY SIGWAVE Exporting spreadsheet with filter Subitems in SigWave exports all waveforms
a7 V0 U8 _1 Z" d1224417 ALLEGRO_EDITOR PLOTTING Hidden font pattern is not showing correct in 16.5 version also 16.6 version.% n! a( }, L% P4 n/ V5 i9 r O
1224704 F2B DESIGNVARI There is no lock for the variant.dat file - multiple users can open the editor
6 d" n$ k8 y/ X1224968 ALLEGRO_EDITOR INTERACTIV Delete >(RMB click) Cut> Snap Pick to>off grid loction does not work for lines.' S2 s/ e- X7 Y& G% C/ v
1224982 CONCEPT_HDL PDF commandline publishpdf does not work when there are spaces in the path
' G/ R* C! X/ a+ D3 F6 @3 e1225114 CAPTURE GENERAL H-pins added after netgroup pin get color as of netgroup pin& e1 z! G) x! E" o7 y
1225494 CAPTURE DRC Different DRC results for Entire design and selection
; {1 P+ n5 W" \6 t% f1226153 ALLEGRO_EDITOR INTERFACES Export STEP should include PART_NUMBER property
1 u/ {" c$ a1 t% Q8 A4 F5 U1226235 ALLEGRO_EDITOR EDIT_ETCH Enhancement to include Pin_delay of descrete forming Xnet8 w# e' H. M* ]4 V$ |0 H+ n3 |) Y
1226372 CAPTURE GENERATE_PART ENH: Functionality to add pin spacing in New Part From Spreadsheet
0 {# F/ {9 r% T0 p7 g7 _1226477 CONCEPT_HDL CORE DE HDL縮 `Allowed Global Shorts? function is inconvenient for Global Signal
4 F( O. e8 z* M+ f1226813 SIP_LAYOUT LEFDEF_IF ERROR SPMHLD-120 when importing a DEF file. Request to increase the number of characters/line in a .cml file
# m$ Q2 E$ e; m' J* o: ]1227453 ALLEGRO_EDITOR SHAPE Addition of Fillet generate Pin to Shape Spacing DRC errors and DBDOCTOR errors4 @% K; u0 T4 G3 O
1227461 ALLEGRO_EDITOR SHAPE Sliding a cline for certain net changes the thermal relief connects for pins connected to another net from 4 to 5,6,7,8
% R7 y! R/ f) d1227469 CIS DBC_CFG_WIZARD Oracle Views not visible on Step2 of CIS Configuration, p4 P& d/ K4 p \. C+ |
1227780 CAPTURE ANNOTATE Inconsistent behaviour when annotating heterogeneous part4 ]7 T2 x2 W* [- y' j! L
1227831 CONCEPT_HDL CORE Pin text and H-block name in upper case/ G) ]8 y2 y/ n+ a8 k
1227954 CONCEPT_HDL OTHER supress check for global signals when wires are unconnected to pins
: s c/ u1 s' e/ d1228190 ALLEGRO_EDITOR OTHER Unable to close the 'usage' window during license selection
' x3 k( h. t" n& Q1228899 CONSTRAINT_MGR INTERACTIV Export/Import constraints in "overwrite" mode from same design shows different results when imported second time.( O$ f9 _4 Z* o) i7 q/ Q
1228934 ALLEGRO_EDITOR EDIT_ETCH The "View Active Layer" option like the Board Station should be provided for dynamic layer visibility.6 T/ @3 B8 S U* U ~( [3 T
1229316 ALLEGRO_EDITOR EDIT_ETCH When routing with Hug only enabled we were able to route through other routes(sometimes Hug).4 p7 l1 t7 J- n3 R
1229545 CONSTRAINT_MGR OTHER Allegro indicate bundle scheduled nets in CM( s& Q9 `5 I$ H
1230056 ALLEGRO_EDITOR GRAPHICS Bug: 3D View of Mechanical Symbol with the drill hole defined
) g8 v- V l+ z! l6 W1230432 CONCEPT_HDL CORE No Description information in BOM9 f: |+ ?$ Y+ x' S, |' G
1231148 F2B DESIGNVARI The variant.dat file is not updated with library PTF changes
+ |2 {; A/ M+ n/ B. o/ y1231625 F2B DESIGNSYNC VDD at command line needs to support sch2sch and test variable to write out report files1 Y' z+ x9 J! K/ r6 L. K
1231697 CONCEPT_HDL CORE If any locked files exist force a pop-up dialog restricting certain commands
) v6 p6 R0 A6 I1231767 CONCEPT_HDL OTHER Unable to find under the search options single bit vector nets, s7 }9 d$ f8 t/ _3 Y8 z
1231961 ALLEGRO_EDITOR SHAPE Shapes not updating to smooth unless we use force update and as a result false DRC's appear in board.
$ m( D& W g' [/ t+ k: I f1232100 CONCEPT_HDL SKILL Unable to execute the SKILL commands in viewer mode
, y( Y6 z+ M6 p1232336 CONSTRAINT_MGR CONCEPT_HDL cmFeedback takes 5hrs to complete during Import Physical* g& A. x5 w$ }* k' N+ |! B
1232710 F2B DESIGNVARI Dehdl crash while moving component in variant viewer mode
% _# z/ P3 Q& g0 ?1233894 F2B PACKAGERXL The page data is missing in the pst* and PCB files
4 B: z: {! ]# S) a! A* ^1235785 CONCEPT_HDL CREFER cref_from_list custom text is not subsitituted in complex hierarchy
6 Z: [ \0 }1 m7 l/ j& U; B1235928 CAPTURE SCHEMATIC_EDITOR OleObject modifications not saved4 {8 k8 W% h, a% X9 M
1236065 CAPTURE PART_EDITOR Mirrored part after being edited get pin name locations incorrect7 \( O: E; _ [
1236071 ALLEGRO_EDITOR SHAPE Airgap for Octagonal Pads ignores DRC Value when Thermal set
9 F/ A9 p6 r6 C; ^; R1236072 CONCEPT_HDL CORE Page 122 cannot be saved as logical page 119 has different page mapping in connectivity data and schematic
! X. j7 ^' H# j# @1236161 CONCEPT_HDL CORE Import Design shows the current project pages
# Y3 p \4 @+ X% R1 w: `1236432 ALLEGRO_EDITOR PADS_IN pads_in doesnot translate via and shape in some instances.
! A/ {2 i7 \/ m5 }" h1236557 CONCEPT_HDL PDF Running Publish PDF on command line in linux doesn't output progress until completion
; z r5 x4 D7 z+ z1236589 CONCEPT_HDL PDF Enhancement license failure error should appear in pdfpuplisher log file
* @5 N% C( ]* ]8 n1236644 ALLEGRO_EDITOR EDIT_ETCH create fanout deletes shape
3 V8 ?4 Z' v" x9 @$ }/ c: X% C* u1236689 ALLEGRO_EDITOR GRAPHICS Graphics displays extraneous lines when panning or zooming* ^6 w+ r' k; c
1236781 F2B PACKAGERXL Export Physical produces empty files
8 x% r. n, {6 P$ Y1237331 PSPICE ENVIRONMENT pspice.exe <cir file name> - hangs when run
5 M ?( j- @* L0 Z k' \1237400 CIS EXPLORER Capture hangs on 2 consecutive runs of `refresh symbol from lib? command
! Y$ G8 u" \ T6 k3 o' \1237437 CONCEPT_HDL CONSTRAINT_MGR CM Crash when saving after restore from definition6 }/ F$ ]6 o6 c8 Y! d
1237862 CONSTRAINT_MGR OTHER A way to remove the RAVEL markers from the Constraint Manager.
& g/ w% _1 K# t9 [+ S F @1238852 CAPTURE GENERAL signal list not updated for buses5 `; \+ M% Q. q6 k# D$ j
1238856 FSP DE-HDL_SCHEMATIC FSP schematic generation crashes
3 W w T0 U! [" ^ D% u1239079 ALLEGRO_EDITOR INTERACTIV The 16.6 Padstack > Replace function leaves old padstack.
" h6 L$ e0 a2 i, m1239706 CONSTRAINT_MGR ANALYSIS The reflection result on a differential signal in the CM when Measurement location is DIE) ]1 z5 B4 U: K* E% R, E' U) i
1239763 PSPICE PROBE Cannot modify text label if right y axis is active
! P: S0 Q" a) C; \9 `. L1240276 ALLEGRO_EDITOR GRAPHICS Printing to PDF from SigXp is giving unreadable images& W9 C; c- p8 _
1240356 CAPTURE IMPORT/EXPORT Can縯 import SDT schematic to Capture.) m) Z5 s0 V6 S1 D7 W c# l! {' h
1240502 F2B PACKAGERXL Corrupt cfg_package does not stop PackagerXL from completing. [1 b8 x5 e4 ~6 T- w8 r
1240607 ALLEGRO_EDITOR OTHER Footprint of screw hole got shift in DXF file( n0 }' w+ z3 G, c' a) o
1240670 ALLEGRO_EDITOR PLACEMENT Select multiple parts and Rotate makes them immovable1 y6 U; v, n8 u; M P* X. J
1240773 CAPTURE DRC DRC check reports error for duplicate NetGroup Reference in complex hierarchy1 ]$ d3 j+ P" I. f4 M, k% y
1240845 SIG_EXPLORER EXTRACTTOP Narrowband via models for Mirrored BB Vias not extracted in in the interconn.iml and this gives bad ringing in waveforms
9 d g" U4 F# u' B1 ?1241634 ALLEGRO_EDITOR OTHER Netshort for pad-pad connect not working
! i" W5 H! M! N$ [' L1241776 CONCEPT_HDL CORE In hierarchal design not all pages are getting printed.
+ e1 j7 p8 g5 s& q1241788 CONSTRAINT_MGR CONCEPT_HDL Issues with changing focus in Constraint manager using keys on keyboard( y, A% F1 b6 K- M$ I7 o% Q& \" a& c
1242683 ALLEGRO_EDITOR INTERACTIV Color View Save replaces file without warning
' f1 \" h/ {/ R1242818 ALLEGRO_EDITOR PLACEMENT Placement edit mirror option places component on wrong side/ R, X+ z; s8 u9 Y& Y4 W) U& [
1242847 ALLEGRO_EDITOR GRAPHICS Need an option to suppress Via Holes in 3D Viewer, c9 u9 ^* k* N, d! m9 q5 C( p
1242923 ADW COMPONENT_BROWSE UCB reports Missing From DB only after selecting the Row in the search results# W/ {0 Y7 L" p( j* C3 D
1243609 CONCEPT_HDL CORE autoprop for occurrence properties
" C6 d8 e0 y5 i8 }& z, t) y* e1243682 F2B DESIGNVARI after undocking variant icon cannot be redocked back to GUI
3 w1 i7 r- X/ x( ` L1243686 ALLEGRO_EDITOR GRAPHICS Invoking Edit->Text, the infinite cursor disappears until edit mode is changed.
6 P, S: p0 e% m" j j& m" {1243715 CAPTURE PART_EDITOR Pin name positioning get changed after rotating or mirroring- F7 h* n; w+ y
1244945 CONCEPT_HDL PDF PDF Publisher does not include image when file is not located in the root folder+ G$ p0 O) s9 M8 j
1245568 CONCEPT_HDL CORE Dual unselect needed for wires attached to other net/source and property is not deselected when component is
5 U# z5 I5 v" y6 Y& y1245819 F2B PACKAGERXL wrong injected properties information passed during packaging of the design
. L# X$ l" r* u1 V$ @' N1245916 SCM CONCEPT_IMPORT Where does the folder location reside for DEHDL imported blocks?3 R9 s4 o# J. s8 L+ s% N/ U& t
1246347 CONSTRAINT_MGR CONCEPT_HDL DEHDL crash if environment variable path has trailing backslash character; K* h; l! S9 m& @2 J
1246896 ALLEGRO_EDITOR DFA DFA_UPDATE on Linux reports err message if the path has Upper case characters, V1 Q& D" D% Z i5 x: ~& ]
1247019 SIP_LAYOUT DIE_STACK_EDITOR SiP Layout - refresh/update symbols is mirroring the assembly drawing data on DIE that is placed ChipDown" M3 p; ?# ` b" \5 u% F9 I
1247037 CAPTURE LIBRARY_EDITOR Copy & Paste of library parts resets pin name and number
' ?. o% m P; ~ s: Y" C* N. K4 N1247089 CONCEPT_HDL CORE Group Align or Distribute > Left/Center/Right crashes DEHDL
: J& `- L4 X; }) `$ N- d3 ]5 L' o: h1247163 CONCEPT_HDL PDF Physical Net Names in PDF not maintained8 o3 i: F) n- e' H7 r5 [' J0 a z
1247462 CONCEPT_HDL CORE Text issue while moving with bounding box
4 B0 C" Y, w4 F% d' P: t* n5 k1247464 ALLEGRO_EDITOR UI_FORMS When using the define B/B via UI the end layer dropdown arrow is partially covered8 m& L% [2 T3 D! m) s3 R4 K0 A
1249063 CONCEPT_HDL CONSTRAINT_MGR CM and SigXP doesn縯 respect PACK_IGNORE at components
2 |6 u' |/ M' ?9 B7 b6 Z) c9 S1250270 CONCEPT_HDL CORE Part Manager Update places wrong parts
3 u5 H# a) O8 W3 `1251206 ALLEGRO_EDITOR ARTWORK Aperture command cannot create appropriate aperture automatically from design.
" C: Q: n/ O5 M. o6 x1251356 ALLEGRO_EDITOR INTERFACES Some STEP models are missing in 3D view of footprint, although all components have STEP model mapped in footprint5 q' B5 j& u+ t" W8 ~5 n0 W# Y) M
1251845 ALLEGRO_EDITOR EXTRACT Crosshatch arcs do not extract correctly
6 ]4 ]4 u/ G6 I- \8 ]; b1252143 APD OTHER When using the beta "shape to cline" command the tool is removing the shape instead of converting it.
. U6 E+ i6 H3 i" O* e1252737 SIP_LAYOUT OTHER SiP Layout - Option to create shapes from Pins for WLP wafer level packaging technologies9 z$ S- b" K- H$ l, v
1253424 SCM SCHGEN Export Schematics Crashes System Architect
| F1 ~3 c8 C# f* M1253508 ALLEGRO_EDITOR INTERFACES Bug - Export IPC2581 exports Crosshatch shapes as filled- m5 \- F D! j! |+ ?5 S: r/ Y
1253554 SIP_LAYOUT OTHER SiP Layout - Add Netlist Spreadsheet export to SiP layout to help with connectivity auditing
7 d2 @4 I+ b5 E5 W: L" D5 S6 G6 }1254578 SPIF OTHER Specctra crash with Error -1073741819 for Auto router
0 H2 K, V6 K% I1254637 ALLEGRO_EDITOR DRC_TIMING_CHK adding nets to a net group causes constraint assignment error
8 G7 R8 L$ g: m1 u! |2 e* n, _1254676 GRE IFP_INTERACTIVE Rake Lines disappear when Auto-Interactive Breakout is enabled.
6 Q2 a8 @* N% K4 Q) K- J1255067 SIG_INTEGRITY REPORTS Allegro hangs on Net Parasitc Report generation
- r# e0 y3 r. i! y2 e, J8 Y6 o1255267 ALLEGRO_EDITOR SKILL axlDBGetPropDictEntry does not return a list of all objects/ \' s4 h' A0 Y. ?4 u( J
1255383 SIP_LAYOUT IC_IO_EDITING cant move bumps or driver in app mode0 e+ m9 R9 z% @0 m
1255703 ALLEGRO_EDITOR SKILL axlCNSSetPhysical and axlCNSGetPhysical return nil if a constraint set name is provided
/ ~! V, G( |- y9 c# @$ _! z1255759 ALLEGRO_EDITOR INTERFACES Change the silkscreen OUTLINE from layerFunction DOCUMENT to layerFunction BOARD_OUTLINE
- l1 p4 U4 [ m5 p; m1256457 CONCEPT_HDL CONSTRAINT_MGR Extracting a XNet from CM crashes the tool
* |4 M/ Z9 h% e' f; C; W1256597 GRE CORE Allegro GRE crashes while running Plan Spatial, on a particular design5 ~6 b5 [" Q" k
1256650 ASI_PI GUI PFE - Cannot generate model file error when using company decap library/ g* _/ l! m3 ]0 V, \
1256837 SIP_LAYOUT DIE_EDITOR Open and close of die editor takes too long
9 Y0 w2 ]+ k- K% h1257732 CONSTRAINT_MGR OTHER Bug - Export Analysis Results in CM makes Allegro crash
: Y% f. p) B* s) X% Y1257755 ALLEGRO_EDITOR OTHER Editing time in Display > Status seems to be logging wrong time- ^" B4 G8 ]' D" e5 _
1258029 APD WIREBOND The bondwire lost after import the wire information
8 j# F0 {* X9 U0 y s }3 G6 Y1258979 APD NC NC Drill: There is difference of number of drills.
' g8 e5 J9 j% o7 `! m1259484 SIP_LAYOUT OTHER SiP - calc min airgap calculate minimum airgap beta feature improvement
6 V8 P i/ C) n. A+ s. t1259677 CONCEPT_HDL CORE hier_write -forcereset cause component prop change." S3 L4 a% C, |7 ^9 g+ u9 F
1259913 ALLEGRO_EDITOR UI_FORMS Unable to save setting of "use secondary step models in 3D viewer"1 L1 ]3 A; }) h" O
1261758 ALLEGRO_EDITOR EDIT_ETCH Auto Interactive Delay tune (AiDT) is deleting clines
: s0 F$ ]1 m! z7 S/ \7 e. [7 D$ C1262543 ALLEGRO_EDITOR MANUFACT merge shape results in moved void, i9 ^+ I& n2 n6 D$ C8 B9 z
1264767 ALLEGRO_EDITOR DRC_TIMING_CHK XNET is choosing to resolve to a different name from 16.5 to 16.6 and is causing constraint loss$ ^- v$ @- B% R9 T# p, |$ G$ _
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发表于 2014-4-26 15:15
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发表于 2014-4-27 21:59
