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Cadence SPB 16.5下载地址（Hotfix更新至044）2 s- g; S8 d, n; x) t; u) V
6 V8 Y# u1 i1 r. ?/ \4 @. [Cadence最新版软件SPB 16.5及其Hotfix下载链接如下：# s/ O! q1 f1 D. q+ G" I
http://dl.vmall.com/c0sfvdb4yy) Q5 W; @' V b" \2 D* h% e
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Hotfix中只需要安装最新的版本即可。: m: \' `5 O8 s' h0 A, x
, Y( I& w5 ~5 m$ ODATE: 06-7-2013 HOTFIX VERSION: 044# _- c" J+ W Z
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7 N# A& S+ v* E! T/ ECCRID PRODUCT PRODUCTLEVEL2 TITLE8 v6 v& z8 B4 Y I3 E2 m4 u* |
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1055338 SIP_LAYOUT DRC_CONSTRAINTS Soldermask to Via drcs on bondfingers" ]' l( ]) N" ^, Y+ E$ a/ H3 |
1084716 ALLEGRO_EDITOR OTHER Getting an MPS error when updating CM from SigXplorer( F/ [+ {* Y" }' |/ @5 W6 A+ J
1104145 ALLEGRO_EDITOR SCHEM_FTB User defined properties do not appear in PCB' M8 Y, d8 Q J
1106116 FLOWS PROJMGR view_pcb setting change was cleared by switching Flows in projmgr.
: W5 r8 z1 N( x4 T1106900 CONCEPT_HDL COMP_BROWSER Component Browser performance utility should honor CPM directives for include and exclude PPT
6 a" ^. w) F0 ~1110323 APD DXF_IF DXF out is offsetting square discrete pads.
. y4 W& K" C, Q; p6 j, Q2 R# b1119007 CONCEPT_HDL CORE PDF Publish of schematic creates extremely large PDF files
% l8 I: v1 a- W: @4 A1 S1121020 FSP MODEL_EDITOR Cut-Paste from Excel causes empty cell in Rule Editor
6 |9 o. n+ z) [' m: j7 O1121353 ALLEGRO_EDITOR INTERACTIV Local env setting will change after saving and reopening.
: q$ S3 a; G0 c3 h* q4 U& p1122781 CONCEPT_HDL CORE cfg_package is generated for component cell automatically- ~7 m% I) }9 P/ U7 C9 M3 o5 B
1122909 CONCEPT_HDL CORE changing version replicates data of first TOC on 2nd one J" n$ I4 g, ~+ g, H* k
1123581 ALLEGRO_EDITOR MANUFACT Dimension Line gets changed on board9 ?- m" ~; ~! Z2 S$ i- H& p
1124544 CONCEPT_HDL CORE About Search History of find with SPB16.51 M6 {- Q& U1 `2 ?9 E
1125366 CONCEPT_HDL CORE DE-HDL craches during Import Physical if CM is open on Linux
0 n' b( A( a7 y$ z7 ]& g3 y1125628 CONCEPT_HDL CORE Crash on doing save hierarchy7 a, c( i* d2 S" A0 B+ g3 _
1126182 ALLEGRO_EDITOR DRC_CONSTR Shape fillet DRC in same net thru via to thru via was removed after update DRC., V$ O5 _; C; v3 b) l
1130945 SCM SCHGEN SCM Export Schematic does not copy all cells in the library. ^* }; \( M- l& \7 D1 K; n& p
1131567 CONCEPT_HDL OTHER Lower case values for VHDL_MODE make genview use pin location to determen direction.
' i6 L% [; Z/ H1131650 ALLEGRO_EDITOR PLOTTING PDF Publisher doesnot display few component defination properties in Property parameters
6 K6 o' z6 [8 A+ I* r$ c6 O5 ~1131868 CONCEPT_HDL CONSTRAINT_MGR Many net-class constraints "fell off" the design after uprev and Import Design of GEP4
7 ?8 x2 H0 ^5 r8 H1132457 CONCEPT_HDL CORE The schematic never fully invokes and has connectivity errors.; G4 w9 y! d5 Z* S
1132575 CONCEPT_HDL CORE 2 pin_name were displayed and overlapped by spin command.6 j- z. B, S1 p7 n9 r" @6 ~. c
1132638 ALLEGRO_EDITOR DFA 'dfa_update' crashes when running the utility on the attached foder.* e( u) B, @. \5 ]# `6 y' Q
1133677 CONCEPT_HDL CORE Cant delete nor reset LOCATION prop in context of top
& t3 M# ~$ @& O: O9 x% i1133791 CONCEPT_HDL CORE Cant do text justification on a single selected NOTE in Windows mode.( v [8 `3 ~( N) C/ l2 t
1134083 CONCEPT_HDL OTHER Published PDF file's hyperlinks do not work fine when user use double digits partitions for page Border.
) i, O Z2 z8 f X$ Y1134761 CONCEPT_HDL CORE Why does Mouse Pointer/Tooltip display LOCATION instead of $LOCATION property! O$ J7 C; r( R
1138586 ADW MIGRATION design migration does not create complete ptf file for hierarchical designs9 n$ J) D' f' Z$ `, F& b# Y
1139376 CONCEPT_HDL CORE setting wire color to default creates new wire with higher thickness2 x" ?- T' H6 \7 I
1141300 CONCEPT_HDL CORE DE HDL hier_write save hierarchy log reports summarizes Successfully saved block x while block was skipped
6 _4 A" J+ e' {- z9 B" a1142876 ALLEGRO_EDITOR SHAPE No DRC error when airgap between place bounds exactly zero' |2 ?0 W/ V! c
1142884 ALLEGRO_EDITOR OTHER Boolean type user defined property doesn't export to the PDF
: e! Y9 Y5 K5 Z1145112 CONCEPT_HDL CORE Warning message: Connectivity MIGHT have changed/ w. q0 |3 h9 X, v$ j9 ]
1145235 CONCEPT_HDL CONSTRAINT_MGR DEHDL CM gives error when trying to launch SigXP
' _: F1 v1 J) ^1145253 CONCEPT_HDL CORE Component Browser adds properties in upper case
$ `# e- B8 x. `1145284 CONCEPT_HDL CORE Publish PDF crashes DE HDL+ e5 {5 M+ |. l4 `/ ?
1145333 ALLEGRO_EDITOR SHAPE SHAPE boundary may not cross itself. Error cannot be fixed.
* A" _0 p, N3 @3 w* _1145856 ALLEGRO_EDITOR DRC_CONSTR DRC Line to Thru Pin appear while Fillet be added
y# h) n' K' N( e, g) o1146287 PCB_LIBRARIAN CORE PDV expand pins and change origin sets coordinates for few pins wrong and places pins on top of each other after collaps) i, e9 Z. E7 X5 X" y' n9 h) b; F
1146728 F2B PACKAGERXL DCF with upper and lower case values on parts causes pxl to fail7 M9 k P: x* N1 G
1147326 CONCEPT_HDL CORE HDL crashes when trying to reimport a block |
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发表于 2013-6-17 08:20
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