|
|
本帖最后由 lvsy 于 2014-4-16 10:05 编辑 * \, M5 o8 n: u1 k
2 j3 S! [ V/ X) }1 U, C
可以！对于Altera的FPGA，JTAG接口不是VCCIO供电的，它有专用的电源VCCPD，VCCPD的电压不能小于VCCIO。
7 S% G1 O- U% i
% d8 R' l1 t- ^如果是xilinx的FPGA，7系列也是可以的。设置CFGBVS管脚，接GND。8 h0 j: `: w+ B |4 z! Z" I/ \
+ W, [& [$ ^" w M9 s/ c
The 7 series devices support configuration interfaces with 3.3V, 2.5V, 1.8V, or 1.5V I/O. The. k% c2 ^, f* h3 q: b* F$ S' V% H
configuration interfaces include the JTAG pins in bank 0, the dedicated configuration pins
) N, D' f& a0 V% Nin bank 0, and the pins related to specific configuration modes in bank 14 and bank 15. To
/ M8 d/ ^# _1 v( wsupport the appropriate configuration interface voltage on bank 0, bank 14, and bank 15,
; I; a2 t V3 M3 cthe following is required:" Y$ |, G$ D+ {6 g
• The configuration banks voltage select pin (CFGBVS) must be set to a High (VCCO_0)
3 r- R& J3 R7 L: ~. n8 Tor Low (GND) in order to set the configuration and JTAG I/O in banks 0, 14, and 15
* a1 R1 {' u; ?& i" q: Lfor 3.3V/2.5V or 1.8V/1.5 operation, respectively. When CFGBVS is set to Low for
r% o, W" |- b& @2 [2 R4 D+ M- e; m8 e( k1.8V/1.5V I/O operation, the VCCO_0 supply and I/O signals to bank 0 must be 1.8V: [8 M/ E. d6 F8 Y B
(or lower) to avoid device damage. If CFGBVS is Low, then any I/O pins used for
3 H# D' {! g8 v2 ^9 w2 @9 z' Vconfiguration in banks 14 and 15 must also be powered and operated at 1.8V or 1.5V.
% y1 x+ S9 l/ m+ ]# {7 ` |
|
/1 
发表于 2014-4-15 18:32
QQ好友和群
QQ空间
腾讯微博
腾讯朋友
微信
收藏
支持！
反对！
楼主