I think you need to check the spd file at high desity connection region for Power and Gnd net plane, $ y; J( B- [# c$ J: B; ], gbecause spd file maybe have big clearance on gnd & power plane cause the Open isssue but the layout file is still correct without open issue (or big clearance inner plane layer). please zoom in at high desinty region to check whether power or gnd plane is open issue. 2 s$ P6 z4 `: T5 z( G% i
) w/ M# U! X5 A+ O$ Y y
this case is flip chip substrate case right ?
/1 
发表于 2013-10-16 17:42
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