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Cadence SPB 16.5下载地址（Hotfix更新至044）; |/ P* q6 i4 Y, Z' E
* J( _( x/ A% w: FCadence最新版软件SPB 16.5及其Hotfix下载链接如下：8 W# E3 `( U. {+ s. D1 L
http://dl.vmall.com/c0sfvdb4yy
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Hotfix中只需要安装最新的版本即可。
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DATE: 06-7-2013 HOTFIX VERSION: 044
0 g- e0 R3 v9 \, m. g& R- T* k+ A===================================================================================================================================2 n% n, i3 t. X3 _, g8 U8 [- f
CCRID PRODUCT PRODUCTLEVEL2 TITLE
$ v0 D$ [/ b1 n5 a) l: s% D9 d$ J===================================================================================================================================
! ?) b4 D/ X" } v4 T1055338 SIP_LAYOUT DRC_CONSTRAINTS Soldermask to Via drcs on bondfingers# C! }& x# T: x. \. x# V' r" @' c
1084716 ALLEGRO_EDITOR OTHER Getting an MPS error when updating CM from SigXplorer$ n& g8 K; X: r! l
1104145 ALLEGRO_EDITOR SCHEM_FTB User defined properties do not appear in PCB
- f, u9 ?$ f1 A8 V1 Z5 ^1106116 FLOWS PROJMGR view_pcb setting change was cleared by switching Flows in projmgr.5 u; K" r. F& ]* S5 U* b
1106900 CONCEPT_HDL COMP_BROWSER Component Browser performance utility should honor CPM directives for include and exclude PPT
) _& K1 q. p9 k% f5 p$ |5 C1110323 APD DXF_IF DXF out is offsetting square discrete pads.
, X, C! I( D6 W2 S8 K# R# ?- ?7 [1119007 CONCEPT_HDL CORE PDF Publish of schematic creates extremely large PDF files1 L. M9 U! S" A/ p2 z
1121020 FSP MODEL_EDITOR Cut-Paste from Excel causes empty cell in Rule Editor* `9 U7 \& | q& E1 y: f
1121353 ALLEGRO_EDITOR INTERACTIV Local env setting will change after saving and reopening.
H- N# m% ~: o. t( s, B% a1122781 CONCEPT_HDL CORE cfg_package is generated for component cell automatically7 [2 F* B& W0 c7 _
1122909 CONCEPT_HDL CORE changing version replicates data of first TOC on 2nd one. t2 i& z p1 c# q7 C8 ?
1123581 ALLEGRO_EDITOR MANUFACT Dimension Line gets changed on board
0 R& f/ r8 K. u$ R& e& E c1124544 CONCEPT_HDL CORE About Search History of find with SPB16.5
* W; x$ ? j7 Z, s K1125366 CONCEPT_HDL CORE DE-HDL craches during Import Physical if CM is open on Linux
" v- n3 z! r! A. q8 @2 F6 f1125628 CONCEPT_HDL CORE Crash on doing save hierarchy
5 a& N$ G. {# N* Q1126182 ALLEGRO_EDITOR DRC_CONSTR Shape fillet DRC in same net thru via to thru via was removed after update DRC.
- r; R5 e* Z6 W1130945 SCM SCHGEN SCM Export Schematic does not copy all cells in the library
7 V; {: r3 Q8 c& m5 j4 Z) [1131567 CONCEPT_HDL OTHER Lower case values for VHDL_MODE make genview use pin location to determen direction.# n: g( a; x0 x: ^6 K
1131650 ALLEGRO_EDITOR PLOTTING PDF Publisher doesnot display few component defination properties in Property parameters$ S: a6 s! W7 P# ?. v- r
1131868 CONCEPT_HDL CONSTRAINT_MGR Many net-class constraints "fell off" the design after uprev and Import Design of GEP4
% P. x, s9 T' t1 H1132457 CONCEPT_HDL CORE The schematic never fully invokes and has connectivity errors.5 a9 z, M6 `' ?6 {
1132575 CONCEPT_HDL CORE 2 pin_name were displayed and overlapped by spin command.
! P$ G$ |" y+ W; ?* ~# F1132638 ALLEGRO_EDITOR DFA 'dfa_update' crashes when running the utility on the attached foder. L1 r% T0 F4 h4 \8 m2 A. v" \7 @2 N
1133677 CONCEPT_HDL CORE Cant delete nor reset LOCATION prop in context of top6 ~: V" t" G4 X3 x7 v9 H; k" X
1133791 CONCEPT_HDL CORE Cant do text justification on a single selected NOTE in Windows mode.8 o4 m& [& x# ?) f3 ^4 F
1134083 CONCEPT_HDL OTHER Published PDF file's hyperlinks do not work fine when user use double digits partitions for page Border.3 I% f, |' H" {8 g
1134761 CONCEPT_HDL CORE Why does Mouse Pointer/Tooltip display LOCATION instead of $LOCATION property
7 d' r: O1 c0 n7 z9 L( W# D+ F! s1138586 ADW MIGRATION design migration does not create complete ptf file for hierarchical designs: z l( r" _ Y2 I( \; L
1139376 CONCEPT_HDL CORE setting wire color to default creates new wire with higher thickness
) C; M2 X/ [; M& R- k- i4 _" c1 R1141300 CONCEPT_HDL CORE DE HDL hier_write save hierarchy log reports summarizes Successfully saved block x while block was skipped q3 q( x( @ ^# x
1142876 ALLEGRO_EDITOR SHAPE No DRC error when airgap between place bounds exactly zero
1 F4 f! U. Z. P( X( Q! M8 D9 w! ]1142884 ALLEGRO_EDITOR OTHER Boolean type user defined property doesn't export to the PDF* r+ o2 z7 z1 L4 A: C$ X' ~
1145112 CONCEPT_HDL CORE Warning message: Connectivity MIGHT have changed
2 N8 _2 t/ a) d( C1145235 CONCEPT_HDL CONSTRAINT_MGR DEHDL CM gives error when trying to launch SigXP' C! m- b& Z2 q7 n) \! J8 u
1145253 CONCEPT_HDL CORE Component Browser adds properties in upper case8 Q4 f4 H6 r! a! _( I8 x5 r+ d# ?
1145284 CONCEPT_HDL CORE Publish PDF crashes DE HDL" F6 L& y% k( ^
1145333 ALLEGRO_EDITOR SHAPE SHAPE boundary may not cross itself. Error cannot be fixed.& E+ R/ Q1 Z" L) X
1145856 ALLEGRO_EDITOR DRC_CONSTR DRC Line to Thru Pin appear while Fillet be added
+ ^# d# p' `) b( A# g, g* E" U1146287 PCB_LIBRARIAN CORE PDV expand pins and change origin sets coordinates for few pins wrong and places pins on top of each other after collaps q( \- J; v3 ^) T; o, M: M, _
1146728 F2B PACKAGERXL DCF with upper and lower case values on parts causes pxl to fail
- O' }, e% d( z/ T% I' l) `/ o1147326 CONCEPT_HDL CORE HDL crashes when trying to reimport a block |
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发表于 2013-6-17 17:16
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