There are Still Challenges at DC When More than 200 A is Distributed to Devices

zzchu · 发表于 2012-2-10 13:28

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在Eric Bogatin(Signal Integrity - Simplified的作者)的博客上看到的，DC的挑战仍然巨大啊。

“That’s a pretty cool benefit,” Phil Warwick, CTO of R&D Circuits, a leading edge circuit board manufacturer said at the 5-TA3 session at DesignCon 2012. He was referring to the use of 0.4 mm pitch BGA packages.

One advantage he’s identified is that differential vias with the typical drill hole size, on a 0.4 mm pitch, with surrounded return vias, results in a differential via impedance of about 85 to 120 Ohms. As long as the via stub is backdrilled, the thru part of the via will look pretty transparent, an advantage, Warwick says for 25 Gbps links.

But, the problem these higher density pitched create is narrow web for delivering the high currents required by large pin count ASICS and FPGAs. Some of the devices he builds boards for require 100 to 300 A at 0.85 v. In the narrow web between clearance holes in the power and ground planes, shoving 300 A causes hot spots which can burn out the board. “We will fry that web quickly,” Warwick said and backed up his comment with graphic images of splattered copper that used to be a narrow web.

To manage a low DC IR drop from the planes to the center of the package, Warwick has worked with chip and package designers to implement a new ball topology he calls “slats”. Rather than scatter the power and ground balls in a checkerboard arrangement, typically recommended to reduce the inductance in the PDN feed to the package, he suggests using grouped rows of power balls and ground balls, as shown in the figure above. This enables wide channels in the power and ground planes and low IR drop.

Temperature rise measurements on boards produced with this slat topology showed only a 20 degree rise with 200A of DC current.

Warwick suggests that while it is important to pay careful attention to specific board features to enhance 28 Gbps data paths, there are still important design tradeoffs to manage all the way down to DC. Understanding all the design-performance cost tradeoffs become increasingly important as the data rates, the pin counts and the power requirements all increase in leading edge designs.

shg_zhou · 发表于 2012-2-10 13:36

本帖最后由 shg_zhou 于 2012-2-10 13:41 编辑

DC直流分析不容忽视呀，IR压降分析，保证我们供电的稳定。过孔、导线宽度等都是我们考虑的范围。
Sigrity独有的感应线分析，可以保证电源芯片的采样反馈线位置准确。从而确保接收端电压稳定。

yawyw · 发表于 2012-2-10 17:02

最近确实有这个感觉
在最新的产品中有以前的设计方法1.5V的电压竟然有300mV的压降
电流越来越大了

zzchu · 发表于 2012-2-10 17:21

电流在增大，电压在减小，工程师的能力也要随之提高啊

zzchu · 发表于 2012-2-10 17:25

yawyw 发表于 2012-2-10 17:02 3 k4 g& T4 b9 z4 \& R/ r
最近确实有这个感觉3 d! z. Z" }* {+ U4 j8 z
在最新的产品中有以前的设计方法1.5V的电压竟然有300mV的压降" [9 G$ T; Y! \3 ~, U
电流越来越大了

有用仿真工具做过分析吗？

yawyw · 发表于 2012-2-10 17:59

zzchu 发表于 2012-2-10 17:25 . I7 ^% [1 d+ r) I: S. r8 [
有用仿真工具做过分析吗？

用Siwave做过DC Drop

shg_zhou · 发表于 2012-2-11 21:39

yawyw 发表于 2012-2-10 17:59 F* j, k4 X4 }$ G
用Siwave做过DC Drop

可以用用PowerDC哟，它在直流分析方面做的非常详细。
 对整个封装和板级的电源分配系统（PDS）提供直流压降（IR Drop）分析
 定位电流分布的热点区域，避免由此导致的系统问题
 优化电压调节模块（VRM）感应线的位置
 对封装和板级的每个电源/地网络进行快速的DRC检查
 分析不同器件位置上的关键电压分布和直流压降问题
 找到难于发现的，高阻抗的布线瓶颈区域
 调整对IR Drop敏感的封装和板上器件的位置
 布局布线前/后PCB或IC封装DC分析；
 彩色显示PCB各层的电压分布、平面电流分布和过孔电流分布；
 可仿真Lumped to Lumped，Lumped to Multiple，Multiple to Lumped以及Multiple to Multiple等各种形式的pin-to-pin电阻；
 还可仿真多端口的阻抗网络，并生成DC情况下相应的S-param模型和SPICE等效模型；
 多子板/多封装的IR Drop分析；
 流程化仿真，指导用户快速准确的完成整个仿真，而且用户可以定制自己特定的Workflow；
 高效的有限元（FEM）算法无需用户设定Mesh即可得到平面上精细而平滑的每一个位置上的电压、电流值；
 内置的Constraint management使仿真支持复杂设计的DRC检查；
 生成所有的电压、电流结果表格，并与预先设定的Constraints作比较；
 将DRC Marker反标回Allegro Layout文件。
 对电源分配系统的部分电阻和环路电阻进行分析，并生成SPICE电路模型
 分析直流问题比其他类似工具效率高很多

详细的电源分布，电流密度分布，高阻抗路径，过孔电流分析，IR_Drop超标提示，过孔电流超标，最佳感应线（电源芯片反馈线的采样点位置），3D电压电流分布。这些都是非常实用，有效的功能，保证直流电源设计最大裕量。

zilongjianke · 发表于 2012-2-13 10:08

PowerDC的功能还是蛮实用的

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There are Still Challenges at DC When More than 200 A is Distributed to Devices

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