请教四细分辨向电路的VHDL语言描述

孙泽华 · 发表于 2010-4-22 15:37

EDA365欢迎您！

您需要登录才可以下载或查看，没有帐号？注册

x

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity time4 is
port(ab : in std_logic_vector(1 downto 0);
      clk : in std_logic;
      pp,np : out std_logic);
end time4;
architecture one of time4 is
signal state : std_logic_vector(1 downto 0);
signal ab_1  : std_logic_vector(1 downto 0);
signal spp,snp : std_logic;
begin
  process(clk,ab)
  begin
  if(clk'event and clk='0') then ab_1<=ab;
  end if;
  end process;
  process(clk,state,snp,spp)
  begin
  if(clk'event and clk='1') then
   if(ab_1="00") then
   case state is
   when "10"=>state<="00";spp<=’1’;
   when "01"=>state<="00";snp<=’1’;
   when others=>state<="00";spp<='0’;snp<=’0’;
   end case;
   elsif(ab_1="01") then
   case state is
   when "00"=>state<="01";spp<='1';
   when "11"=>state<="01";snp<='1';
   when others=>state<="01";snp<='0';spp<='0';
   end case;
   elsif(ab_1="11") then
      case state is
      when "01"=>state<="11";spp='1';
      when "10"=>state<="11";snp='1';
      when others =>state<="11";--spp='0';snp='0';
      end case;
   else
      case state is
      when "11"=>state<="10";spp='1';
      when "00"=>state<="10";snp='1';
      when others =>state<="10";snp='0';spp='0';
      end case;
   end if;
  end if;
end process;
pp<=spp;
np<=snp;
end one;
程序在QII中老是错误，请大虾们帮帮小弟！