VHDL编译错误，请大家指教

Annhu · 发表于 2009-10-26 16:07

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本帖最后由 Annhu 于 2009-10-26 16:08 编辑

:) 下面的程序是一款CCD的驱动程序，clk1=2MHZ,enable主要是控制sh的周期是10us还是10ms icg的周期不变始终为10ms,delay用于控制sh、icg的延时0.5us。编译错误见最下方，小弟把clk和enable的位置换了一下即先判断clk1上升沿然后在判断enable问题就解决了，麻烦高手帮忙看一下这到底是什么原因呢？还有j就是程序的代码有没有可以优化的地方呢，谢谢大家！
--CCDshixu
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity divclk is
port(clk: in std_logic;
      start:in std_logic;
      enable:in std_logic_vector(1 downto 0);
      o_m_clk  out std_logic;
      o_sh,o_icg  out std_logic;
      stop out std_logic);
end divclk;
architecture behave1 of divclk is
constant halftime :std_logic_vector(3 downto 0):="0101";
signal divcounter: std_logic_vector(3 downto 0);--shizhong fenpinjishu
signal shcounter : std_logic_vector(13 downto 0);--tiaozheng sh zhouqi he zhan kong bi
signal icgcounter :std_logic_vector (14 downto 0);--tiao zheng icg zhouqi he zhan kong bi
signal delay :std_logic_vector(1 downto 0);--shixian ICG/SH de mai chong jian ge
signal clk1: std_logic;
begin
P1:process(clk,start)--24MHZ,12fenpin
begin
   if start='1' then
   clk1<='0';
   divcounter<="0000";
   elsif clk'event and clk='1' then
         if divcounter = halftime then
            clk1 <= not clk1;
            divcounter <= "0000";
         else
            divcounter <= divcounter + 1;
         end if;
      end if;
   o_m_clk <= clk1;
end process P1;
P2:process(clk1,start,enable)
begin
   if start = '1' then
      delay <="00";
      shcounter <= "00000000000000";
      icgcounter <= "000000000000000";
      o_sh <= '0';
      o_icg <='1';
      stop <= '0';
   elsif enable = "01" then
      if clk1'event and clk1='1' then
         if icgcounter <"100111000100000" then  -- 20000分频产生10ms的周期
            icgcounter <= icgcounter +1;
            if icgcounter <"000000000010100" then
               o_icg <= '0';
            else
               o_icg <= '1';
            end if;
         else
            icgcounter <= "000000000000000";
            stop<='1';
         end if;
         if delay = "01"  then
            delay <= "00";
            if shcounter < "00000000001001" then  -- delay用于产生ICG、SH的脉冲间隔0.5us,10us SH
               shcounter <= shcounter +1;
               if shcounter <"00000000000101" then  o_sh <= '1';
                  else o_sh <= '0';
               end if;
            else
            shcounter<= "00000000000000";
            end if;
         else
            delay <= delay +1;
         end if;
      end if;

   elsif enable = "10" then
      if clk1'event and clk1='1' then
         if icgcounter <"100111000100000" then  -- 10ms ICG
            icgcounter <= icgcounter +1;
            if icgcounter <"000000000010100" then
               o_icg <= '0';
            else
               o_icg <= '1';
            end if;
         else
            icgcounter <= "000000000000000";
            stop<='1';
         end if;
         if delay = "01"  then
            delay <= "00";
            if shcounter < "10011100010000" then  -- 2次10000分频delay用于产生ICG、SH的脉冲间隔0.5us,10ms SH
               shcounter <= shcounter +1;
               if shcounter <"00000000000101" then
                  o_sh <= '1';
               else
                  o_sh <= '0';
               end if;
            else
               shcounter<= "00000000000000";
            end if;
         else
            delay <= delay +1;
         end if;
      end if;
end if;
  end process P2;
end behave1;
Error (10821): HDL error at divclk.vhd(42): can't infer register for "stop" because its behavior does not match any supported register model
Error (10821): HDL error at divclk.vhd(42): can't infer register for "o_icg" because its behavior does not match any supported register model
Error (10821): HDL error at divclk.vhd(42): can't infer register for "o_sh" because its behavior does not match any supported register model
Error (10821): HDL error at divclk.vhd(42): can't infer register for "icgcounter[0]" because its behavior does not match any supported register
model
Error (10821): HDL error at divclk.vhd(42): can't infer register for "icgcounter[1]" because its behavior does not match any supported register
model
Error (10821): HDL error at divclk.vhd(42): can't infer register for "icgcounter[2]" because its behavior does not match any supported register
model
Error (10821): HDL error at divclk.vhd(42): can't infer register for "icgcounter[3]" because its behavior does not match any supported register
model
Error (10821): HDL error at divclk.vhd(42): can't infer register for "icgcounter[4]" because its behavior does not match any supported register
model
Error (10821): HDL error at divclk.vhd(42): can't infer register for "icgcounter[5]" because its behavior does not match any supported register
model
Error (10821): HDL error at divclk.vhd(42): can't infer register for "icgcounter[6]" because its behavior does not match any supported register
model
Error (10821): HDL error at divclk.vhd(42): can't infer register for "icgcounter[7]" because its behavior does not match any supported register
model
Error (10821): HDL error at divclk.vhd(42): can't infer register for "icgcounter[8]" because its behavior does not match any supported register
model
Error (10821): HDL error at divclk.vhd(42): can't infer register for "icgcounter[9]" because its behavior does not match any supported register
model
Error (10821): HDL error at divclk.vhd(42): can't infer register for "icgcounter[10]" because its behavior does not match any supported register
model
Error (10821): HDL error at divclk.vhd(42): can't infer register for "icgcounter[11]" because its behavior does not match any supported register
model
Error (10821): HDL error at divclk.vhd(42): can't infer register for "icgcounter[12]" because its behavior does not match any supported register
model
Error (10821): HDL error at divclk.vhd(42): can't infer register for "icgcounter[13]" because its behavior does not match any supported register
model
Error (10821): HDL error at divclk.vhd(42): can't infer register for "icgcounter[14]" because its behavior does not match any supported register
model
Error (10821): HDL error at divclk.vhd(42): can't infer register for "shcounter[0]" because its behavior does not match any supported register
model
Error: Can't elaborate top-level user hierarchy

Annhu · 发表于 2009-10-28 19:32

怎么没人理呢？

wang759153 · 发表于 2009-11-4 19:43

错误太多了得一步一步找一下是看不出来的所以没人里

pex857617729 · 发表于 2010-5-15 10:53

爱莫能助

alec4050 · 发表于 2012-2-24 20:35

这么长，自己慢慢找吧，细心点总能找出来的

alec4050 · 发表于 2012-2-26 13:58

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity divclk is
port(clk: in std_logic;
      start:in std_logic;
      enable:in std_logic_vector(1 downto 0);
      o_m_clk : out std_logic;
      o_sh,o_icg:  out std_logic;
      stop: out std_logic);
end divclk;
architecture behave1 of divclk is
constant halftime :std_logic_vector(3 downto 0):="0101";
signal divcounter: std_logic_vector(3 downto 0);--shizhong fenpinjishu
signal shcounter : std_logic_vector(13 downto 0);--tiaozheng sh zhouqi he zhan kong bi1 t: s2 {2 }8 h0 F1 o
signal icgcounter :std_logic_vector (14 downto 0);--tiao zheng icg zhouqi he zhan kong bi% d9 K0 \( Q* D7 ^- g0 Z* s# k
signal delay :std_logic_vector(1 downto 0);--shixian ICG/SH de mai chong jian ge7 o6 n3 \2 a1 H6 K
signal clk1: std_logic;
begin
P1:process(clk,start)--24MHZ,12fenpin
begin
   if start='1' then
      clk1<='0';
      divcounter<="0000";
   elsif clk'event and clk='1' then
         if divcounter = halftime then
            clk1 <= not clk1;
            divcounter <= "0000";
         else
            divcounter <= divcounter + 1;
         end if;
      end if;
   o_m_clk <= clk1;
end process P1;
P2:process(clk1,start,enable)
begin
   if start <= '1' then
      delay <="00";
      shcounter <= "00000000000000";
      icgcounter <= "000000000000000";
      o_sh <= '0';
      o_icg <='1';
      stop <= '0';
   elsif enable = "01" then
      if clk1'event and clk1='1' then
         if icgcounter <"100111000100000" then --20000....32767
            icgcounter <= icgcounter +1;
            if icgcounter <"000000000010100" then --20
               o_icg <= '0';
            else
               o_icg <= '1';
            end if;
         else
            icgcounter <= "000000000000000";
            stop<='1';
         end if;
         if delay = "01"  then
            delay <= "00";
            if shcounter < "00000000001001" then
               shcounter <= shcounter +1;
               if shcounter <"00000000000101" then  o_sh <= '1';
                  else o_sh <= '0';
               end if;
            else
            shcounter<= "00000000000000";
            end if;
         else
            delay <= delay +1;
         end if;
      end if;

   elsif enable = "10" then
      if clk1'event and clk1='1' then
         if icgcounter <"100111000100000" then
            icgcounter <= icgcounter +1;
            if icgcounter <"000000000010100" then
               o_icg <= '0';
            else
               o_icg <= '1';
            end if;
         else
            icgcounter <= "000000000000000";
            stop<='1';
         end if;
         if delay = "01"  then
            delay <= "00";
            if shcounter < "10011100010000" then
               shcounter <= shcounter +1;
               if shcounter <"00000000000101" then
                  o_sh <= '1';
               else
                  o_sh <= '0';
               end if;
            else
               shcounter<= "00000000000000";
            end if;
         else
            delay <= delay +1;
         end if;
      end if;
end if;
end process P2;
end behave1;

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VHDL编译错误，请大家指教

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