高速数字信号设计和高速互连

shuaiwang · 发表于 2017-7-6 14:49

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高速数字信号设计和高速互连
CHAPTER 1 Transmission Line Fundamentals.......................................... 1
Basic Electromagnetics.................................................................... 1
Electromagnetics Field Theory................................................... 1
Propagation of Plane Waves....................................................... 6
Transmission Line Theory............................................................. 10
Wave Equations on Lossless Transmission Lines.................... 11
Impedance, Reflection Coefficient, and Power Flow
on a Lossless Transmission Line......................................... 14
Traveling and Standing Waves on a Transmission Line ......... 16
Transmission Line Structures ........................................................ 18
Stripline ..................................................................................... 19
Microstrip.................................................................................. 20
Coplanar Waveguides ............................................................... 21
Novel Transmission Lines ........................................................ 22
References ...................................................................................... 26
CHAPTER 2 PCB design for Signal Integrity........................................... 27
Differential Signaling..................................................................... 27
Impedance ................................................................................. 28
Time Domain Analysis .................................................................. 31
Eye Diagram ............................................................................. 31
Jitter........................................................................................... 33
Frequency Domain Analysis.......................................................... 42
Spectral Content........................................................................ 42
Insertion Loss............................................................................ 44
Integrated Insertion Loss Noise................................................ 46
Return Loss ............................................................................... 49
Crosstalk.................................................................................... 51
Integrated Crosstalk .................................................................. 54
Signal-to-Noise Ratio................................................................ 55
Stack-Up Design ............................................................................ 58
Impedance Target (Routing Impedance) .................................. 59
PCB Losses ............................................................................... 61
Dielectric Loss .......................................................................... 62
Conductor Loss ......................................................................... 65
Crosstalk Mitigation through StackUp..................................... 68
Dual Stripline ............................................................................ 73
v
Densely Broadside Coupled Dual Stripline.............................. 84
Via Stub Mitigation .................................................................. 86
PCB Layout Optimization ............................................................. 95
Length Matching....................................................................... 96
Fiber Weave Effect ................................................................... 99
Crosstalk Reduction ................................................................ 101
Non-Ideal Return Path ............................................................ 107
Power Integrity........................................................................ 110
Repeaters ................................................................................. 111
References .................................................................................... 115
CHAPTER 3 Channel Modeling and Simulation.................................... 117
Transmission Lines ...................................................................... 117
Causality.................................................................................. 117
Checking for Model Causality................................................ 118
Causal Frequency-Dependent Model...................................... 120
Copper Surface Roughness..................................................... 121
Conductivity............................................................................ 126
Environmental Impact............................................................. 127
Model Geometries................................................................... 130
Corner Models......................................................................... 133
Ideal Assumptions: Homogeneous Impedance....................... 137
Ideal Assumptions: Crosstalk Aggressors .............................. 137
Transmitters.................................................................................. 138
IBIS Models ............................................................................ 138
Spice Voltage Source Model .................................................. 139
3D Modeling ................................................................................ 141
Ports/Terminals ....................................................................... 142
Model Analysis Settings ......................................................... 144
Plated-Through-Hole Via............................................................. 146
Model Techniques................................................................... 147
Pre-Layout Approximation ..................................................... 148
Pre-Layout Modeling .............................................................. 148
Post-Layout ............................................................................. 149
Connectors.................................................................................... 150
Connector Variability.............................................................. 150
Signal Selection....................................................................... 150
Separated Via Models............................................................. 152
Unconnected Pins.................................................................... 153
Physical Features..................................................................... 154
Design Optimization ............................................................... 154
Packages....................................................................................... 156
C4 Escape................................................................................ 158
vi Contents
Transmission Line................................................................... 158
PTH Via .................................................................................. 160
BGA Model............................................................................. 160
Signal Selection for 3D Package Structures........................... 161
References ....................................................................................161
CHAPTER 4 Link Circuits and Architecture .......................................... 163
Types of Link Circuit Architectures............................................163
Embedded Clock Architecture................................................ 163
Forwarded Clock Architecture................................................ 164
Termination ..................................................................................165
DC and AC Coupling.............................................................. 165
Termination Type.................................................................... 166
Termination Circuits ............................................................... 167
Termination Calibration Circuits............................................ 168
Termination Detection Circuits .............................................. 169
Transmitter ...................................................................................170
Transmitter Equalization......................................................... 171
Transmitter Data Path ............................................................. 173
Current-Mode Driver .............................................................. 174
Voltage-Mode Driver.............................................................. 177
Receiver........................................................................................179
Receiver Equalization ............................................................. 180
Receiver Data Path.................................................................. 182
Continuous-Time Linear Equalizer ........................................ 184
Decision Feedback Equalizer.................................................. 184
Data Sampler........................................................................... 186
Error Sampler.......................................................................... 186
Receiver Calibration ............................................................... 187
Receiver Adaptation................................................................ 188
Clock and Data Recovery............................................................190
Clock and Data Recovery Loop ............................................. 191
Phase Detectors....................................................................... 192
Forwarded Clock Receiver ..........................................................195
Delay-Locked Loop ................................................................ 195
Design for Test/Manufacture.......................................................195
Analog DFx Features .............................................................. 196
Digital DFx Features............................................................... 196
References ....................................................................................198
CHAPTER 5 Measurement and Data Acquisition Techniques............... 199
Digital Oscilloscope Measurement..............................................199
Real-Time and Equivalent-Time Sampling Scopes ............... 199
Contents vii
Bandwidth ............................................................................... 200
Scope Digital Filter Applications ........................................... 202
TDR Measurements ..................................................................... 204
De-skew Differential Pairs with TDR .................................... 205
Channel Characterization with TDR ...................................... 207
Return Loss Measurement with TDR..................................... 209
Vector Network Analyzer Measurement..................................... 211
What is VNA?......................................................................... 211
VNA Error Sources and Calibration....................................... 213
Full Two-Port SOLT Calibration Procedure .......................... 217
Example of Measurement Using VNA................................... 217
VNA Measurement Procedure................................................ 218
References .................................................................................... 219
CHAPTER 6 Designing and Validating with Intel Processors............... 221
Designing Systems with Intel Devices........................................ 221
Interconnect Model ................................................................. 221
Equalization Models ............................................................... 223
Automatic Equalization Adaptation ....................................... 225
Performance Analysis ............................................................. 227
Solution from Design of Experiments.................................... 232
Solution from Typical Models................................................ 234
System Validation with Intel Devices ......................................... 237
Power-on Preparations ............................................................ 237
Types of I/O Design Validation ............................................. 238
System Margining Validation Overview................................ 239
DDR System Margining Validation ....................................... 244
High-Speed Serial I/O Margining Validation ........................ 246
Low-Margin Debug Guidance ................................................ 249
Summary ...................................................................................... 250
References .................................................................................... 250
Index .............................................................................................................

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